Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 940
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T106 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.571748681 Feb 28 04:23:32 PM PST 24 Feb 28 04:23:34 PM PST 24 76618597 ps
T757 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.142998107 Feb 28 04:23:33 PM PST 24 Feb 28 04:23:34 PM PST 24 113616587 ps
T758 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3360957656 Feb 28 04:23:58 PM PST 24 Feb 28 04:23:59 PM PST 24 16868972 ps
T759 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2809958595 Feb 28 04:25:52 PM PST 24 Feb 28 04:25:55 PM PST 24 448903049 ps
T760 /workspace/coverage/cover_reg_top/13.gpio_intr_test.1851183529 Feb 28 04:23:59 PM PST 24 Feb 28 04:24:00 PM PST 24 12225440 ps
T761 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1362464483 Feb 28 04:23:38 PM PST 24 Feb 28 04:23:39 PM PST 24 32807240 ps
T762 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3516243737 Feb 28 04:23:57 PM PST 24 Feb 28 04:23:58 PM PST 24 20744216 ps
T763 /workspace/coverage/cover_reg_top/8.gpio_intr_test.4291862687 Feb 28 04:23:55 PM PST 24 Feb 28 04:23:55 PM PST 24 109314817 ps
T764 /workspace/coverage/cover_reg_top/11.gpio_intr_test.946297121 Feb 28 04:23:40 PM PST 24 Feb 28 04:23:42 PM PST 24 27629399 ps
T765 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.696521387 Feb 28 04:27:28 PM PST 24 Feb 28 04:27:31 PM PST 24 149726684 ps
T766 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2849331525 Feb 28 04:23:45 PM PST 24 Feb 28 04:23:48 PM PST 24 377500904 ps
T767 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3250114859 Feb 28 04:27:28 PM PST 24 Feb 28 04:27:29 PM PST 24 18597111 ps
T768 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1295923463 Feb 28 04:24:03 PM PST 24 Feb 28 04:24:04 PM PST 24 14224199 ps
T769 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.16423022 Feb 28 04:23:42 PM PST 24 Feb 28 04:23:49 PM PST 24 180846047 ps
T89 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1572598325 Feb 28 04:27:13 PM PST 24 Feb 28 04:27:16 PM PST 24 14905873 ps
T770 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.904983765 Feb 28 04:23:42 PM PST 24 Feb 28 04:23:45 PM PST 24 180275605 ps
T771 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3624801230 Feb 28 04:23:42 PM PST 24 Feb 28 04:23:44 PM PST 24 59679490 ps
T772 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.460000804 Feb 28 04:23:41 PM PST 24 Feb 28 04:23:45 PM PST 24 67260435 ps
T773 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3518104742 Feb 28 04:23:39 PM PST 24 Feb 28 04:23:40 PM PST 24 72139051 ps
T86 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2402375702 Feb 28 04:23:34 PM PST 24 Feb 28 04:23:35 PM PST 24 60220196 ps
T87 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2480231817 Feb 28 04:23:56 PM PST 24 Feb 28 04:23:57 PM PST 24 25139525 ps
T774 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.20266551 Feb 28 04:24:06 PM PST 24 Feb 28 04:24:07 PM PST 24 99705666 ps
T775 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3085336150 Feb 28 04:23:39 PM PST 24 Feb 28 04:23:40 PM PST 24 216074320 ps
T776 /workspace/coverage/cover_reg_top/34.gpio_intr_test.2627821148 Feb 28 04:24:09 PM PST 24 Feb 28 04:24:10 PM PST 24 134780126 ps
T777 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2770262400 Feb 28 04:23:36 PM PST 24 Feb 28 04:23:37 PM PST 24 15963756 ps
T778 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.4264319141 Feb 28 04:23:30 PM PST 24 Feb 28 04:23:31 PM PST 24 14846674 ps
T779 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3928638130 Feb 28 04:27:13 PM PST 24 Feb 28 04:27:16 PM PST 24 36712430 ps
T780 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.4040651983 Feb 28 04:23:37 PM PST 24 Feb 28 04:23:38 PM PST 24 107139224 ps
T781 /workspace/coverage/cover_reg_top/23.gpio_intr_test.2146001993 Feb 28 04:23:43 PM PST 24 Feb 28 04:23:45 PM PST 24 32930587 ps
T782 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2903635953 Feb 28 04:23:56 PM PST 24 Feb 28 04:23:58 PM PST 24 285391991 ps
T88 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1864482868 Feb 28 04:23:45 PM PST 24 Feb 28 04:23:46 PM PST 24 15874152 ps
T783 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.945225897 Feb 28 04:24:10 PM PST 24 Feb 28 04:24:10 PM PST 24 45849967 ps
T784 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3671878469 Feb 28 04:23:45 PM PST 24 Feb 28 04:23:47 PM PST 24 762725445 ps
T785 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2729085610 Feb 28 04:23:52 PM PST 24 Feb 28 04:23:53 PM PST 24 148993678 ps
T786 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1038580197 Feb 28 04:24:06 PM PST 24 Feb 28 04:24:07 PM PST 24 26175935 ps
T787 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3554624372 Feb 28 04:23:42 PM PST 24 Feb 28 04:23:44 PM PST 24 94570832 ps
T788 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.490194978 Feb 28 04:23:47 PM PST 24 Feb 28 04:23:49 PM PST 24 70010694 ps
T789 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2879512069 Feb 28 04:24:00 PM PST 24 Feb 28 04:24:00 PM PST 24 39526469 ps
T790 /workspace/coverage/cover_reg_top/5.gpio_intr_test.218273058 Feb 28 04:24:07 PM PST 24 Feb 28 04:24:07 PM PST 24 17453748 ps
T791 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.4263615115 Feb 28 04:23:37 PM PST 24 Feb 28 04:23:38 PM PST 24 145629059 ps
T792 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.4077258946 Feb 28 04:23:39 PM PST 24 Feb 28 04:23:40 PM PST 24 32531872 ps
T793 /workspace/coverage/cover_reg_top/49.gpio_intr_test.230944012 Feb 28 04:24:08 PM PST 24 Feb 28 04:24:09 PM PST 24 29680516 ps
T794 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1503354060 Feb 28 04:24:08 PM PST 24 Feb 28 04:24:09 PM PST 24 91080055 ps
T795 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2340565917 Feb 28 04:23:57 PM PST 24 Feb 28 04:23:59 PM PST 24 436318969 ps
T796 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3067616289 Feb 28 04:27:26 PM PST 24 Feb 28 04:27:27 PM PST 24 79927250 ps
T797 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3675382638 Feb 28 04:23:44 PM PST 24 Feb 28 04:23:46 PM PST 24 39523837 ps
T798 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1658228324 Feb 28 04:25:56 PM PST 24 Feb 28 04:25:57 PM PST 24 55727204 ps
T799 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.696945566 Feb 28 04:23:40 PM PST 24 Feb 28 04:23:42 PM PST 24 271886419 ps
T800 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3532310469 Feb 28 04:25:50 PM PST 24 Feb 28 04:25:50 PM PST 24 36920126 ps
T801 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2018980196 Feb 28 04:23:43 PM PST 24 Feb 28 04:23:45 PM PST 24 312251899 ps
T802 /workspace/coverage/cover_reg_top/37.gpio_intr_test.1635996232 Feb 28 04:24:05 PM PST 24 Feb 28 04:24:05 PM PST 24 145149657 ps
T803 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3274264536 Feb 28 04:23:30 PM PST 24 Feb 28 04:23:32 PM PST 24 31213999 ps
T804 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1199510145 Feb 28 04:23:39 PM PST 24 Feb 28 04:23:40 PM PST 24 85689242 ps
T805 /workspace/coverage/cover_reg_top/17.gpio_intr_test.1156248441 Feb 28 04:23:42 PM PST 24 Feb 28 04:23:45 PM PST 24 40838364 ps
T806 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2979902829 Feb 28 04:23:46 PM PST 24 Feb 28 04:23:48 PM PST 24 146918323 ps
T807 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3213065086 Feb 28 04:25:51 PM PST 24 Feb 28 04:25:52 PM PST 24 130083803 ps
T808 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.233824334 Feb 28 04:23:40 PM PST 24 Feb 28 04:23:41 PM PST 24 37956486 ps
T809 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1920810785 Feb 28 04:23:42 PM PST 24 Feb 28 04:23:44 PM PST 24 45373400 ps
T810 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.995138468 Feb 28 04:23:56 PM PST 24 Feb 28 04:23:58 PM PST 24 126130252 ps
T811 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.831239877 Feb 28 04:23:46 PM PST 24 Feb 28 04:23:47 PM PST 24 30013826 ps
T812 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2709204292 Feb 28 04:23:21 PM PST 24 Feb 28 04:23:23 PM PST 24 14856972 ps
T813 /workspace/coverage/cover_reg_top/4.gpio_intr_test.741362663 Feb 28 04:23:48 PM PST 24 Feb 28 04:23:50 PM PST 24 41447632 ps
T814 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1536414117 Feb 28 04:23:30 PM PST 24 Feb 28 04:23:31 PM PST 24 47123745 ps
T815 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.362795343 Feb 28 04:23:30 PM PST 24 Feb 28 04:23:33 PM PST 24 91698552 ps
T816 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.33252426 Feb 28 04:23:52 PM PST 24 Feb 28 04:23:53 PM PST 24 61285820 ps
T817 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4158730274 Feb 28 04:23:40 PM PST 24 Feb 28 04:23:42 PM PST 24 50902243 ps
T818 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.4024393983 Feb 28 04:25:33 PM PST 24 Feb 28 04:25:34 PM PST 24 100893943 ps
T819 /workspace/coverage/cover_reg_top/28.gpio_intr_test.3079492512 Feb 28 04:24:02 PM PST 24 Feb 28 04:24:03 PM PST 24 11766380 ps
T820 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3156958455 Feb 28 04:23:44 PM PST 24 Feb 28 04:23:46 PM PST 24 13351422 ps
T821 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3886277840 Feb 28 04:23:49 PM PST 24 Feb 28 04:23:50 PM PST 24 48229464 ps
T822 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3187206726 Feb 28 04:23:57 PM PST 24 Feb 28 04:23:58 PM PST 24 156311968 ps
T823 /workspace/coverage/cover_reg_top/47.gpio_intr_test.3038199444 Feb 28 04:24:07 PM PST 24 Feb 28 04:24:08 PM PST 24 30662490 ps
T824 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1963446632 Feb 28 04:23:37 PM PST 24 Feb 28 04:23:37 PM PST 24 164554662 ps
T825 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3527238347 Feb 28 04:23:35 PM PST 24 Feb 28 04:23:36 PM PST 24 182347542 ps
T826 /workspace/coverage/cover_reg_top/19.gpio_intr_test.2955762756 Feb 28 04:24:04 PM PST 24 Feb 28 04:24:05 PM PST 24 12466352 ps
T827 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2614671487 Feb 28 04:25:50 PM PST 24 Feb 28 04:25:51 PM PST 24 32975384 ps
T828 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2498353841 Feb 28 04:24:04 PM PST 24 Feb 28 04:24:04 PM PST 24 54006811 ps
T829 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2529600941 Feb 28 04:24:00 PM PST 24 Feb 28 04:24:02 PM PST 24 128393627 ps
T830 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3878792485 Feb 28 04:23:23 PM PST 24 Feb 28 04:23:24 PM PST 24 122162789 ps
T831 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1663368703 Feb 28 04:23:46 PM PST 24 Feb 28 04:23:49 PM PST 24 341628101 ps
T832 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.874680763 Feb 28 04:23:54 PM PST 24 Feb 28 04:23:55 PM PST 24 56507367 ps
T833 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3600815508 Feb 28 04:25:52 PM PST 24 Feb 28 04:25:52 PM PST 24 16606666 ps
T834 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.842574234 Feb 28 04:23:27 PM PST 24 Feb 28 04:23:30 PM PST 24 374158926 ps
T835 /workspace/coverage/cover_reg_top/24.gpio_intr_test.3799876823 Feb 28 04:24:08 PM PST 24 Feb 28 04:24:09 PM PST 24 62547973 ps
T836 /workspace/coverage/cover_reg_top/15.gpio_intr_test.1394029505 Feb 28 04:27:26 PM PST 24 Feb 28 04:27:27 PM PST 24 55283606 ps
T837 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.4254364796 Feb 28 04:23:43 PM PST 24 Feb 28 04:23:45 PM PST 24 46293083 ps
T838 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2304407377 Feb 28 04:23:35 PM PST 24 Feb 28 04:23:38 PM PST 24 101537126 ps
T839 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1774044736 Feb 28 04:23:59 PM PST 24 Feb 28 04:24:01 PM PST 24 64662295 ps
T840 /workspace/coverage/cover_reg_top/46.gpio_intr_test.498017618 Feb 28 04:24:16 PM PST 24 Feb 28 04:24:17 PM PST 24 159070778 ps
T90 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1722125722 Feb 28 04:23:44 PM PST 24 Feb 28 04:23:45 PM PST 24 112638966 ps
T841 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3368973820 Feb 28 04:24:06 PM PST 24 Feb 28 04:24:08 PM PST 24 51462625 ps
T842 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.689080531 Feb 28 04:24:32 PM PST 24 Feb 28 04:24:34 PM PST 24 160726595 ps
T843 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3695475967 Feb 28 04:22:16 PM PST 24 Feb 28 04:22:19 PM PST 24 345389874 ps
T844 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.824861158 Feb 28 04:22:35 PM PST 24 Feb 28 04:22:36 PM PST 24 68967676 ps
T845 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3648635703 Feb 28 04:22:21 PM PST 24 Feb 28 04:22:23 PM PST 24 65349828 ps
T846 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3384501286 Feb 28 04:22:35 PM PST 24 Feb 28 04:22:36 PM PST 24 260721716 ps
T847 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3936560364 Feb 28 04:22:31 PM PST 24 Feb 28 04:22:33 PM PST 24 269815885 ps
T848 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1275177737 Feb 28 04:22:13 PM PST 24 Feb 28 04:22:14 PM PST 24 163987180 ps
T849 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2060027062 Feb 28 04:22:29 PM PST 24 Feb 28 04:22:31 PM PST 24 260047639 ps
T850 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.387966181 Feb 28 04:22:26 PM PST 24 Feb 28 04:22:28 PM PST 24 64644887 ps
T851 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.126678952 Feb 28 04:22:25 PM PST 24 Feb 28 04:22:27 PM PST 24 28960838 ps
T852 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.12237768 Feb 28 04:22:27 PM PST 24 Feb 28 04:22:28 PM PST 24 50713681 ps
T853 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2387219000 Feb 28 04:24:33 PM PST 24 Feb 28 04:24:35 PM PST 24 126415923 ps
T854 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1243463799 Feb 28 04:24:34 PM PST 24 Feb 28 04:24:35 PM PST 24 307585063 ps
T855 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1370729532 Feb 28 04:22:39 PM PST 24 Feb 28 04:22:41 PM PST 24 52826244 ps
T856 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.341367860 Feb 28 04:22:28 PM PST 24 Feb 28 04:22:29 PM PST 24 64558532 ps
T857 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3098450464 Feb 28 04:22:39 PM PST 24 Feb 28 04:22:40 PM PST 24 150420738 ps
T858 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.875076623 Feb 28 04:22:36 PM PST 24 Feb 28 04:22:37 PM PST 24 264317865 ps
T859 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.335085367 Feb 28 04:22:28 PM PST 24 Feb 28 04:22:30 PM PST 24 38459431 ps
T860 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.425505052 Feb 28 04:22:16 PM PST 24 Feb 28 04:22:19 PM PST 24 23301373 ps
T861 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3315584340 Feb 28 04:22:20 PM PST 24 Feb 28 04:22:21 PM PST 24 44376305 ps
T862 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.891136774 Feb 28 04:22:51 PM PST 24 Feb 28 04:22:53 PM PST 24 58429645 ps
T863 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3376805383 Feb 28 04:22:36 PM PST 24 Feb 28 04:22:37 PM PST 24 304375681 ps
T864 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1250803182 Feb 28 04:22:14 PM PST 24 Feb 28 04:22:17 PM PST 24 226805224 ps
T865 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1225481286 Feb 28 04:22:36 PM PST 24 Feb 28 04:22:37 PM PST 24 271515568 ps
T866 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.109557325 Feb 28 04:24:34 PM PST 24 Feb 28 04:24:35 PM PST 24 61751570 ps
T867 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.662686933 Feb 28 04:22:15 PM PST 24 Feb 28 04:22:17 PM PST 24 71689372 ps
T868 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3370608085 Feb 28 04:22:25 PM PST 24 Feb 28 04:22:26 PM PST 24 90104643 ps
T869 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3142443044 Feb 28 04:22:31 PM PST 24 Feb 28 04:22:32 PM PST 24 125482942 ps
T870 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3713606400 Feb 28 04:22:20 PM PST 24 Feb 28 04:22:22 PM PST 24 149821948 ps
T871 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2439096645 Feb 28 04:22:22 PM PST 24 Feb 28 04:22:23 PM PST 24 45594070 ps
T872 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3439825605 Feb 28 04:22:38 PM PST 24 Feb 28 04:22:39 PM PST 24 56713169 ps
T873 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1519740488 Feb 28 04:22:37 PM PST 24 Feb 28 04:22:39 PM PST 24 43824340 ps
T874 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1863299698 Feb 28 04:24:28 PM PST 24 Feb 28 04:24:29 PM PST 24 73318851 ps
T875 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.464411655 Feb 28 04:22:27 PM PST 24 Feb 28 04:22:29 PM PST 24 611255791 ps
T876 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.730080665 Feb 28 04:22:34 PM PST 24 Feb 28 04:22:35 PM PST 24 133354319 ps
T877 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.764887563 Feb 28 04:22:18 PM PST 24 Feb 28 04:22:24 PM PST 24 246768775 ps
T878 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2732281549 Feb 28 04:22:33 PM PST 24 Feb 28 04:22:35 PM PST 24 120677310 ps
T879 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3502328255 Feb 28 04:22:39 PM PST 24 Feb 28 04:22:41 PM PST 24 186437519 ps
T880 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.474824762 Feb 28 04:22:30 PM PST 24 Feb 28 04:22:33 PM PST 24 228424869 ps
T881 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1470939893 Feb 28 04:22:33 PM PST 24 Feb 28 04:22:34 PM PST 24 145953023 ps
T882 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.425179892 Feb 28 04:22:32 PM PST 24 Feb 28 04:22:34 PM PST 24 44302526 ps
T883 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.661110766 Feb 28 04:22:38 PM PST 24 Feb 28 04:22:39 PM PST 24 121624315 ps
T884 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1652113714 Feb 28 04:22:35 PM PST 24 Feb 28 04:22:36 PM PST 24 302471476 ps
T885 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3482829743 Feb 28 04:22:32 PM PST 24 Feb 28 04:22:33 PM PST 24 67801644 ps
T886 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.461354178 Feb 28 04:22:29 PM PST 24 Feb 28 04:22:31 PM PST 24 265346664 ps
T887 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.220594287 Feb 28 04:22:37 PM PST 24 Feb 28 04:22:38 PM PST 24 87862898 ps
T888 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2412648543 Feb 28 04:24:35 PM PST 24 Feb 28 04:24:36 PM PST 24 237358612 ps
T889 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2098370908 Feb 28 04:22:27 PM PST 24 Feb 28 04:22:28 PM PST 24 563891558 ps
T890 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4184840922 Feb 28 04:22:15 PM PST 24 Feb 28 04:22:17 PM PST 24 85199865 ps
T891 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.743038087 Feb 28 04:23:29 PM PST 24 Feb 28 04:23:31 PM PST 24 242276904 ps
T892 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1037503467 Feb 28 04:22:24 PM PST 24 Feb 28 04:22:25 PM PST 24 58134231 ps
T893 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3861069495 Feb 28 04:22:37 PM PST 24 Feb 28 04:22:38 PM PST 24 59761886 ps
T894 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2274493399 Feb 28 04:22:35 PM PST 24 Feb 28 04:22:36 PM PST 24 49517149 ps
T895 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3548652457 Feb 28 04:22:15 PM PST 24 Feb 28 04:22:17 PM PST 24 61056408 ps
T896 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.884727024 Feb 28 04:22:33 PM PST 24 Feb 28 04:22:35 PM PST 24 80538736 ps
T897 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3924574577 Feb 28 04:22:28 PM PST 24 Feb 28 04:22:29 PM PST 24 59110205 ps
T898 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3507622790 Feb 28 04:22:01 PM PST 24 Feb 28 04:22:03 PM PST 24 277435593 ps
T899 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1652187408 Feb 28 04:22:27 PM PST 24 Feb 28 04:22:29 PM PST 24 75072303 ps
T900 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3278533140 Feb 28 04:22:18 PM PST 24 Feb 28 04:22:20 PM PST 24 43989845 ps
T901 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2887997538 Feb 28 04:22:14 PM PST 24 Feb 28 04:22:16 PM PST 24 49660729 ps
T902 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1031079019 Feb 28 04:22:47 PM PST 24 Feb 28 04:22:53 PM PST 24 1125676050 ps
T903 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1513900019 Feb 28 04:22:25 PM PST 24 Feb 28 04:22:26 PM PST 24 70674083 ps
T904 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2153258430 Feb 28 04:22:38 PM PST 24 Feb 28 04:22:40 PM PST 24 35261865 ps
T905 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.205615148 Feb 28 04:22:37 PM PST 24 Feb 28 04:22:38 PM PST 24 58566011 ps
T906 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.101274714 Feb 28 04:22:36 PM PST 24 Feb 28 04:22:37 PM PST 24 70658381 ps
T907 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.237464114 Feb 28 04:24:28 PM PST 24 Feb 28 04:24:30 PM PST 24 118211608 ps
T908 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3556232815 Feb 28 04:22:24 PM PST 24 Feb 28 04:22:25 PM PST 24 66669565 ps
T909 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1815969108 Feb 28 04:22:35 PM PST 24 Feb 28 04:22:37 PM PST 24 85057175 ps
T910 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1257138932 Feb 28 04:22:27 PM PST 24 Feb 28 04:22:28 PM PST 24 26571334 ps
T911 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2476091793 Feb 28 04:22:33 PM PST 24 Feb 28 04:22:34 PM PST 24 67736533 ps
T912 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1189930973 Feb 28 04:22:26 PM PST 24 Feb 28 04:22:28 PM PST 24 200512377 ps
T913 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2708108089 Feb 28 04:22:22 PM PST 24 Feb 28 04:22:23 PM PST 24 177310779 ps
T914 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2740383494 Feb 28 04:24:28 PM PST 24 Feb 28 04:24:30 PM PST 24 221166271 ps
T915 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2288754366 Feb 28 04:22:43 PM PST 24 Feb 28 04:22:45 PM PST 24 126237119 ps
T916 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.166837541 Feb 28 04:22:13 PM PST 24 Feb 28 04:22:15 PM PST 24 547233311 ps
T917 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1861214054 Feb 28 04:22:23 PM PST 24 Feb 28 04:22:23 PM PST 24 22965163 ps
T918 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2750532112 Feb 28 04:24:31 PM PST 24 Feb 28 04:24:33 PM PST 24 151960745 ps
T919 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.149184151 Feb 28 04:22:22 PM PST 24 Feb 28 04:22:23 PM PST 24 27122064 ps
T920 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3535861711 Feb 28 04:22:25 PM PST 24 Feb 28 04:22:27 PM PST 24 70999611 ps
T921 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2291887861 Feb 28 04:22:22 PM PST 24 Feb 28 04:22:23 PM PST 24 41260015 ps
T922 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.144882651 Feb 28 04:22:26 PM PST 24 Feb 28 04:22:28 PM PST 24 287294466 ps
T923 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2939391126 Feb 28 04:22:17 PM PST 24 Feb 28 04:22:20 PM PST 24 97483079 ps
T924 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.270074128 Feb 28 04:22:39 PM PST 24 Feb 28 04:22:40 PM PST 24 274966311 ps
T925 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3681999615 Feb 28 04:22:21 PM PST 24 Feb 28 04:22:22 PM PST 24 147179980 ps
T926 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2159897102 Feb 28 04:22:49 PM PST 24 Feb 28 04:22:51 PM PST 24 85196094 ps
T927 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.952310896 Feb 28 04:22:26 PM PST 24 Feb 28 04:22:27 PM PST 24 54919228 ps
T928 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3021079495 Feb 28 04:22:24 PM PST 24 Feb 28 04:22:25 PM PST 24 115970125 ps
T929 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2603151619 Feb 28 04:22:41 PM PST 24 Feb 28 04:22:43 PM PST 24 35273660 ps
T930 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.84392068 Feb 28 04:22:34 PM PST 24 Feb 28 04:22:35 PM PST 24 87790353 ps
T931 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2896311473 Feb 28 04:22:17 PM PST 24 Feb 28 04:22:20 PM PST 24 183057626 ps
T932 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.4039477201 Feb 28 04:22:26 PM PST 24 Feb 28 04:22:27 PM PST 24 102451567 ps
T933 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3049407620 Feb 28 04:22:22 PM PST 24 Feb 28 04:22:23 PM PST 24 50665749 ps
T934 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4061380186 Feb 28 04:22:28 PM PST 24 Feb 28 04:22:29 PM PST 24 100857834 ps
T935 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.292205452 Feb 28 04:22:19 PM PST 24 Feb 28 04:22:21 PM PST 24 75374976 ps
T936 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3356927117 Feb 28 04:22:10 PM PST 24 Feb 28 04:22:11 PM PST 24 77665293 ps
T937 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2825656983 Feb 28 04:22:35 PM PST 24 Feb 28 04:22:36 PM PST 24 85602694 ps
T938 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.384822261 Feb 28 04:22:30 PM PST 24 Feb 28 04:22:33 PM PST 24 286143572 ps
T939 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1023444502 Feb 28 04:22:37 PM PST 24 Feb 28 04:22:38 PM PST 24 105215171 ps
T940 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.330285429 Feb 28 04:22:25 PM PST 24 Feb 28 04:22:27 PM PST 24 64643611 ps

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.1818079546
Short name T25
Test name
Test status
Simulation time 207789614877 ps
CPU time 2279.79 seconds
Started Feb 28 05:21:34 PM PST 24
Finished Feb 28 05:59:34 PM PST 24
Peak memory 198368 kb
Host smart-c5070309-23cb-4555-9d32-20429b653f86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1818079546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.1818079546
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1115390312
Short name T13
Test name
Test status
Simulation time 195925563 ps
CPU time 2.1 seconds
Started Feb 28 05:20:27 PM PST 24
Finished Feb 28 05:20:29 PM PST 24
Peak memory 198088 kb
Host smart-bbfc2cde-e116-460a-9bc0-c65adbb22b9d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115390312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1115390312
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2201210981
Short name T34
Test name
Test status
Simulation time 377238789 ps
CPU time 0.99 seconds
Started Feb 28 05:19:43 PM PST 24
Finished Feb 28 05:19:44 PM PST 24
Peak memory 215012 kb
Host smart-54fa3020-9374-4120-922b-73f127ab4216
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201210981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2201210981
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3473202604
Short name T76
Test name
Test status
Simulation time 55990991 ps
CPU time 0.62 seconds
Started Feb 28 04:23:35 PM PST 24
Finished Feb 28 04:23:36 PM PST 24
Peak memory 195000 kb
Host smart-85643d74-64a6-4980-b8b9-de96d9576870
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473202604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3473202604
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.1033856822
Short name T3
Test name
Test status
Simulation time 39727731226 ps
CPU time 456.99 seconds
Started Feb 28 05:21:36 PM PST 24
Finished Feb 28 05:29:13 PM PST 24
Peak memory 198376 kb
Host smart-542ad028-6f7a-464d-b351-dcda14c94154
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1033856822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.1033856822
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.216042675
Short name T41
Test name
Test status
Simulation time 493827824 ps
CPU time 1.79 seconds
Started Feb 28 04:23:57 PM PST 24
Finished Feb 28 04:23:59 PM PST 24
Peak memory 197784 kb
Host smart-6f6a18d9-faee-4dc1-8405-af4ba154339e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216042675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.216042675
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2667438558
Short name T180
Test name
Test status
Simulation time 24066164 ps
CPU time 0.59 seconds
Started Feb 28 05:19:43 PM PST 24
Finished Feb 28 05:19:43 PM PST 24
Peak memory 194188 kb
Host smart-f7653754-058d-4156-afce-9cecf2b92410
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667438558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2667438558
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.999888736
Short name T93
Test name
Test status
Simulation time 156030228 ps
CPU time 0.92 seconds
Started Feb 28 04:27:13 PM PST 24
Finished Feb 28 04:27:16 PM PST 24
Peak memory 194600 kb
Host smart-c0ab04d5-ad01-4f36-88da-a287783afed9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999888736 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.999888736
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.gpio_smoke.54406848
Short name T119
Test name
Test status
Simulation time 46275042 ps
CPU time 0.93 seconds
Started Feb 28 05:20:38 PM PST 24
Finished Feb 28 05:20:39 PM PST 24
Peak memory 195876 kb
Host smart-bee1cad5-9393-434b-b578-b24320fc07b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54406848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.54406848
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3671878469
Short name T784
Test name
Test status
Simulation time 762725445 ps
CPU time 1.51 seconds
Started Feb 28 04:23:45 PM PST 24
Finished Feb 28 04:23:47 PM PST 24
Peak memory 198440 kb
Host smart-6c04cbc1-8488-4597-9c15-e1f19d5f2b1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671878469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3671878469
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1722125722
Short name T90
Test name
Test status
Simulation time 112638966 ps
CPU time 0.77 seconds
Started Feb 28 04:23:44 PM PST 24
Finished Feb 28 04:23:45 PM PST 24
Peak memory 196356 kb
Host smart-ba23ba0b-23ac-48b2-ad7e-e8d4e36cc432
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722125722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1722125722
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3426528152
Short name T71
Test name
Test status
Simulation time 85502271 ps
CPU time 1.35 seconds
Started Feb 28 04:23:37 PM PST 24
Finished Feb 28 04:23:39 PM PST 24
Peak memory 196952 kb
Host smart-b68f4955-8e76-470c-82d9-2d3b85336a0c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426528152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3426528152
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1671669314
Short name T84
Test name
Test status
Simulation time 113863478 ps
CPU time 0.58 seconds
Started Feb 28 04:23:43 PM PST 24
Finished Feb 28 04:23:45 PM PST 24
Peak memory 194804 kb
Host smart-f96b4f0a-0f4d-4901-a089-33764f073c20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671669314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1671669314
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3739225674
Short name T719
Test name
Test status
Simulation time 102262361 ps
CPU time 0.93 seconds
Started Feb 28 04:23:53 PM PST 24
Finished Feb 28 04:23:54 PM PST 24
Peak memory 198396 kb
Host smart-5cba7bd8-a1b4-4ff7-932b-ac0c7ddbaff2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739225674 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3739225674
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3645544274
Short name T77
Test name
Test status
Simulation time 14076800 ps
CPU time 0.59 seconds
Started Feb 28 04:23:31 PM PST 24
Finished Feb 28 04:23:32 PM PST 24
Peak memory 194740 kb
Host smart-ae224e66-985a-4566-a95c-f6390b8f8b98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645544274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3645544274
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2020018147
Short name T743
Test name
Test status
Simulation time 35660480 ps
CPU time 0.55 seconds
Started Feb 28 04:23:36 PM PST 24
Finished Feb 28 04:23:37 PM PST 24
Peak memory 194052 kb
Host smart-bd405b8d-a386-4e78-8ca0-db7b3f74f133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020018147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2020018147
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3878792485
Short name T830
Test name
Test status
Simulation time 122162789 ps
CPU time 1 seconds
Started Feb 28 04:23:23 PM PST 24
Finished Feb 28 04:23:24 PM PST 24
Peak memory 196872 kb
Host smart-dffa1b0f-9c72-470c-ad79-0ea39b3cc847
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878792485 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3878792485
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2304407377
Short name T838
Test name
Test status
Simulation time 101537126 ps
CPU time 1.76 seconds
Started Feb 28 04:23:35 PM PST 24
Finished Feb 28 04:23:38 PM PST 24
Peak memory 198460 kb
Host smart-c0545fd9-0b36-430b-992b-350325a23d8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304407377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2304407377
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.571748681
Short name T106
Test name
Test status
Simulation time 76618597 ps
CPU time 1.24 seconds
Started Feb 28 04:23:32 PM PST 24
Finished Feb 28 04:23:34 PM PST 24
Peak memory 198132 kb
Host smart-c22c595e-a877-436e-a78b-5be3b4fa9315
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571748681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.571748681
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2402375702
Short name T86
Test name
Test status
Simulation time 60220196 ps
CPU time 0.77 seconds
Started Feb 28 04:23:34 PM PST 24
Finished Feb 28 04:23:35 PM PST 24
Peak memory 196356 kb
Host smart-a95ab81f-cb1e-479a-a104-897ff3a0a206
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402375702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2402375702
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.362795343
Short name T815
Test name
Test status
Simulation time 91698552 ps
CPU time 2.16 seconds
Started Feb 28 04:23:30 PM PST 24
Finished Feb 28 04:23:33 PM PST 24
Peak memory 197552 kb
Host smart-b7e74d58-1e0f-49b9-96c1-4c54f1142d0e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362795343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.362795343
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2317635196
Short name T83
Test name
Test status
Simulation time 48301258 ps
CPU time 0.59 seconds
Started Feb 28 04:23:37 PM PST 24
Finished Feb 28 04:23:39 PM PST 24
Peak memory 195068 kb
Host smart-06661b55-c886-4bd1-adb7-40cea16791b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317635196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2317635196
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3187206726
Short name T822
Test name
Test status
Simulation time 156311968 ps
CPU time 0.84 seconds
Started Feb 28 04:23:57 PM PST 24
Finished Feb 28 04:23:58 PM PST 24
Peak memory 197656 kb
Host smart-8c1f59b1-5c7b-47ed-bb32-f33ebc053980
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187206726 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3187206726
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2870876868
Short name T69
Test name
Test status
Simulation time 14353002 ps
CPU time 0.59 seconds
Started Feb 28 04:23:40 PM PST 24
Finished Feb 28 04:23:41 PM PST 24
Peak memory 194160 kb
Host smart-06a39acd-bff9-4053-a427-818564936ff0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870876868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2870876868
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2879512069
Short name T789
Test name
Test status
Simulation time 39526469 ps
CPU time 0.56 seconds
Started Feb 28 04:24:00 PM PST 24
Finished Feb 28 04:24:00 PM PST 24
Peak memory 194132 kb
Host smart-11110870-7756-40e3-a828-39ffd13074f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879512069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2879512069
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.4263615115
Short name T791
Test name
Test status
Simulation time 145629059 ps
CPU time 0.87 seconds
Started Feb 28 04:23:37 PM PST 24
Finished Feb 28 04:23:38 PM PST 24
Peak memory 197724 kb
Host smart-2ec13d7d-337d-4e81-a6a8-e36bf7e8b327
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263615115 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.4263615115
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1374234572
Short name T750
Test name
Test status
Simulation time 39463085 ps
CPU time 2.16 seconds
Started Feb 28 04:23:40 PM PST 24
Finished Feb 28 04:23:43 PM PST 24
Peak memory 198436 kb
Host smart-750f456c-a020-4f46-a242-370b01b123da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374234572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1374234572
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1199510145
Short name T804
Test name
Test status
Simulation time 85689242 ps
CPU time 0.85 seconds
Started Feb 28 04:23:39 PM PST 24
Finished Feb 28 04:23:40 PM PST 24
Peak memory 197320 kb
Host smart-2642e3db-fec7-4bea-a28b-e643e2a6bf03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199510145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1199510145
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3675382638
Short name T797
Test name
Test status
Simulation time 39523837 ps
CPU time 1.08 seconds
Started Feb 28 04:23:44 PM PST 24
Finished Feb 28 04:23:46 PM PST 24
Peak memory 198432 kb
Host smart-3d357b36-734f-4575-968f-f2cfe9809a6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675382638 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3675382638
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1572598325
Short name T89
Test name
Test status
Simulation time 14905873 ps
CPU time 0.69 seconds
Started Feb 28 04:27:13 PM PST 24
Finished Feb 28 04:27:16 PM PST 24
Peak memory 194076 kb
Host smart-438ea4f6-fe65-4afc-98b1-92812558bf46
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572598325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1572598325
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2289300669
Short name T737
Test name
Test status
Simulation time 46623275 ps
CPU time 0.55 seconds
Started Feb 28 04:23:46 PM PST 24
Finished Feb 28 04:23:46 PM PST 24
Peak memory 194040 kb
Host smart-164e2faa-ed6b-402f-b968-a95305f83e57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289300669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2289300669
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3788113161
Short name T738
Test name
Test status
Simulation time 98814619 ps
CPU time 0.97 seconds
Started Feb 28 04:23:52 PM PST 24
Finished Feb 28 04:23:54 PM PST 24
Peak memory 198256 kb
Host smart-479194af-f582-4007-bad9-a3ed0e722f74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788113161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3788113161
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.490194978
Short name T788
Test name
Test status
Simulation time 70010694 ps
CPU time 1.08 seconds
Started Feb 28 04:23:47 PM PST 24
Finished Feb 28 04:23:49 PM PST 24
Peak memory 198480 kb
Host smart-4abdbafa-9e6f-409a-a235-921b4b800715
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490194978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.490194978
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.33252426
Short name T816
Test name
Test status
Simulation time 61285820 ps
CPU time 0.97 seconds
Started Feb 28 04:23:52 PM PST 24
Finished Feb 28 04:23:53 PM PST 24
Peak memory 198356 kb
Host smart-3cd073fc-a9dc-4b71-914d-16f507a3989a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33252426 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.33252426
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3554624372
Short name T787
Test name
Test status
Simulation time 94570832 ps
CPU time 0.6 seconds
Started Feb 28 04:23:42 PM PST 24
Finished Feb 28 04:23:44 PM PST 24
Peak memory 194900 kb
Host smart-b4bb7eac-75db-432c-b8d9-7459271ac91b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554624372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3554624372
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.946297121
Short name T764
Test name
Test status
Simulation time 27629399 ps
CPU time 0.57 seconds
Started Feb 28 04:23:40 PM PST 24
Finished Feb 28 04:23:42 PM PST 24
Peak memory 194060 kb
Host smart-1e6895a6-c0be-49fe-8407-ef2f2cf461b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946297121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.946297121
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3250114859
Short name T767
Test name
Test status
Simulation time 18597111 ps
CPU time 0.66 seconds
Started Feb 28 04:27:28 PM PST 24
Finished Feb 28 04:27:29 PM PST 24
Peak memory 195076 kb
Host smart-7410f76b-b4ea-4899-860c-550cae9fe8ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250114859 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3250114859
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.319745390
Short name T744
Test name
Test status
Simulation time 164859092 ps
CPU time 2.18 seconds
Started Feb 28 04:23:42 PM PST 24
Finished Feb 28 04:23:46 PM PST 24
Peak memory 198492 kb
Host smart-b2cc4462-3645-44fc-ac23-d5539b4a703f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319745390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.319745390
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2578833476
Short name T724
Test name
Test status
Simulation time 156733477 ps
CPU time 1.02 seconds
Started Feb 28 04:23:43 PM PST 24
Finished Feb 28 04:23:45 PM PST 24
Peak memory 198332 kb
Host smart-be5b02f4-6015-47e6-a46d-4e9e767bdedc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578833476 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2578833476
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3594396316
Short name T78
Test name
Test status
Simulation time 37388870 ps
CPU time 0.59 seconds
Started Feb 28 04:23:52 PM PST 24
Finished Feb 28 04:23:52 PM PST 24
Peak memory 194104 kb
Host smart-963bdac5-e261-4a20-96ee-978017a502bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594396316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3594396316
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3410908912
Short name T746
Test name
Test status
Simulation time 32743385 ps
CPU time 0.56 seconds
Started Feb 28 04:23:57 PM PST 24
Finished Feb 28 04:23:58 PM PST 24
Peak memory 194828 kb
Host smart-ece1f5a6-1741-4088-adb9-afc9c28260e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410908912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3410908912
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3518104742
Short name T773
Test name
Test status
Simulation time 72139051 ps
CPU time 0.66 seconds
Started Feb 28 04:23:39 PM PST 24
Finished Feb 28 04:23:40 PM PST 24
Peak memory 195712 kb
Host smart-2e5495bb-2831-41e1-9072-5d065e92eec5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518104742 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3518104742
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2903635953
Short name T782
Test name
Test status
Simulation time 285391991 ps
CPU time 1.39 seconds
Started Feb 28 04:23:56 PM PST 24
Finished Feb 28 04:23:58 PM PST 24
Peak memory 198604 kb
Host smart-4cd0104b-0f6d-4f0e-a804-d1b195b7bda2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903635953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2903635953
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2979902829
Short name T806
Test name
Test status
Simulation time 146918323 ps
CPU time 0.86 seconds
Started Feb 28 04:23:46 PM PST 24
Finished Feb 28 04:23:48 PM PST 24
Peak memory 198232 kb
Host smart-7a182ba4-f267-48b4-ad86-184375d581e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979902829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2979902829
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1118891544
Short name T728
Test name
Test status
Simulation time 16070458 ps
CPU time 0.65 seconds
Started Feb 28 04:23:41 PM PST 24
Finished Feb 28 04:23:43 PM PST 24
Peak memory 197084 kb
Host smart-7721a888-8b9d-4a5b-a79a-84759f12c81f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118891544 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1118891544
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2480231817
Short name T87
Test name
Test status
Simulation time 25139525 ps
CPU time 0.55 seconds
Started Feb 28 04:23:56 PM PST 24
Finished Feb 28 04:23:57 PM PST 24
Peak memory 193840 kb
Host smart-86500c77-e251-4407-8147-4e1af4d95130
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480231817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2480231817
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1851183529
Short name T760
Test name
Test status
Simulation time 12225440 ps
CPU time 0.58 seconds
Started Feb 28 04:23:59 PM PST 24
Finished Feb 28 04:24:00 PM PST 24
Peak memory 194732 kb
Host smart-40ab27af-aa18-4674-aa49-0f41fdeb3e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851183529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1851183529
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2989576461
Short name T73
Test name
Test status
Simulation time 16124395 ps
CPU time 0.62 seconds
Started Feb 28 04:24:12 PM PST 24
Finished Feb 28 04:24:13 PM PST 24
Peak memory 195644 kb
Host smart-9e0a9d4f-f6a6-4313-be46-6a55d0d7d50b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989576461 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2989576461
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4158730274
Short name T817
Test name
Test status
Simulation time 50902243 ps
CPU time 1.23 seconds
Started Feb 28 04:23:40 PM PST 24
Finished Feb 28 04:23:42 PM PST 24
Peak memory 198444 kb
Host smart-42f5d8c5-fd9e-4267-a68b-1dc658b7a30e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158730274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.4158730274
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3442726774
Short name T40
Test name
Test status
Simulation time 316397256 ps
CPU time 1.13 seconds
Started Feb 28 04:23:37 PM PST 24
Finished Feb 28 04:23:38 PM PST 24
Peak memory 198440 kb
Host smart-07c545c3-270a-46d6-b457-692eec010253
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442726774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3442726774
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.20266551
Short name T774
Test name
Test status
Simulation time 99705666 ps
CPU time 0.66 seconds
Started Feb 28 04:24:06 PM PST 24
Finished Feb 28 04:24:07 PM PST 24
Peak memory 198228 kb
Host smart-c026fd42-d6cc-4247-a2de-8e57a7777345
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20266551 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.20266551
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3600815508
Short name T833
Test name
Test status
Simulation time 16606666 ps
CPU time 0.61 seconds
Started Feb 28 04:25:52 PM PST 24
Finished Feb 28 04:25:52 PM PST 24
Peak memory 194784 kb
Host smart-c1d73787-080a-46f5-9763-e7ace5e88afb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600815508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3600815508
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.4192154134
Short name T732
Test name
Test status
Simulation time 30938886 ps
CPU time 0.58 seconds
Started Feb 28 04:27:26 PM PST 24
Finished Feb 28 04:27:27 PM PST 24
Peak memory 194548 kb
Host smart-af71d735-4a14-42bf-bcdd-7a700052f563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192154134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4192154134
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3928638130
Short name T779
Test name
Test status
Simulation time 36712430 ps
CPU time 0.91 seconds
Started Feb 28 04:27:13 PM PST 24
Finished Feb 28 04:27:16 PM PST 24
Peak memory 195196 kb
Host smart-082b4caf-98f6-4efc-a689-bca4c7946240
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928638130 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3928638130
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2809958595
Short name T759
Test name
Test status
Simulation time 448903049 ps
CPU time 2.14 seconds
Started Feb 28 04:25:52 PM PST 24
Finished Feb 28 04:25:55 PM PST 24
Peak memory 198232 kb
Host smart-88df2d09-b29b-4b23-8c3f-354c9dbd48ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809958595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2809958595
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1081429665
Short name T29
Test name
Test status
Simulation time 47815362 ps
CPU time 0.91 seconds
Started Feb 28 04:23:42 PM PST 24
Finished Feb 28 04:23:45 PM PST 24
Peak memory 197416 kb
Host smart-66fe5171-5ff4-432e-817f-b2c8269ddbba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081429665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1081429665
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3624801230
Short name T771
Test name
Test status
Simulation time 59679490 ps
CPU time 0.69 seconds
Started Feb 28 04:23:42 PM PST 24
Finished Feb 28 04:23:44 PM PST 24
Peak memory 198192 kb
Host smart-a3f280c2-b874-440c-a758-5201b484d6a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624801230 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3624801230
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3532310469
Short name T800
Test name
Test status
Simulation time 36920126 ps
CPU time 0.58 seconds
Started Feb 28 04:25:50 PM PST 24
Finished Feb 28 04:25:50 PM PST 24
Peak memory 195420 kb
Host smart-cf4befbd-6681-42ca-87fc-f85d2a3d3803
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532310469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3532310469
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1394029505
Short name T836
Test name
Test status
Simulation time 55283606 ps
CPU time 0.58 seconds
Started Feb 28 04:27:26 PM PST 24
Finished Feb 28 04:27:27 PM PST 24
Peak memory 193956 kb
Host smart-3530b2e4-5b8f-43d1-9c37-d53edc446e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394029505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1394029505
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.233824334
Short name T808
Test name
Test status
Simulation time 37956486 ps
CPU time 0.61 seconds
Started Feb 28 04:23:40 PM PST 24
Finished Feb 28 04:23:41 PM PST 24
Peak memory 195840 kb
Host smart-7d83f0ab-5c44-48c5-85a8-1079f7b4acf3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233824334 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.233824334
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.4024393983
Short name T818
Test name
Test status
Simulation time 100893943 ps
CPU time 1.06 seconds
Started Feb 28 04:25:33 PM PST 24
Finished Feb 28 04:25:34 PM PST 24
Peak memory 196336 kb
Host smart-703bb73a-92b0-41a6-9aff-3ef1efc303d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024393983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.4024393983
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3067616289
Short name T796
Test name
Test status
Simulation time 79927250 ps
CPU time 1.1 seconds
Started Feb 28 04:27:26 PM PST 24
Finished Feb 28 04:27:27 PM PST 24
Peak memory 198228 kb
Host smart-419d1e51-ca43-44d3-95c7-af456217efb6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067616289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3067616289
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1503354060
Short name T794
Test name
Test status
Simulation time 91080055 ps
CPU time 1.17 seconds
Started Feb 28 04:24:08 PM PST 24
Finished Feb 28 04:24:09 PM PST 24
Peak memory 198556 kb
Host smart-7f0a48f0-4850-4611-bfcb-2a895d942d31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503354060 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1503354060
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.874680763
Short name T832
Test name
Test status
Simulation time 56507367 ps
CPU time 0.6 seconds
Started Feb 28 04:23:54 PM PST 24
Finished Feb 28 04:23:55 PM PST 24
Peak memory 195320 kb
Host smart-63ebd90f-9c6b-4a7f-b8df-1113e6226e8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874680763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.874680763
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3213065086
Short name T807
Test name
Test status
Simulation time 130083803 ps
CPU time 0.55 seconds
Started Feb 28 04:25:51 PM PST 24
Finished Feb 28 04:25:52 PM PST 24
Peak memory 194540 kb
Host smart-2a7bc994-9529-4fdd-84b5-34f04a0f6d74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213065086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3213065086
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.738545445
Short name T72
Test name
Test status
Simulation time 126370622 ps
CPU time 0.79 seconds
Started Feb 28 04:23:59 PM PST 24
Finished Feb 28 04:24:00 PM PST 24
Peak memory 197508 kb
Host smart-3388dcff-ae80-4854-949c-c8959a0f52e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738545445 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.738545445
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1658228324
Short name T798
Test name
Test status
Simulation time 55727204 ps
CPU time 1.27 seconds
Started Feb 28 04:25:56 PM PST 24
Finished Feb 28 04:25:57 PM PST 24
Peak memory 198248 kb
Host smart-6ed4a110-a37a-4379-8633-73e54858dfa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658228324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1658228324
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1980627842
Short name T39
Test name
Test status
Simulation time 118642900 ps
CPU time 1.33 seconds
Started Feb 28 04:25:56 PM PST 24
Finished Feb 28 04:25:58 PM PST 24
Peak memory 198268 kb
Host smart-a94eadc5-9b26-48ae-a357-78030068b118
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980627842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1980627842
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.696945566
Short name T799
Test name
Test status
Simulation time 271886419 ps
CPU time 0.97 seconds
Started Feb 28 04:23:40 PM PST 24
Finished Feb 28 04:23:42 PM PST 24
Peak memory 198352 kb
Host smart-cfa5774f-237c-42a7-9b82-338d043b56be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696945566 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.696945566
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1575433789
Short name T70
Test name
Test status
Simulation time 15365195 ps
CPU time 0.62 seconds
Started Feb 28 04:24:09 PM PST 24
Finished Feb 28 04:24:10 PM PST 24
Peak memory 195184 kb
Host smart-96d63395-a60f-4c84-ad09-2c7692157cc7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575433789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.1575433789
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1156248441
Short name T805
Test name
Test status
Simulation time 40838364 ps
CPU time 0.58 seconds
Started Feb 28 04:23:42 PM PST 24
Finished Feb 28 04:23:45 PM PST 24
Peak memory 194180 kb
Host smart-f1013e4f-fcdb-432d-a1f5-7d856cb89ee7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156248441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1156248441
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2913046258
Short name T94
Test name
Test status
Simulation time 16114138 ps
CPU time 0.65 seconds
Started Feb 28 04:23:34 PM PST 24
Finished Feb 28 04:23:35 PM PST 24
Peak memory 195128 kb
Host smart-68a9872b-187b-427a-bec4-c9eaf68ff40c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913046258 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2913046258
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3193756519
Short name T756
Test name
Test status
Simulation time 25596052 ps
CPU time 1.24 seconds
Started Feb 28 04:24:09 PM PST 24
Finished Feb 28 04:24:11 PM PST 24
Peak memory 198528 kb
Host smart-f16ee810-8e73-4d73-b7f0-9b924242f2e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193756519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3193756519
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3329833150
Short name T716
Test name
Test status
Simulation time 450238590 ps
CPU time 1.1 seconds
Started Feb 28 04:23:54 PM PST 24
Finished Feb 28 04:23:55 PM PST 24
Peak memory 198456 kb
Host smart-8c4d514d-8dc1-4178-8c74-8cde47ce6612
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329833150 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3329833150
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.102748824
Short name T753
Test name
Test status
Simulation time 26125557 ps
CPU time 0.58 seconds
Started Feb 28 04:24:03 PM PST 24
Finished Feb 28 04:24:04 PM PST 24
Peak memory 195796 kb
Host smart-239f595b-60d3-4949-979a-552bbb4af320
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102748824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.102748824
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2614671487
Short name T827
Test name
Test status
Simulation time 32975384 ps
CPU time 0.6 seconds
Started Feb 28 04:25:50 PM PST 24
Finished Feb 28 04:25:51 PM PST 24
Peak memory 194652 kb
Host smart-35de45a3-3907-43c0-b36b-24fc1ff85d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614671487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2614671487
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2317261094
Short name T75
Test name
Test status
Simulation time 60532566 ps
CPU time 0.71 seconds
Started Feb 28 04:23:56 PM PST 24
Finished Feb 28 04:23:57 PM PST 24
Peak memory 196032 kb
Host smart-6925bed2-6e8f-4d0d-973a-98fb33e76025
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317261094 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2317261094
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.696521387
Short name T765
Test name
Test status
Simulation time 149726684 ps
CPU time 2.58 seconds
Started Feb 28 04:27:28 PM PST 24
Finished Feb 28 04:27:31 PM PST 24
Peak memory 198208 kb
Host smart-2542820a-5617-4951-a604-12339f25d5e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696521387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.696521387
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2340565917
Short name T795
Test name
Test status
Simulation time 436318969 ps
CPU time 1.43 seconds
Started Feb 28 04:23:57 PM PST 24
Finished Feb 28 04:23:59 PM PST 24
Peak memory 198456 kb
Host smart-240bd281-9a61-4a27-91f5-82a5c3ac94b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340565917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2340565917
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3886277840
Short name T821
Test name
Test status
Simulation time 48229464 ps
CPU time 0.94 seconds
Started Feb 28 04:23:49 PM PST 24
Finished Feb 28 04:23:50 PM PST 24
Peak memory 198264 kb
Host smart-5a017fe2-f7e0-4a10-9c50-87cbafa7e302
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886277840 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3886277840
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1808604248
Short name T735
Test name
Test status
Simulation time 47759887 ps
CPU time 0.57 seconds
Started Feb 28 04:23:54 PM PST 24
Finished Feb 28 04:23:54 PM PST 24
Peak memory 194312 kb
Host smart-feb15d17-7800-4b59-bda2-c62fce61387b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808604248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1808604248
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2955762756
Short name T826
Test name
Test status
Simulation time 12466352 ps
CPU time 0.57 seconds
Started Feb 28 04:24:04 PM PST 24
Finished Feb 28 04:24:05 PM PST 24
Peak memory 194752 kb
Host smart-86f3a33f-49ba-4bed-980a-499ebfca675f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955762756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2955762756
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3360957656
Short name T758
Test name
Test status
Simulation time 16868972 ps
CPU time 0.63 seconds
Started Feb 28 04:23:58 PM PST 24
Finished Feb 28 04:23:59 PM PST 24
Peak memory 194972 kb
Host smart-8962af70-3f39-4a74-bec6-f845e6ef5d59
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360957656 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3360957656
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2248772443
Short name T717
Test name
Test status
Simulation time 47464373 ps
CPU time 2.34 seconds
Started Feb 28 04:23:58 PM PST 24
Finished Feb 28 04:24:01 PM PST 24
Peak memory 198480 kb
Host smart-f8596315-a9a8-496f-8360-794ec7a7ec01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248772443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2248772443
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3442026204
Short name T107
Test name
Test status
Simulation time 1470255507 ps
CPU time 1.3 seconds
Started Feb 28 04:25:55 PM PST 24
Finished Feb 28 04:25:56 PM PST 24
Peak memory 198276 kb
Host smart-a2af0ef4-014d-425a-8206-8a843c478a88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442026204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3442026204
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3378752021
Short name T733
Test name
Test status
Simulation time 31462513 ps
CPU time 0.84 seconds
Started Feb 28 04:23:42 PM PST 24
Finished Feb 28 04:23:45 PM PST 24
Peak memory 196480 kb
Host smart-29af577e-04be-4eaa-9a60-3be635af13c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378752021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3378752021
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.995138468
Short name T810
Test name
Test status
Simulation time 126130252 ps
CPU time 1.37 seconds
Started Feb 28 04:23:56 PM PST 24
Finished Feb 28 04:23:58 PM PST 24
Peak memory 197100 kb
Host smart-c088b10a-991f-49c8-8125-91c3568e14b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995138468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.995138468
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1907638227
Short name T81
Test name
Test status
Simulation time 17713714 ps
CPU time 0.61 seconds
Started Feb 28 04:23:55 PM PST 24
Finished Feb 28 04:23:56 PM PST 24
Peak memory 194780 kb
Host smart-95ffcee6-388a-425e-8221-026cb06d4d55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907638227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1907638227
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.4077258946
Short name T792
Test name
Test status
Simulation time 32531872 ps
CPU time 0.87 seconds
Started Feb 28 04:23:39 PM PST 24
Finished Feb 28 04:23:40 PM PST 24
Peak memory 198320 kb
Host smart-a8cd2889-e3b3-4165-81de-af5384985b47
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077258946 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.4077258946
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.4264319141
Short name T778
Test name
Test status
Simulation time 14846674 ps
CPU time 0.57 seconds
Started Feb 28 04:23:30 PM PST 24
Finished Feb 28 04:23:31 PM PST 24
Peak memory 194988 kb
Host smart-10506ea0-796f-4918-b402-bda0e3a4883c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264319141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.4264319141
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3039845908
Short name T721
Test name
Test status
Simulation time 27522262 ps
CPU time 0.64 seconds
Started Feb 28 04:23:31 PM PST 24
Finished Feb 28 04:23:32 PM PST 24
Peak memory 194284 kb
Host smart-acde055a-4a0c-4554-bdc9-566acfc04106
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039845908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3039845908
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3769037196
Short name T95
Test name
Test status
Simulation time 42598791 ps
CPU time 0.64 seconds
Started Feb 28 04:23:33 PM PST 24
Finished Feb 28 04:23:34 PM PST 24
Peak memory 195440 kb
Host smart-67b01182-4167-485a-af66-9914585fce7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769037196 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3769037196
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4102088678
Short name T718
Test name
Test status
Simulation time 510358199 ps
CPU time 2.38 seconds
Started Feb 28 04:23:48 PM PST 24
Finished Feb 28 04:23:51 PM PST 24
Peak memory 198572 kb
Host smart-941e7c8c-2c8e-4067-a99a-31ac567b7cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102088678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.4102088678
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.16423022
Short name T769
Test name
Test status
Simulation time 180846047 ps
CPU time 1.28 seconds
Started Feb 28 04:23:42 PM PST 24
Finished Feb 28 04:23:49 PM PST 24
Peak memory 198412 kb
Host smart-3c3e7980-8bb5-4c57-bbb5-72181d0b9409
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16423022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_tl_intg_err.16423022
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.385492391
Short name T748
Test name
Test status
Simulation time 30390775 ps
CPU time 0.61 seconds
Started Feb 28 04:25:52 PM PST 24
Finished Feb 28 04:25:52 PM PST 24
Peak memory 193980 kb
Host smart-5d927678-edd4-4ef6-87e5-e8aefd85ceaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385492391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.385492391
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3476575651
Short name T715
Test name
Test status
Simulation time 13585535 ps
CPU time 0.67 seconds
Started Feb 28 04:25:33 PM PST 24
Finished Feb 28 04:25:34 PM PST 24
Peak memory 192784 kb
Host smart-bbff7f38-bc8b-49f1-be9a-0ffc0d35faba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476575651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3476575651
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2718504651
Short name T741
Test name
Test status
Simulation time 97880124 ps
CPU time 0.55 seconds
Started Feb 28 04:23:58 PM PST 24
Finished Feb 28 04:23:59 PM PST 24
Peak memory 194140 kb
Host smart-f52025fa-88f9-4186-8baa-783773620c53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718504651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2718504651
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2146001993
Short name T781
Test name
Test status
Simulation time 32930587 ps
CPU time 0.58 seconds
Started Feb 28 04:23:43 PM PST 24
Finished Feb 28 04:23:45 PM PST 24
Peak memory 194592 kb
Host smart-f3c420f5-eb1a-4a34-ad14-dbc4436b3aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146001993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2146001993
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3799876823
Short name T835
Test name
Test status
Simulation time 62547973 ps
CPU time 0.65 seconds
Started Feb 28 04:24:08 PM PST 24
Finished Feb 28 04:24:09 PM PST 24
Peak memory 194776 kb
Host smart-6bdc2293-bd68-450b-a8f4-751ea70c1d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799876823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3799876823
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3845133376
Short name T725
Test name
Test status
Simulation time 25733954 ps
CPU time 0.63 seconds
Started Feb 28 04:23:57 PM PST 24
Finished Feb 28 04:23:58 PM PST 24
Peak memory 194764 kb
Host smart-f5f56c87-4b3c-4d6b-8b58-afe2dde88d3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845133376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3845133376
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3713666811
Short name T755
Test name
Test status
Simulation time 36556107 ps
CPU time 0.6 seconds
Started Feb 28 04:24:07 PM PST 24
Finished Feb 28 04:24:08 PM PST 24
Peak memory 194876 kb
Host smart-2c74cf1d-d04d-4ca3-a582-db4a10c1976f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713666811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3713666811
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1295923463
Short name T768
Test name
Test status
Simulation time 14224199 ps
CPU time 0.58 seconds
Started Feb 28 04:24:03 PM PST 24
Finished Feb 28 04:24:04 PM PST 24
Peak memory 194144 kb
Host smart-b5b4eabe-f6a1-4f9e-800f-6e510de347db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295923463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1295923463
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3079492512
Short name T819
Test name
Test status
Simulation time 11766380 ps
CPU time 0.61 seconds
Started Feb 28 04:24:02 PM PST 24
Finished Feb 28 04:24:03 PM PST 24
Peak memory 194856 kb
Host smart-cd5e0601-5b4a-4353-9d3d-dda852a865b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079492512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3079492512
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.831893588
Short name T749
Test name
Test status
Simulation time 41611326 ps
CPU time 0.58 seconds
Started Feb 28 04:24:33 PM PST 24
Finished Feb 28 04:24:34 PM PST 24
Peak memory 194816 kb
Host smart-0c67f822-9fd8-426f-a866-50572f672915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831893588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.831893588
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1963446632
Short name T824
Test name
Test status
Simulation time 164554662 ps
CPU time 0.61 seconds
Started Feb 28 04:23:37 PM PST 24
Finished Feb 28 04:23:37 PM PST 24
Peak memory 194524 kb
Host smart-c6232ca9-91fb-40d6-a74f-a6a2b7622c96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963446632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1963446632
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.842574234
Short name T834
Test name
Test status
Simulation time 374158926 ps
CPU time 3.36 seconds
Started Feb 28 04:23:27 PM PST 24
Finished Feb 28 04:23:30 PM PST 24
Peak memory 197624 kb
Host smart-a7f2bc47-1c0d-4631-8922-ba81ce83897f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842574234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.842574234
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3274264536
Short name T803
Test name
Test status
Simulation time 31213999 ps
CPU time 1.39 seconds
Started Feb 28 04:23:30 PM PST 24
Finished Feb 28 04:23:32 PM PST 24
Peak memory 198496 kb
Host smart-f0a6cbb7-f524-4cb5-8a29-279f6d2960e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274264536 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3274264536
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1362464483
Short name T761
Test name
Test status
Simulation time 32807240 ps
CPU time 0.57 seconds
Started Feb 28 04:23:38 PM PST 24
Finished Feb 28 04:23:39 PM PST 24
Peak memory 194660 kb
Host smart-cc0e560b-0ef2-47f4-8fa3-c429373a6921
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362464483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1362464483
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2709204292
Short name T812
Test name
Test status
Simulation time 14856972 ps
CPU time 0.6 seconds
Started Feb 28 04:23:21 PM PST 24
Finished Feb 28 04:23:23 PM PST 24
Peak memory 194760 kb
Host smart-9a94d995-934f-42c0-b2bf-eb6f0f1cf118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709204292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2709204292
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1367429650
Short name T74
Test name
Test status
Simulation time 23564843 ps
CPU time 0.74 seconds
Started Feb 28 04:23:46 PM PST 24
Finished Feb 28 04:23:48 PM PST 24
Peak memory 196648 kb
Host smart-f04aeb3e-fc4e-4d4e-90ea-fd1b5d25f1ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367429650 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1367429650
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3730291103
Short name T729
Test name
Test status
Simulation time 594192688 ps
CPU time 2.8 seconds
Started Feb 28 04:23:40 PM PST 24
Finished Feb 28 04:23:43 PM PST 24
Peak memory 198420 kb
Host smart-cc424f20-5f1d-4eda-ad10-5a68e203dbd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730291103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3730291103
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3371398527
Short name T31
Test name
Test status
Simulation time 1032745397 ps
CPU time 1.3 seconds
Started Feb 28 04:23:42 PM PST 24
Finished Feb 28 04:23:45 PM PST 24
Peak memory 198448 kb
Host smart-9988f0f7-29d4-4513-91f8-0b89451d5741
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371398527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3371398527
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1839028362
Short name T736
Test name
Test status
Simulation time 18905955 ps
CPU time 0.56 seconds
Started Feb 28 04:24:00 PM PST 24
Finished Feb 28 04:24:01 PM PST 24
Peak memory 194048 kb
Host smart-1b484f8c-4198-4247-b2af-7ff4c1a8b40c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839028362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1839028362
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.377456298
Short name T752
Test name
Test status
Simulation time 11342478 ps
CPU time 0.61 seconds
Started Feb 28 04:23:52 PM PST 24
Finished Feb 28 04:23:53 PM PST 24
Peak memory 194896 kb
Host smart-62a80a50-c4e2-4759-b655-087f88bc695e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377456298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.377456298
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.700337483
Short name T745
Test name
Test status
Simulation time 26299700 ps
CPU time 0.61 seconds
Started Feb 28 04:24:13 PM PST 24
Finished Feb 28 04:24:13 PM PST 24
Peak memory 194136 kb
Host smart-19696ff5-fc5e-4895-9966-549e2845b55b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700337483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.700337483
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1750250719
Short name T751
Test name
Test status
Simulation time 16190362 ps
CPU time 0.59 seconds
Started Feb 28 04:23:52 PM PST 24
Finished Feb 28 04:23:53 PM PST 24
Peak memory 194108 kb
Host smart-d779165c-6076-4991-a89b-5190ec2268ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750250719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1750250719
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2627821148
Short name T776
Test name
Test status
Simulation time 134780126 ps
CPU time 0.6 seconds
Started Feb 28 04:24:09 PM PST 24
Finished Feb 28 04:24:10 PM PST 24
Peak memory 194232 kb
Host smart-deaaef3f-31bb-4965-8aca-1dab3c5f747f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627821148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2627821148
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.53658315
Short name T740
Test name
Test status
Simulation time 10902926 ps
CPU time 0.6 seconds
Started Feb 28 04:24:00 PM PST 24
Finished Feb 28 04:24:01 PM PST 24
Peak memory 194680 kb
Host smart-3becf793-5635-4cc4-8242-a8e5b29f94a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53658315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.53658315
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3516243737
Short name T762
Test name
Test status
Simulation time 20744216 ps
CPU time 0.61 seconds
Started Feb 28 04:23:57 PM PST 24
Finished Feb 28 04:23:58 PM PST 24
Peak memory 194756 kb
Host smart-494cd635-7437-4b0e-8d00-60b295a00000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516243737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3516243737
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1635996232
Short name T802
Test name
Test status
Simulation time 145149657 ps
CPU time 0.59 seconds
Started Feb 28 04:24:05 PM PST 24
Finished Feb 28 04:24:05 PM PST 24
Peak memory 194220 kb
Host smart-23a77942-7909-4f7b-9232-08b76e8831d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635996232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1635996232
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1187545308
Short name T727
Test name
Test status
Simulation time 22027553 ps
CPU time 0.62 seconds
Started Feb 28 04:24:01 PM PST 24
Finished Feb 28 04:24:02 PM PST 24
Peak memory 194796 kb
Host smart-7c18522d-b064-42ae-a843-c5b2e8823256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187545308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1187545308
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.545767706
Short name T723
Test name
Test status
Simulation time 18391338 ps
CPU time 0.6 seconds
Started Feb 28 04:24:11 PM PST 24
Finished Feb 28 04:24:12 PM PST 24
Peak memory 194192 kb
Host smart-a6e4d6b3-086d-4a70-b0d2-67b84a0c9aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545767706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.545767706
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.919640959
Short name T82
Test name
Test status
Simulation time 41522015 ps
CPU time 0.66 seconds
Started Feb 28 04:23:38 PM PST 24
Finished Feb 28 04:23:39 PM PST 24
Peak memory 194448 kb
Host smart-161d39d0-9336-4a4d-be26-e9be10d51061
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919640959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.919640959
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1661721668
Short name T79
Test name
Test status
Simulation time 1287206636 ps
CPU time 3.49 seconds
Started Feb 28 04:23:34 PM PST 24
Finished Feb 28 04:23:38 PM PST 24
Peak memory 198512 kb
Host smart-025db731-7622-4a5a-9d5c-db04a00ae77e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661721668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1661721668
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1536414117
Short name T814
Test name
Test status
Simulation time 47123745 ps
CPU time 0.62 seconds
Started Feb 28 04:23:30 PM PST 24
Finished Feb 28 04:23:31 PM PST 24
Peak memory 194812 kb
Host smart-da37cd34-0fba-4943-b4cc-2b2fe4a49fce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536414117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1536414117
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1774044736
Short name T839
Test name
Test status
Simulation time 64662295 ps
CPU time 1.6 seconds
Started Feb 28 04:23:59 PM PST 24
Finished Feb 28 04:24:01 PM PST 24
Peak memory 198568 kb
Host smart-3d6ab851-948f-43b9-bd30-026186035a77
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774044736 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1774044736
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.201917535
Short name T80
Test name
Test status
Simulation time 13547343 ps
CPU time 0.58 seconds
Started Feb 28 04:23:57 PM PST 24
Finished Feb 28 04:23:58 PM PST 24
Peak memory 195960 kb
Host smart-0639b623-0f4a-4c02-8770-98c6f53729fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201917535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.201917535
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.741362663
Short name T813
Test name
Test status
Simulation time 41447632 ps
CPU time 0.59 seconds
Started Feb 28 04:23:48 PM PST 24
Finished Feb 28 04:23:50 PM PST 24
Peak memory 194068 kb
Host smart-c1da5490-7cf7-43b7-af16-590a9b5d465b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741362663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.741362663
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.904983765
Short name T770
Test name
Test status
Simulation time 180275605 ps
CPU time 0.68 seconds
Started Feb 28 04:23:42 PM PST 24
Finished Feb 28 04:23:45 PM PST 24
Peak memory 194700 kb
Host smart-5e7d8098-8a17-40f8-8e20-62e183ccaef0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904983765 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.904983765
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3240159595
Short name T734
Test name
Test status
Simulation time 324550138 ps
CPU time 3.53 seconds
Started Feb 28 04:23:56 PM PST 24
Finished Feb 28 04:24:00 PM PST 24
Peak memory 198508 kb
Host smart-54a1ea54-fb5d-42b2-9d47-979305ba6fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240159595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3240159595
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2729085610
Short name T785
Test name
Test status
Simulation time 148993678 ps
CPU time 1.46 seconds
Started Feb 28 04:23:52 PM PST 24
Finished Feb 28 04:23:53 PM PST 24
Peak memory 198572 kb
Host smart-74c75e62-9832-4045-9781-678fa09282af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729085610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2729085610
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2964669752
Short name T739
Test name
Test status
Simulation time 23521350 ps
CPU time 0.62 seconds
Started Feb 28 04:23:57 PM PST 24
Finished Feb 28 04:23:58 PM PST 24
Peak memory 194076 kb
Host smart-7f42e3cb-a746-4ca2-8465-a506c764efb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964669752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2964669752
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2498353841
Short name T828
Test name
Test status
Simulation time 54006811 ps
CPU time 0.6 seconds
Started Feb 28 04:24:04 PM PST 24
Finished Feb 28 04:24:04 PM PST 24
Peak memory 194036 kb
Host smart-e2c7fb75-8a41-4470-ab41-713d9cd106a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498353841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2498353841
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1486142967
Short name T720
Test name
Test status
Simulation time 12650574 ps
CPU time 0.57 seconds
Started Feb 28 04:24:09 PM PST 24
Finished Feb 28 04:24:09 PM PST 24
Peak memory 194724 kb
Host smart-c4804f00-9a2f-48df-9859-032fba174089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486142967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1486142967
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3244664522
Short name T742
Test name
Test status
Simulation time 46637810 ps
CPU time 0.62 seconds
Started Feb 28 04:24:20 PM PST 24
Finished Feb 28 04:24:21 PM PST 24
Peak memory 194228 kb
Host smart-990ff196-3ff0-4ce6-8582-5b1646bdf6bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244664522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3244664522
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1653256247
Short name T714
Test name
Test status
Simulation time 28057953 ps
CPU time 0.61 seconds
Started Feb 28 04:24:07 PM PST 24
Finished Feb 28 04:24:08 PM PST 24
Peak memory 194180 kb
Host smart-897eb04f-1577-410d-81cb-30e1deb711ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653256247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1653256247
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1038580197
Short name T786
Test name
Test status
Simulation time 26175935 ps
CPU time 0.59 seconds
Started Feb 28 04:24:06 PM PST 24
Finished Feb 28 04:24:07 PM PST 24
Peak memory 194780 kb
Host smart-eecce623-bd62-4583-bd3a-80a68b3f53ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038580197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1038580197
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.498017618
Short name T840
Test name
Test status
Simulation time 159070778 ps
CPU time 0.6 seconds
Started Feb 28 04:24:16 PM PST 24
Finished Feb 28 04:24:17 PM PST 24
Peak memory 194764 kb
Host smart-0d5c08c7-63b6-4ca0-aadf-241bc203e9ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498017618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.498017618
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3038199444
Short name T823
Test name
Test status
Simulation time 30662490 ps
CPU time 0.58 seconds
Started Feb 28 04:24:07 PM PST 24
Finished Feb 28 04:24:08 PM PST 24
Peak memory 194164 kb
Host smart-27e145d6-3fd3-40b8-b1a2-92c8f5ce8425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038199444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3038199444
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3545490151
Short name T713
Test name
Test status
Simulation time 14530534 ps
CPU time 0.65 seconds
Started Feb 28 04:24:09 PM PST 24
Finished Feb 28 04:24:10 PM PST 24
Peak memory 194172 kb
Host smart-9a801403-c8e9-46c2-9b0e-bc923f077864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545490151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3545490151
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.230944012
Short name T793
Test name
Test status
Simulation time 29680516 ps
CPU time 0.57 seconds
Started Feb 28 04:24:08 PM PST 24
Finished Feb 28 04:24:09 PM PST 24
Peak memory 194100 kb
Host smart-b79aa372-2b8c-4f11-a9cd-3e22baaef8b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230944012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.230944012
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3799433291
Short name T754
Test name
Test status
Simulation time 43833152 ps
CPU time 0.78 seconds
Started Feb 28 04:23:46 PM PST 24
Finished Feb 28 04:23:52 PM PST 24
Peak memory 197512 kb
Host smart-9aea55cc-4c9e-490b-b52f-0d42614f074f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799433291 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3799433291
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1864482868
Short name T88
Test name
Test status
Simulation time 15874152 ps
CPU time 0.64 seconds
Started Feb 28 04:23:45 PM PST 24
Finished Feb 28 04:23:46 PM PST 24
Peak memory 195988 kb
Host smart-6f7e820d-193d-40ad-8f53-4241b1f3ecd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864482868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1864482868
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.218273058
Short name T790
Test name
Test status
Simulation time 17453748 ps
CPU time 0.6 seconds
Started Feb 28 04:24:07 PM PST 24
Finished Feb 28 04:24:07 PM PST 24
Peak memory 194236 kb
Host smart-5b0df05f-1972-4220-acad-b76c20e4f716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218273058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.218273058
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.4040651983
Short name T780
Test name
Test status
Simulation time 107139224 ps
CPU time 0.72 seconds
Started Feb 28 04:23:37 PM PST 24
Finished Feb 28 04:23:38 PM PST 24
Peak memory 196144 kb
Host smart-01f16eb6-4ac8-4e18-844f-d1ae4ba8a804
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040651983 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.4040651983
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2018980196
Short name T801
Test name
Test status
Simulation time 312251899 ps
CPU time 1.23 seconds
Started Feb 28 04:23:43 PM PST 24
Finished Feb 28 04:23:45 PM PST 24
Peak memory 198456 kb
Host smart-bef564ec-c940-47ca-b1ed-19b95bb49274
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018980196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2018980196
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3085336150
Short name T775
Test name
Test status
Simulation time 216074320 ps
CPU time 0.86 seconds
Started Feb 28 04:23:39 PM PST 24
Finished Feb 28 04:23:40 PM PST 24
Peak memory 197720 kb
Host smart-ec482172-eb8d-4cf6-8de3-94f657309199
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085336150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3085336150
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.831239877
Short name T811
Test name
Test status
Simulation time 30013826 ps
CPU time 0.79 seconds
Started Feb 28 04:23:46 PM PST 24
Finished Feb 28 04:23:47 PM PST 24
Peak memory 198284 kb
Host smart-70b5dde9-ee34-4d76-994e-8bfc6228ac2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831239877 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.831239877
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.142998107
Short name T757
Test name
Test status
Simulation time 113616587 ps
CPU time 0.62 seconds
Started Feb 28 04:23:33 PM PST 24
Finished Feb 28 04:23:34 PM PST 24
Peak memory 195408 kb
Host smart-df8d8cd4-7107-4009-becd-ea9f01c5c61d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142998107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.142998107
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3156958455
Short name T820
Test name
Test status
Simulation time 13351422 ps
CPU time 0.56 seconds
Started Feb 28 04:23:44 PM PST 24
Finished Feb 28 04:23:46 PM PST 24
Peak memory 194044 kb
Host smart-4be91e1e-3e31-4fda-b678-66059058aee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156958455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3156958455
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.4254364796
Short name T837
Test name
Test status
Simulation time 46293083 ps
CPU time 0.83 seconds
Started Feb 28 04:23:43 PM PST 24
Finished Feb 28 04:23:45 PM PST 24
Peak memory 196400 kb
Host smart-db6fbaf5-efcf-4b2c-b48d-02997b1b8b34
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254364796 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.4254364796
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3527238347
Short name T825
Test name
Test status
Simulation time 182347542 ps
CPU time 1.23 seconds
Started Feb 28 04:23:35 PM PST 24
Finished Feb 28 04:23:36 PM PST 24
Peak memory 198388 kb
Host smart-fca0f69e-26ec-4e35-a1e3-30a31b51af78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527238347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3527238347
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3799572724
Short name T32
Test name
Test status
Simulation time 119507823 ps
CPU time 1.41 seconds
Started Feb 28 04:23:44 PM PST 24
Finished Feb 28 04:23:47 PM PST 24
Peak memory 198508 kb
Host smart-e2f63027-2c5b-4ffc-a08d-042ceb23d210
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799572724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3799572724
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.460000804
Short name T772
Test name
Test status
Simulation time 67260435 ps
CPU time 0.86 seconds
Started Feb 28 04:23:41 PM PST 24
Finished Feb 28 04:23:45 PM PST 24
Peak memory 198384 kb
Host smart-1b3b6414-c12f-477f-a667-a82cb34acbbd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460000804 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.460000804
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1920810785
Short name T809
Test name
Test status
Simulation time 45373400 ps
CPU time 0.59 seconds
Started Feb 28 04:23:42 PM PST 24
Finished Feb 28 04:23:44 PM PST 24
Peak memory 195572 kb
Host smart-447a03f3-210e-429a-8ef0-34f36faeaf7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920810785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1920810785
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2770262400
Short name T777
Test name
Test status
Simulation time 15963756 ps
CPU time 0.59 seconds
Started Feb 28 04:23:36 PM PST 24
Finished Feb 28 04:23:37 PM PST 24
Peak memory 194756 kb
Host smart-b166712f-a508-4d9b-bfb6-e660b2a709c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770262400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2770262400
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1544668780
Short name T92
Test name
Test status
Simulation time 71640291 ps
CPU time 0.74 seconds
Started Feb 28 04:24:01 PM PST 24
Finished Feb 28 04:24:02 PM PST 24
Peak memory 196540 kb
Host smart-aeb97756-971f-4fbe-84f3-a2bd041f507e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544668780 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1544668780
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2849331525
Short name T766
Test name
Test status
Simulation time 377500904 ps
CPU time 1.71 seconds
Started Feb 28 04:23:45 PM PST 24
Finished Feb 28 04:23:48 PM PST 24
Peak memory 198444 kb
Host smart-c7d4dfa1-7576-449d-8e55-d6301a6babf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849331525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2849331525
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2529600941
Short name T829
Test name
Test status
Simulation time 128393627 ps
CPU time 1.43 seconds
Started Feb 28 04:24:00 PM PST 24
Finished Feb 28 04:24:02 PM PST 24
Peak memory 198496 kb
Host smart-4bf07ab5-53ab-409d-a190-557a0b596064
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529600941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2529600941
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1081703989
Short name T730
Test name
Test status
Simulation time 63376253 ps
CPU time 0.91 seconds
Started Feb 28 04:23:41 PM PST 24
Finished Feb 28 04:23:45 PM PST 24
Peak memory 198260 kb
Host smart-4420028f-8776-4de1-88f6-e70ecfd0873b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081703989 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1081703989
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.878621294
Short name T85
Test name
Test status
Simulation time 42965058 ps
CPU time 0.67 seconds
Started Feb 28 04:23:47 PM PST 24
Finished Feb 28 04:23:48 PM PST 24
Peak memory 195228 kb
Host smart-57760994-4c1d-408b-88b3-a08da549585e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878621294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.878621294
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.4291862687
Short name T763
Test name
Test status
Simulation time 109314817 ps
CPU time 0.59 seconds
Started Feb 28 04:23:55 PM PST 24
Finished Feb 28 04:23:55 PM PST 24
Peak memory 194868 kb
Host smart-61558974-eafe-4a5b-be58-bc0b43fe3796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291862687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.4291862687
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1220481495
Short name T91
Test name
Test status
Simulation time 19541154 ps
CPU time 0.61 seconds
Started Feb 28 04:23:42 PM PST 24
Finished Feb 28 04:23:45 PM PST 24
Peak memory 194556 kb
Host smart-34402220-39e7-489e-bba0-bdb35b1467b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220481495 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1220481495
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1109619155
Short name T731
Test name
Test status
Simulation time 36241778 ps
CPU time 1.18 seconds
Started Feb 28 04:23:52 PM PST 24
Finished Feb 28 04:23:53 PM PST 24
Peak memory 198584 kb
Host smart-8b8a8d93-3b35-4e1a-b8af-b081e8211aa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109619155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1109619155
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.945225897
Short name T783
Test name
Test status
Simulation time 45849967 ps
CPU time 0.86 seconds
Started Feb 28 04:24:10 PM PST 24
Finished Feb 28 04:24:10 PM PST 24
Peak memory 198120 kb
Host smart-8dcb2d44-c3d4-4732-86ad-5ad861774c0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945225897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.945225897
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.34028212
Short name T726
Test name
Test status
Simulation time 54590281 ps
CPU time 0.69 seconds
Started Feb 28 04:23:47 PM PST 24
Finished Feb 28 04:23:49 PM PST 24
Peak memory 197892 kb
Host smart-d6523d3b-1d76-4cf9-8814-f5d9580df7eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34028212 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.34028212
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.4203840709
Short name T747
Test name
Test status
Simulation time 28682957 ps
CPU time 0.56 seconds
Started Feb 28 04:23:42 PM PST 24
Finished Feb 28 04:23:44 PM PST 24
Peak memory 193780 kb
Host smart-6d546109-b907-4d5f-864b-99121b39aa43
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203840709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.4203840709
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1092720654
Short name T722
Test name
Test status
Simulation time 54515236 ps
CPU time 0.61 seconds
Started Feb 28 04:24:01 PM PST 24
Finished Feb 28 04:24:02 PM PST 24
Peak memory 193988 kb
Host smart-abafc21f-9ac2-477a-aec4-846e8f9117f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092720654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1092720654
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2238713367
Short name T96
Test name
Test status
Simulation time 103045826 ps
CPU time 0.73 seconds
Started Feb 28 04:23:59 PM PST 24
Finished Feb 28 04:24:00 PM PST 24
Peak memory 197396 kb
Host smart-826860e9-9332-45ea-9bc5-9ff463536c76
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238713367 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2238713367
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1663368703
Short name T831
Test name
Test status
Simulation time 341628101 ps
CPU time 1.51 seconds
Started Feb 28 04:23:46 PM PST 24
Finished Feb 28 04:23:49 PM PST 24
Peak memory 198508 kb
Host smart-545d6336-920e-4ef1-8b9c-cac4a647b976
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663368703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1663368703
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3855454112
Short name T30
Test name
Test status
Simulation time 60471828 ps
CPU time 0.85 seconds
Started Feb 28 04:23:43 PM PST 24
Finished Feb 28 04:23:50 PM PST 24
Peak memory 198336 kb
Host smart-cd7051c1-ea49-4001-af9e-63874cd96b0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855454112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3855454112
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.319552052
Short name T529
Test name
Test status
Simulation time 24265671 ps
CPU time 0.6 seconds
Started Feb 28 05:19:41 PM PST 24
Finished Feb 28 05:19:42 PM PST 24
Peak memory 194672 kb
Host smart-b79c53e5-1efb-49d7-b595-049e846b00ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319552052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.319552052
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.941897771
Short name T502
Test name
Test status
Simulation time 126779143 ps
CPU time 0.96 seconds
Started Feb 28 05:19:42 PM PST 24
Finished Feb 28 05:19:43 PM PST 24
Peak memory 196556 kb
Host smart-84584b79-b7e6-4496-9735-277ceacf8168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941897771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.941897771
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.195945984
Short name T293
Test name
Test status
Simulation time 244151207 ps
CPU time 12.44 seconds
Started Feb 28 05:19:42 PM PST 24
Finished Feb 28 05:19:55 PM PST 24
Peak memory 198084 kb
Host smart-19dc2ef8-6b5a-41bb-9922-eefe7783f382
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195945984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.195945984
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.876811186
Short name T401
Test name
Test status
Simulation time 247287880 ps
CPU time 0.82 seconds
Started Feb 28 05:19:43 PM PST 24
Finished Feb 28 05:19:44 PM PST 24
Peak memory 196572 kb
Host smart-cbaf78a4-92f8-4670-ae51-872351b1a1e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876811186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.876811186
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1427566376
Short name T606
Test name
Test status
Simulation time 45923839 ps
CPU time 0.94 seconds
Started Feb 28 05:19:42 PM PST 24
Finished Feb 28 05:19:43 PM PST 24
Peak memory 196716 kb
Host smart-c579c857-f176-4530-9a33-f834303460a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427566376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1427566376
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3545736216
Short name T416
Test name
Test status
Simulation time 25567257 ps
CPU time 1.13 seconds
Started Feb 28 05:19:43 PM PST 24
Finished Feb 28 05:19:44 PM PST 24
Peak memory 197136 kb
Host smart-ce20beb8-2abb-4a81-9482-dc3cf1a787b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545736216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3545736216
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3204946180
Short name T133
Test name
Test status
Simulation time 126013841 ps
CPU time 1.06 seconds
Started Feb 28 05:19:43 PM PST 24
Finished Feb 28 05:19:44 PM PST 24
Peak memory 195408 kb
Host smart-50898178-8bc5-4c91-8860-17f0f3609dc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204946180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3204946180
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1108621690
Short name T294
Test name
Test status
Simulation time 98176583 ps
CPU time 1.28 seconds
Started Feb 28 05:19:44 PM PST 24
Finished Feb 28 05:19:45 PM PST 24
Peak memory 197148 kb
Host smart-b64b171e-a275-41e6-aa57-88a3f3d461c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108621690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1108621690
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3470362322
Short name T246
Test name
Test status
Simulation time 119758585 ps
CPU time 1.34 seconds
Started Feb 28 05:19:43 PM PST 24
Finished Feb 28 05:19:45 PM PST 24
Peak memory 195948 kb
Host smart-251fc689-6156-4d08-bf49-bf3e4c60c8ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470362322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3470362322
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1079162522
Short name T519
Test name
Test status
Simulation time 377832008 ps
CPU time 4.34 seconds
Started Feb 28 05:19:43 PM PST 24
Finished Feb 28 05:19:47 PM PST 24
Peak memory 198068 kb
Host smart-e5e9e157-7403-439e-8ebe-d7b4457a5235
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079162522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1079162522
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.502530173
Short name T35
Test name
Test status
Simulation time 144215204 ps
CPU time 0.9 seconds
Started Feb 28 05:19:43 PM PST 24
Finished Feb 28 05:19:44 PM PST 24
Peak memory 213756 kb
Host smart-98f1d940-1c41-4ae8-9599-4b9c0e77cb1c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502530173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.502530173
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.2815242929
Short name T608
Test name
Test status
Simulation time 29777024 ps
CPU time 0.87 seconds
Started Feb 28 05:19:45 PM PST 24
Finished Feb 28 05:19:46 PM PST 24
Peak memory 196368 kb
Host smart-e962dedb-44ea-4a3c-98f0-126a892c5cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815242929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2815242929
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2297399182
Short name T351
Test name
Test status
Simulation time 228793725 ps
CPU time 1.24 seconds
Started Feb 28 05:19:41 PM PST 24
Finished Feb 28 05:19:42 PM PST 24
Peak memory 196792 kb
Host smart-a9c67b04-782d-4580-b97c-f52b0abe962d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297399182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2297399182
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2587986657
Short name T607
Test name
Test status
Simulation time 3420801056 ps
CPU time 50.94 seconds
Started Feb 28 05:19:42 PM PST 24
Finished Feb 28 05:20:33 PM PST 24
Peak memory 198232 kb
Host smart-51624943-807d-4624-88d6-6018b7f20807
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587986657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2587986657
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2806211052
Short name T117
Test name
Test status
Simulation time 37903209 ps
CPU time 0.7 seconds
Started Feb 28 05:19:44 PM PST 24
Finished Feb 28 05:19:45 PM PST 24
Peak memory 194868 kb
Host smart-eb1c45f3-9341-4718-8883-55575a08ee37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806211052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2806211052
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3681946572
Short name T373
Test name
Test status
Simulation time 114133276 ps
CPU time 4.07 seconds
Started Feb 28 05:19:49 PM PST 24
Finished Feb 28 05:19:53 PM PST 24
Peak memory 196380 kb
Host smart-792f7251-afee-4f84-b803-43efa0131489
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681946572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3681946572
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1519823927
Short name T525
Test name
Test status
Simulation time 141765066 ps
CPU time 1.03 seconds
Started Feb 28 05:19:47 PM PST 24
Finished Feb 28 05:19:48 PM PST 24
Peak memory 197308 kb
Host smart-3b3b5df4-893f-49c1-ac81-5279883cc93f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519823927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1519823927
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2600332230
Short name T503
Test name
Test status
Simulation time 14709292 ps
CPU time 0.68 seconds
Started Feb 28 05:19:43 PM PST 24
Finished Feb 28 05:19:44 PM PST 24
Peak memory 194388 kb
Host smart-f2c79553-901d-450b-9168-b9c3e17a8c51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600332230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2600332230
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.17791359
Short name T268
Test name
Test status
Simulation time 64448324 ps
CPU time 2.6 seconds
Started Feb 28 05:19:50 PM PST 24
Finished Feb 28 05:19:52 PM PST 24
Peak memory 198208 kb
Host smart-89f63948-7685-405e-96c9-78a0ed073f78
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17791359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.gpio_intr_with_filter_rand_intr_event.17791359
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.113016952
Short name T352
Test name
Test status
Simulation time 127695785 ps
CPU time 2.74 seconds
Started Feb 28 05:19:50 PM PST 24
Finished Feb 28 05:19:53 PM PST 24
Peak memory 197092 kb
Host smart-f4b48857-c5bc-4db8-a0e5-be945e5362b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113016952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.113016952
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3861956581
Short name T141
Test name
Test status
Simulation time 59015056 ps
CPU time 1.35 seconds
Started Feb 28 05:19:47 PM PST 24
Finished Feb 28 05:19:48 PM PST 24
Peak memory 196932 kb
Host smart-8f28d095-2ac4-4d9d-8169-2186efa7aacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861956581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3861956581
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3820618736
Short name T138
Test name
Test status
Simulation time 45260429 ps
CPU time 0.93 seconds
Started Feb 28 05:19:42 PM PST 24
Finished Feb 28 05:19:43 PM PST 24
Peak memory 196060 kb
Host smart-498db97e-e4ca-4d7b-89fa-c45a92bd7a10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820618736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3820618736
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3679118564
Short name T175
Test name
Test status
Simulation time 264899917 ps
CPU time 3.5 seconds
Started Feb 28 05:19:45 PM PST 24
Finished Feb 28 05:19:48 PM PST 24
Peak memory 198240 kb
Host smart-2f1eacaf-709a-403c-9b77-d7054fde1b24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679118564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3679118564
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.2861296256
Short name T413
Test name
Test status
Simulation time 359490465 ps
CPU time 1.56 seconds
Started Feb 28 05:19:43 PM PST 24
Finished Feb 28 05:19:44 PM PST 24
Peak memory 196896 kb
Host smart-dffb478e-9c8b-4364-905e-0f370a5f3a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861296256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2861296256
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.236768174
Short name T221
Test name
Test status
Simulation time 72462647 ps
CPU time 1.11 seconds
Started Feb 28 05:19:43 PM PST 24
Finished Feb 28 05:19:44 PM PST 24
Peak memory 195588 kb
Host smart-cf92029a-0a17-4d0b-80d7-e4dc7232918f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236768174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.236768174
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3438732180
Short name T15
Test name
Test status
Simulation time 6668429283 ps
CPU time 46.28 seconds
Started Feb 28 05:19:47 PM PST 24
Finished Feb 28 05:20:33 PM PST 24
Peak memory 198244 kb
Host smart-fb31a71c-bef0-4639-bbdc-94397287405c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438732180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3438732180
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.3001901331
Short name T704
Test name
Test status
Simulation time 69489741504 ps
CPU time 521.36 seconds
Started Feb 28 05:19:50 PM PST 24
Finished Feb 28 05:28:32 PM PST 24
Peak memory 198396 kb
Host smart-b79d0322-bc79-44c5-8d8f-fc8fe4cb1acf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3001901331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.3001901331
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.505772986
Short name T271
Test name
Test status
Simulation time 25994702 ps
CPU time 0.62 seconds
Started Feb 28 05:20:20 PM PST 24
Finished Feb 28 05:20:20 PM PST 24
Peak memory 193968 kb
Host smart-54e86c0f-940c-4a71-8d12-13698f6da46a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505772986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.505772986
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.355837455
Short name T232
Test name
Test status
Simulation time 25460417 ps
CPU time 0.75 seconds
Started Feb 28 05:20:20 PM PST 24
Finished Feb 28 05:20:21 PM PST 24
Peak memory 194288 kb
Host smart-3af983ea-72ee-47b8-b081-c8e0c9b196bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355837455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.355837455
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.102713723
Short name T648
Test name
Test status
Simulation time 833640611 ps
CPU time 27.71 seconds
Started Feb 28 05:20:23 PM PST 24
Finished Feb 28 05:20:51 PM PST 24
Peak memory 196280 kb
Host smart-79d5785e-75fe-4ef5-a458-e870a9865e09
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102713723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.102713723
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1661650967
Short name T21
Test name
Test status
Simulation time 83453564 ps
CPU time 1.06 seconds
Started Feb 28 05:20:17 PM PST 24
Finished Feb 28 05:20:18 PM PST 24
Peak memory 196552 kb
Host smart-652345de-4529-4e61-9bc1-202710f481fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661650967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1661650967
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1029414100
Short name T517
Test name
Test status
Simulation time 81373977 ps
CPU time 1.39 seconds
Started Feb 28 05:20:16 PM PST 24
Finished Feb 28 05:20:18 PM PST 24
Peak memory 197028 kb
Host smart-dda80cb5-1ab9-4bbc-9286-c8d9ba8e905e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029414100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1029414100
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1460368720
Short name T436
Test name
Test status
Simulation time 214826976 ps
CPU time 2.36 seconds
Started Feb 28 05:20:16 PM PST 24
Finished Feb 28 05:20:18 PM PST 24
Peak memory 198136 kb
Host smart-d01c19d3-3b42-47f3-9a8a-0b0665ce725e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460368720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1460368720
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3613831285
Short name T123
Test name
Test status
Simulation time 39180818 ps
CPU time 1.23 seconds
Started Feb 28 05:20:16 PM PST 24
Finished Feb 28 05:20:17 PM PST 24
Peak memory 196116 kb
Host smart-3d1aabca-70e7-479b-9086-6939146f1cbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613831285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3613831285
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1561844548
Short name T469
Test name
Test status
Simulation time 25336976 ps
CPU time 0.85 seconds
Started Feb 28 05:20:24 PM PST 24
Finished Feb 28 05:20:25 PM PST 24
Peak memory 196020 kb
Host smart-bca88758-b575-4212-ab3d-3bbcef9adbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561844548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1561844548
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2281549151
Short name T702
Test name
Test status
Simulation time 176484863 ps
CPU time 1.21 seconds
Started Feb 28 05:20:16 PM PST 24
Finished Feb 28 05:20:18 PM PST 24
Peak memory 195900 kb
Host smart-81d4675f-4f45-4dd8-aa3e-992b9fea172b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281549151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2281549151
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3597570016
Short name T312
Test name
Test status
Simulation time 59893270 ps
CPU time 1.35 seconds
Started Feb 28 05:20:19 PM PST 24
Finished Feb 28 05:20:20 PM PST 24
Peak memory 198132 kb
Host smart-3c594264-2853-4ef2-92ae-2f8bc7ec816c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597570016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3597570016
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1746348835
Short name T392
Test name
Test status
Simulation time 206596674 ps
CPU time 1.16 seconds
Started Feb 28 05:20:13 PM PST 24
Finished Feb 28 05:20:14 PM PST 24
Peak memory 195860 kb
Host smart-bdeaa862-41c6-4a0f-aa4e-484414c35ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746348835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1746348835
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.895125825
Short name T375
Test name
Test status
Simulation time 30499977 ps
CPU time 0.8 seconds
Started Feb 28 05:20:14 PM PST 24
Finished Feb 28 05:20:15 PM PST 24
Peak memory 195288 kb
Host smart-1037e7df-0e4f-47ed-9974-95bf5af2a2bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895125825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.895125825
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1465434399
Short name T671
Test name
Test status
Simulation time 5787002549 ps
CPU time 165.14 seconds
Started Feb 28 05:20:16 PM PST 24
Finished Feb 28 05:23:01 PM PST 24
Peak memory 198224 kb
Host smart-94d72773-3cba-40bf-8c6f-673b2f851430
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465434399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1465434399
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.2091597817
Short name T52
Test name
Test status
Simulation time 292725906207 ps
CPU time 1403.85 seconds
Started Feb 28 05:20:24 PM PST 24
Finished Feb 28 05:43:48 PM PST 24
Peak memory 198304 kb
Host smart-1c8e4330-d6cc-4d71-bb72-400545082b1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2091597817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.2091597817
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1226150767
Short name T579
Test name
Test status
Simulation time 55623386 ps
CPU time 0.6 seconds
Started Feb 28 05:20:18 PM PST 24
Finished Feb 28 05:20:19 PM PST 24
Peak memory 194072 kb
Host smart-2996d1c7-8bae-4572-9be2-581193a49652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226150767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1226150767
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.824234705
Short name T684
Test name
Test status
Simulation time 83650553 ps
CPU time 0.87 seconds
Started Feb 28 05:20:24 PM PST 24
Finished Feb 28 05:20:25 PM PST 24
Peak memory 197108 kb
Host smart-347f064b-7579-42d6-8939-674514573dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824234705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.824234705
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.66109053
Short name T585
Test name
Test status
Simulation time 3098587860 ps
CPU time 16.39 seconds
Started Feb 28 05:20:23 PM PST 24
Finished Feb 28 05:20:40 PM PST 24
Peak memory 196936 kb
Host smart-161c28dc-e665-4f69-9305-be5d305f4c2a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66109053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stress
.66109053
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1777855856
Short name T279
Test name
Test status
Simulation time 225296718 ps
CPU time 0.7 seconds
Started Feb 28 05:20:18 PM PST 24
Finished Feb 28 05:20:19 PM PST 24
Peak memory 195440 kb
Host smart-6e11853b-dbf2-4ac6-a891-7ebc965ed38a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777855856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1777855856
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1599247788
Short name T335
Test name
Test status
Simulation time 53832862 ps
CPU time 0.94 seconds
Started Feb 28 05:20:22 PM PST 24
Finished Feb 28 05:20:23 PM PST 24
Peak memory 195916 kb
Host smart-8117f6f7-3e52-4648-9e0e-4621dad7bb58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599247788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1599247788
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2542273017
Short name T431
Test name
Test status
Simulation time 168790858 ps
CPU time 3.86 seconds
Started Feb 28 05:20:16 PM PST 24
Finished Feb 28 05:20:20 PM PST 24
Peak memory 198232 kb
Host smart-985dc2c7-ad3d-4915-908e-c2c3fabb0e99
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542273017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2542273017
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3197819688
Short name T543
Test name
Test status
Simulation time 568336751 ps
CPU time 2.45 seconds
Started Feb 28 05:20:22 PM PST 24
Finished Feb 28 05:20:24 PM PST 24
Peak memory 197268 kb
Host smart-82046a0a-508e-4be2-84d7-ae444b7e46ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197819688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3197819688
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2477620024
Short name T389
Test name
Test status
Simulation time 23490926 ps
CPU time 0.98 seconds
Started Feb 28 05:20:16 PM PST 24
Finished Feb 28 05:20:17 PM PST 24
Peak memory 196060 kb
Host smart-0c8f2551-1e36-406a-b040-62efcea870fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477620024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2477620024
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1163607359
Short name T390
Test name
Test status
Simulation time 56142417 ps
CPU time 1.44 seconds
Started Feb 28 05:20:19 PM PST 24
Finished Feb 28 05:20:20 PM PST 24
Peak memory 197040 kb
Host smart-eb5eca98-cdad-4100-863d-749d74a0008e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163607359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1163607359
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.289862812
Short name T444
Test name
Test status
Simulation time 146299518 ps
CPU time 3.55 seconds
Started Feb 28 05:20:17 PM PST 24
Finished Feb 28 05:20:20 PM PST 24
Peak memory 198084 kb
Host smart-64c61299-40a2-4823-b6b5-7cbec0438c5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289862812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.289862812
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1413237331
Short name T173
Test name
Test status
Simulation time 42165041 ps
CPU time 0.96 seconds
Started Feb 28 05:20:16 PM PST 24
Finished Feb 28 05:20:17 PM PST 24
Peak memory 196448 kb
Host smart-2ca76946-36b6-4be4-9a7d-5d953d1ce8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413237331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1413237331
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1306973566
Short name T505
Test name
Test status
Simulation time 266984044 ps
CPU time 0.96 seconds
Started Feb 28 05:20:22 PM PST 24
Finished Feb 28 05:20:24 PM PST 24
Peak memory 195588 kb
Host smart-43cfc454-c64d-4151-9f37-a0ed07b3ec9e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306973566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1306973566
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1942579636
Short name T491
Test name
Test status
Simulation time 17938244032 ps
CPU time 187.15 seconds
Started Feb 28 05:20:22 PM PST 24
Finished Feb 28 05:23:29 PM PST 24
Peak memory 197776 kb
Host smart-bb8b707d-f872-4edd-8adf-67305f22cbb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942579636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1942579636
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.998247483
Short name T551
Test name
Test status
Simulation time 47007811 ps
CPU time 0.57 seconds
Started Feb 28 05:20:26 PM PST 24
Finished Feb 28 05:20:27 PM PST 24
Peak memory 193948 kb
Host smart-4cf05e25-a3a9-45d2-927f-a8ecf82269cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998247483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.998247483
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2674545599
Short name T131
Test name
Test status
Simulation time 15535691 ps
CPU time 0.62 seconds
Started Feb 28 05:20:21 PM PST 24
Finished Feb 28 05:20:22 PM PST 24
Peak memory 194024 kb
Host smart-b54ad337-3fc8-4e85-a80e-28a9c344b0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674545599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2674545599
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2901264539
Short name T432
Test name
Test status
Simulation time 87324069 ps
CPU time 4.49 seconds
Started Feb 28 05:20:20 PM PST 24
Finished Feb 28 05:20:25 PM PST 24
Peak memory 196068 kb
Host smart-a9739663-2c26-4b59-9745-620506d5345a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901264539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2901264539
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2880561067
Short name T673
Test name
Test status
Simulation time 539865313 ps
CPU time 1.05 seconds
Started Feb 28 05:20:21 PM PST 24
Finished Feb 28 05:20:22 PM PST 24
Peak memory 196640 kb
Host smart-b90a54be-ffeb-44a5-aabd-cb8713162e49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880561067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2880561067
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2333824383
Short name T209
Test name
Test status
Simulation time 21132726 ps
CPU time 0.8 seconds
Started Feb 28 05:20:23 PM PST 24
Finished Feb 28 05:20:24 PM PST 24
Peak memory 196256 kb
Host smart-139fea88-f4cd-4fb5-8e17-3585b9d70f39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333824383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2333824383
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2475691469
Short name T210
Test name
Test status
Simulation time 77218688 ps
CPU time 1.74 seconds
Started Feb 28 05:20:20 PM PST 24
Finished Feb 28 05:20:22 PM PST 24
Peak memory 196752 kb
Host smart-dbb5d831-6e9a-446d-a550-09725382b7a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475691469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2475691469
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2260700578
Short name T627
Test name
Test status
Simulation time 77061905 ps
CPU time 1.47 seconds
Started Feb 28 05:20:21 PM PST 24
Finished Feb 28 05:20:23 PM PST 24
Peak memory 196192 kb
Host smart-000f9891-5979-4986-bdeb-6d7bce6cb74a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260700578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2260700578
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3246528667
Short name T468
Test name
Test status
Simulation time 56161416 ps
CPU time 0.96 seconds
Started Feb 28 05:20:19 PM PST 24
Finished Feb 28 05:20:20 PM PST 24
Peak memory 196040 kb
Host smart-2656f50a-28de-40bf-bf3b-5b40d30cccdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246528667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3246528667
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1387372255
Short name T226
Test name
Test status
Simulation time 21563513 ps
CPU time 0.72 seconds
Started Feb 28 05:20:19 PM PST 24
Finished Feb 28 05:20:19 PM PST 24
Peak memory 194260 kb
Host smart-1e8f8454-401f-46a3-aa58-d19365de8f76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387372255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1387372255
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3306349975
Short name T626
Test name
Test status
Simulation time 209984310 ps
CPU time 5.55 seconds
Started Feb 28 05:20:20 PM PST 24
Finished Feb 28 05:20:26 PM PST 24
Peak memory 198076 kb
Host smart-a07e3cbb-6f04-4bcd-9082-5bfece74b68c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306349975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3306349975
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3173700580
Short name T451
Test name
Test status
Simulation time 81688252 ps
CPU time 1.13 seconds
Started Feb 28 05:20:21 PM PST 24
Finished Feb 28 05:20:22 PM PST 24
Peak memory 196356 kb
Host smart-cbe77d53-94f1-417e-897e-b9083eb48ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173700580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3173700580
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.492964267
Short name T162
Test name
Test status
Simulation time 35966597 ps
CPU time 0.74 seconds
Started Feb 28 05:20:21 PM PST 24
Finished Feb 28 05:20:22 PM PST 24
Peak memory 195140 kb
Host smart-39fa62dd-35b1-4be7-8b7f-82ae0428822b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492964267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.492964267
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1859358129
Short name T508
Test name
Test status
Simulation time 16077164759 ps
CPU time 244.47 seconds
Started Feb 28 05:20:24 PM PST 24
Finished Feb 28 05:24:29 PM PST 24
Peak memory 198232 kb
Host smart-fa4b1d65-dbeb-43dc-964c-1692246e78d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859358129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1859358129
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.181528421
Short name T211
Test name
Test status
Simulation time 21344250 ps
CPU time 0.59 seconds
Started Feb 28 05:20:26 PM PST 24
Finished Feb 28 05:20:27 PM PST 24
Peak memory 193956 kb
Host smart-4d6957a1-f9cd-488d-ab34-ca8bc2202d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181528421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.181528421
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2150720821
Short name T177
Test name
Test status
Simulation time 31719802 ps
CPU time 0.8 seconds
Started Feb 28 05:20:25 PM PST 24
Finished Feb 28 05:20:26 PM PST 24
Peak memory 196052 kb
Host smart-779b9c49-f316-46c9-87c6-439fe4a48252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150720821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2150720821
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.293118199
Short name T576
Test name
Test status
Simulation time 213741692 ps
CPU time 5.73 seconds
Started Feb 28 05:20:24 PM PST 24
Finished Feb 28 05:20:30 PM PST 24
Peak memory 197064 kb
Host smart-7ece32ad-8b5f-4bf7-9a40-e7d3225c8d8e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293118199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.293118199
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.543911831
Short name T515
Test name
Test status
Simulation time 233848961 ps
CPU time 0.82 seconds
Started Feb 28 05:20:25 PM PST 24
Finished Feb 28 05:20:26 PM PST 24
Peak memory 196052 kb
Host smart-5b31a184-c8e3-4cd6-8dd6-f24360ef1532
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543911831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.543911831
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2351587935
Short name T129
Test name
Test status
Simulation time 89035290 ps
CPU time 0.75 seconds
Started Feb 28 05:20:24 PM PST 24
Finished Feb 28 05:20:25 PM PST 24
Peak memory 196316 kb
Host smart-b5b6ca4c-aa88-4ea5-bded-178dadb218b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351587935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2351587935
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1653458463
Short name T404
Test name
Test status
Simulation time 104265958 ps
CPU time 1.37 seconds
Started Feb 28 05:20:24 PM PST 24
Finished Feb 28 05:20:26 PM PST 24
Peak memory 196560 kb
Host smart-d5f499a4-54b2-4116-9375-f4cb2d9f44a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653458463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1653458463
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.904310535
Short name T612
Test name
Test status
Simulation time 659775752 ps
CPU time 1.18 seconds
Started Feb 28 05:20:24 PM PST 24
Finished Feb 28 05:20:26 PM PST 24
Peak memory 195888 kb
Host smart-ae9a6e4a-0048-4db8-8b3e-1258214c162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904310535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.904310535
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3446490094
Short name T50
Test name
Test status
Simulation time 24247123 ps
CPU time 1.01 seconds
Started Feb 28 05:20:26 PM PST 24
Finished Feb 28 05:20:27 PM PST 24
Peak memory 196104 kb
Host smart-1da4e564-807b-46b0-99e6-152d622d02c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446490094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3446490094
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3040763729
Short name T589
Test name
Test status
Simulation time 3045786127 ps
CPU time 4.65 seconds
Started Feb 28 05:20:23 PM PST 24
Finished Feb 28 05:20:28 PM PST 24
Peak memory 198140 kb
Host smart-ee46f795-1770-4076-a7ac-46903223e2b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040763729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3040763729
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.242714010
Short name T281
Test name
Test status
Simulation time 30665187 ps
CPU time 1.23 seconds
Started Feb 28 05:20:25 PM PST 24
Finished Feb 28 05:20:27 PM PST 24
Peak memory 195908 kb
Host smart-7d2103d7-0c43-4b54-aedc-509b54b42c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242714010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.242714010
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1047513949
Short name T216
Test name
Test status
Simulation time 33203774 ps
CPU time 0.78 seconds
Started Feb 28 05:20:26 PM PST 24
Finished Feb 28 05:20:27 PM PST 24
Peak memory 195868 kb
Host smart-4a9b1f98-ded2-468b-ae6c-0c1f71464708
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047513949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1047513949
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.3667962733
Short name T453
Test name
Test status
Simulation time 13664945841 ps
CPU time 145.34 seconds
Started Feb 28 05:20:24 PM PST 24
Finished Feb 28 05:22:50 PM PST 24
Peak memory 198204 kb
Host smart-dffb5dc5-153a-4ea0-9dc4-c69a23279b89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667962733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.3667962733
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1693597163
Short name T556
Test name
Test status
Simulation time 13125614 ps
CPU time 0.59 seconds
Started Feb 28 05:20:28 PM PST 24
Finished Feb 28 05:20:29 PM PST 24
Peak memory 194656 kb
Host smart-da1b43c5-d5df-4078-b9e1-49d13ba6134f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693597163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1693597163
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.895707285
Short name T542
Test name
Test status
Simulation time 135914675 ps
CPU time 0.91 seconds
Started Feb 28 05:20:29 PM PST 24
Finished Feb 28 05:20:30 PM PST 24
Peak memory 195496 kb
Host smart-ae65b8cc-9fd2-4a8a-b1fd-52223f9f751b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895707285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.895707285
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2935744249
Short name T236
Test name
Test status
Simulation time 528707172 ps
CPU time 8.11 seconds
Started Feb 28 05:20:29 PM PST 24
Finished Feb 28 05:20:38 PM PST 24
Peak memory 197224 kb
Host smart-67aec3ae-d53e-4e05-99b7-98b412ba30d2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935744249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2935744249
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1104536244
Short name T541
Test name
Test status
Simulation time 41339873 ps
CPU time 0.77 seconds
Started Feb 28 05:20:30 PM PST 24
Finished Feb 28 05:20:31 PM PST 24
Peak memory 194708 kb
Host smart-1200c075-f0ba-478f-a88e-31de62c1080c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104536244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1104536244
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3564192172
Short name T60
Test name
Test status
Simulation time 638501673 ps
CPU time 1.51 seconds
Started Feb 28 05:20:26 PM PST 24
Finished Feb 28 05:20:28 PM PST 24
Peak memory 196664 kb
Host smart-76b0d2d1-c119-4915-8b07-58e7d48ed429
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564192172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3564192172
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.585453957
Short name T299
Test name
Test status
Simulation time 35401977 ps
CPU time 1.46 seconds
Started Feb 28 05:20:28 PM PST 24
Finished Feb 28 05:20:29 PM PST 24
Peak memory 196728 kb
Host smart-a585b82f-f789-422a-a973-a76296c91a4c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585453957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.585453957
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1204468692
Short name T247
Test name
Test status
Simulation time 262944984 ps
CPU time 3.35 seconds
Started Feb 28 05:20:28 PM PST 24
Finished Feb 28 05:20:32 PM PST 24
Peak memory 197356 kb
Host smart-e0865b8a-9933-4108-bb79-12186c6aa592
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204468692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1204468692
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2832696049
Short name T670
Test name
Test status
Simulation time 55443312 ps
CPU time 0.64 seconds
Started Feb 28 05:20:30 PM PST 24
Finished Feb 28 05:20:31 PM PST 24
Peak memory 194336 kb
Host smart-1afb4aec-2223-45bc-87f9-309969483ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832696049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2832696049
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3318827387
Short name T439
Test name
Test status
Simulation time 104425335 ps
CPU time 0.84 seconds
Started Feb 28 05:20:33 PM PST 24
Finished Feb 28 05:20:34 PM PST 24
Peak memory 195548 kb
Host smart-61fa9b47-8987-4a24-8d73-ca11909d165c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318827387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3318827387
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.4271376917
Short name T196
Test name
Test status
Simulation time 144750840 ps
CPU time 3.42 seconds
Started Feb 28 05:20:29 PM PST 24
Finished Feb 28 05:20:32 PM PST 24
Peak memory 197992 kb
Host smart-83f62b17-ca89-4ca9-a4d9-fa14300db602
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271376917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.4271376917
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3605551351
Short name T367
Test name
Test status
Simulation time 129905064 ps
CPU time 1.02 seconds
Started Feb 28 05:20:26 PM PST 24
Finished Feb 28 05:20:27 PM PST 24
Peak memory 196636 kb
Host smart-6b09466f-9286-4e4a-a3af-09ee472f7b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605551351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3605551351
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1997420477
Short name T287
Test name
Test status
Simulation time 870343776 ps
CPU time 1.25 seconds
Started Feb 28 05:20:36 PM PST 24
Finished Feb 28 05:20:38 PM PST 24
Peak memory 196692 kb
Host smart-df80c01e-e113-46d4-9ca2-291028ecce39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997420477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1997420477
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.2005597762
Short name T494
Test name
Test status
Simulation time 6714911024 ps
CPU time 22.86 seconds
Started Feb 28 05:20:29 PM PST 24
Finished Feb 28 05:20:52 PM PST 24
Peak memory 198092 kb
Host smart-812af6a2-ced9-42cc-a07e-41f38b7d22a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005597762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.2005597762
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.4235546941
Short name T56
Test name
Test status
Simulation time 190940127575 ps
CPU time 1419.53 seconds
Started Feb 28 05:20:33 PM PST 24
Finished Feb 28 05:44:13 PM PST 24
Peak memory 198376 kb
Host smart-2fdd55e9-cbaa-4585-93b2-708562b565cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4235546941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.4235546941
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3144589899
Short name T538
Test name
Test status
Simulation time 36353921 ps
CPU time 0.58 seconds
Started Feb 28 05:20:31 PM PST 24
Finished Feb 28 05:20:32 PM PST 24
Peak memory 194672 kb
Host smart-2845f551-5969-482c-9a60-81d8b1a2d319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144589899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3144589899
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1017571952
Short name T596
Test name
Test status
Simulation time 53999250 ps
CPU time 0.61 seconds
Started Feb 28 05:20:28 PM PST 24
Finished Feb 28 05:20:28 PM PST 24
Peak memory 193920 kb
Host smart-4ab76052-9027-430b-b7bc-b4710342dc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017571952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1017571952
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1256567479
Short name T411
Test name
Test status
Simulation time 3748657422 ps
CPU time 24.53 seconds
Started Feb 28 05:20:31 PM PST 24
Finished Feb 28 05:20:56 PM PST 24
Peak memory 198232 kb
Host smart-ff5f482c-3888-4a5e-b505-9c632255b1fd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256567479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1256567479
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1496862825
Short name T20
Test name
Test status
Simulation time 214355514 ps
CPU time 1.12 seconds
Started Feb 28 05:20:32 PM PST 24
Finished Feb 28 05:20:33 PM PST 24
Peak memory 196432 kb
Host smart-ecb96b39-ec75-473b-8001-d063d4dde4b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496862825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1496862825
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3526740885
Short name T586
Test name
Test status
Simulation time 37876062 ps
CPU time 1.12 seconds
Started Feb 28 05:20:30 PM PST 24
Finished Feb 28 05:20:31 PM PST 24
Peak memory 196584 kb
Host smart-1904f052-4796-4fa0-8247-1290ad8b8d86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526740885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3526740885
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3475043256
Short name T399
Test name
Test status
Simulation time 1679061245 ps
CPU time 3.76 seconds
Started Feb 28 05:20:30 PM PST 24
Finished Feb 28 05:20:34 PM PST 24
Peak memory 198252 kb
Host smart-984a5dba-4986-4595-b5d0-f36ca972540c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475043256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3475043256
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2442808406
Short name T554
Test name
Test status
Simulation time 495685601 ps
CPU time 3.48 seconds
Started Feb 28 05:20:36 PM PST 24
Finished Feb 28 05:20:40 PM PST 24
Peak memory 198140 kb
Host smart-e297655b-a152-45ac-92a0-2d834d3f0f4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442808406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2442808406
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1020289455
Short name T571
Test name
Test status
Simulation time 56121522 ps
CPU time 1.5 seconds
Started Feb 28 05:20:31 PM PST 24
Finished Feb 28 05:20:32 PM PST 24
Peak memory 198160 kb
Host smart-3e0603ab-17be-465a-bde5-f316d892aea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020289455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1020289455
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.24769395
Short name T383
Test name
Test status
Simulation time 169797843 ps
CPU time 1.16 seconds
Started Feb 28 05:20:29 PM PST 24
Finished Feb 28 05:20:30 PM PST 24
Peak memory 196688 kb
Host smart-e3ed74a2-7f7c-4db7-861e-6e7ae8ca309e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24769395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup_
pulldown.24769395
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3979417087
Short name T301
Test name
Test status
Simulation time 221039365 ps
CPU time 3.96 seconds
Started Feb 28 05:20:30 PM PST 24
Finished Feb 28 05:20:34 PM PST 24
Peak memory 198080 kb
Host smart-ea0b3434-a5c3-4a37-92a5-b27f5fdb3488
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979417087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3979417087
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.565779439
Short name T64
Test name
Test status
Simulation time 881220423 ps
CPU time 1.45 seconds
Started Feb 28 05:20:29 PM PST 24
Finished Feb 28 05:20:31 PM PST 24
Peak memory 196700 kb
Host smart-1fb8a342-64b0-423b-a86b-d06349d8503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565779439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.565779439
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1465649203
Short name T705
Test name
Test status
Simulation time 34839335 ps
CPU time 1.14 seconds
Started Feb 28 05:20:29 PM PST 24
Finished Feb 28 05:20:31 PM PST 24
Peak memory 195692 kb
Host smart-e85ba1b8-7ce0-4a9c-a6d8-d3a3ac55799d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465649203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1465649203
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.696621355
Short name T172
Test name
Test status
Simulation time 5360382110 ps
CPU time 133.05 seconds
Started Feb 28 05:20:31 PM PST 24
Finished Feb 28 05:22:45 PM PST 24
Peak memory 198232 kb
Host smart-e95ec75d-d198-40a3-a6e5-772d32ca946a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696621355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.696621355
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.764827939
Short name T605
Test name
Test status
Simulation time 22181202 ps
CPU time 0.57 seconds
Started Feb 28 05:20:36 PM PST 24
Finished Feb 28 05:20:37 PM PST 24
Peak memory 193892 kb
Host smart-74157f60-6b35-4bae-9261-99e2ab2877af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764827939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.764827939
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.4000137182
Short name T557
Test name
Test status
Simulation time 18529654 ps
CPU time 0.63 seconds
Started Feb 28 05:20:35 PM PST 24
Finished Feb 28 05:20:36 PM PST 24
Peak memory 194012 kb
Host smart-5826d9f5-4fdc-4240-a489-276a033db485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000137182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4000137182
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3766204821
Short name T682
Test name
Test status
Simulation time 460694438 ps
CPU time 3.8 seconds
Started Feb 28 05:20:36 PM PST 24
Finished Feb 28 05:20:41 PM PST 24
Peak memory 196360 kb
Host smart-164d8769-3d78-4e96-9f4d-39ef919fae22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766204821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3766204821
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3073662301
Short name T348
Test name
Test status
Simulation time 54775852 ps
CPU time 0.83 seconds
Started Feb 28 05:20:38 PM PST 24
Finished Feb 28 05:20:39 PM PST 24
Peak memory 195912 kb
Host smart-bdd67e59-c0d3-4278-9d07-ae450faa3f0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073662301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3073662301
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1549737859
Short name T642
Test name
Test status
Simulation time 31814385 ps
CPU time 0.85 seconds
Started Feb 28 05:20:38 PM PST 24
Finished Feb 28 05:20:39 PM PST 24
Peak memory 195600 kb
Host smart-a5fc6fdc-8e76-4daf-ad97-84cdd200a2f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549737859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1549737859
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2314990572
Short name T526
Test name
Test status
Simulation time 158009591 ps
CPU time 3.59 seconds
Started Feb 28 05:20:37 PM PST 24
Finished Feb 28 05:20:41 PM PST 24
Peak memory 198168 kb
Host smart-74b97532-8bb5-4a75-8fb9-bcde4af1c137
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314990572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2314990572
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.439022220
Short name T259
Test name
Test status
Simulation time 58939679 ps
CPU time 1.38 seconds
Started Feb 28 05:20:37 PM PST 24
Finished Feb 28 05:20:38 PM PST 24
Peak memory 196944 kb
Host smart-ce9e9f1f-e911-479f-88da-742c02f580ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439022220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
439022220
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.971811121
Short name T120
Test name
Test status
Simulation time 63992920 ps
CPU time 0.88 seconds
Started Feb 28 05:20:30 PM PST 24
Finished Feb 28 05:20:31 PM PST 24
Peak memory 197188 kb
Host smart-031bc49e-3ac2-48d6-988e-8de4a02478b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971811121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.971811121
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.157368212
Short name T447
Test name
Test status
Simulation time 33630279 ps
CPU time 0.94 seconds
Started Feb 28 05:20:36 PM PST 24
Finished Feb 28 05:20:37 PM PST 24
Peak memory 196228 kb
Host smart-5f2850d5-6ecf-4b48-817a-c442aec9362f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157368212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.157368212
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3031444318
Short name T161
Test name
Test status
Simulation time 220152440 ps
CPU time 2.98 seconds
Started Feb 28 05:20:36 PM PST 24
Finished Feb 28 05:20:39 PM PST 24
Peak memory 198004 kb
Host smart-00ad2380-cd01-4ccf-a9cf-05e9bc08089b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031444318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3031444318
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.4279322192
Short name T385
Test name
Test status
Simulation time 229509497 ps
CPU time 0.93 seconds
Started Feb 28 05:20:31 PM PST 24
Finished Feb 28 05:20:32 PM PST 24
Peak memory 196484 kb
Host smart-f03c0beb-6e93-4b38-a730-2237b98f9a35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279322192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.4279322192
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3584755936
Short name T473
Test name
Test status
Simulation time 73004599498 ps
CPU time 189.47 seconds
Started Feb 28 05:20:37 PM PST 24
Finished Feb 28 05:23:47 PM PST 24
Peak memory 198252 kb
Host smart-6f661e94-188f-403a-9ad0-5a499e081a02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584755936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3584755936
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.180899246
Short name T36
Test name
Test status
Simulation time 12459590 ps
CPU time 0.55 seconds
Started Feb 28 05:20:44 PM PST 24
Finished Feb 28 05:20:44 PM PST 24
Peak memory 193932 kb
Host smart-c8d0b3ee-f091-47a8-b254-ce5eccc9fea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180899246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.180899246
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2228528879
Short name T414
Test name
Test status
Simulation time 20729863 ps
CPU time 0.9 seconds
Started Feb 28 05:20:42 PM PST 24
Finished Feb 28 05:20:43 PM PST 24
Peak memory 196084 kb
Host smart-94ca74a0-6ab3-4f0a-beab-99a8df3cfedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228528879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2228528879
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.4201468241
Short name T510
Test name
Test status
Simulation time 1259493342 ps
CPU time 17.08 seconds
Started Feb 28 05:20:42 PM PST 24
Finished Feb 28 05:20:59 PM PST 24
Peak memory 196972 kb
Host smart-d6178820-02e3-4569-82c1-1dd206de2c43
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201468241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.4201468241
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.4036690868
Short name T248
Test name
Test status
Simulation time 318503093 ps
CPU time 1.16 seconds
Started Feb 28 05:20:39 PM PST 24
Finished Feb 28 05:20:41 PM PST 24
Peak memory 196688 kb
Host smart-5a8efc83-e580-4fff-bcbd-5f4c571de00a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036690868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.4036690868
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3142017416
Short name T257
Test name
Test status
Simulation time 51380833 ps
CPU time 0.96 seconds
Started Feb 28 05:20:41 PM PST 24
Finished Feb 28 05:20:42 PM PST 24
Peak memory 196696 kb
Host smart-c9c46e41-9b23-4502-82ee-4bcd46243930
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142017416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3142017416
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.975860881
Short name T341
Test name
Test status
Simulation time 143249393 ps
CPU time 3.34 seconds
Started Feb 28 05:20:41 PM PST 24
Finished Feb 28 05:20:45 PM PST 24
Peak memory 196624 kb
Host smart-8d6b0cf7-83de-4df0-9b49-7461e721bcaf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975860881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.975860881
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2739562107
Short name T193
Test name
Test status
Simulation time 138897425 ps
CPU time 2.94 seconds
Started Feb 28 05:20:42 PM PST 24
Finished Feb 28 05:20:46 PM PST 24
Peak memory 196596 kb
Host smart-65e224d8-968d-4013-90b1-128174991022
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739562107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2739562107
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1009731206
Short name T379
Test name
Test status
Simulation time 102682617 ps
CPU time 0.83 seconds
Started Feb 28 05:20:40 PM PST 24
Finished Feb 28 05:20:41 PM PST 24
Peak memory 196584 kb
Host smart-a8484c6d-cd9d-44da-9ead-3bcd78289132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009731206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1009731206
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2443126395
Short name T111
Test name
Test status
Simulation time 74128985 ps
CPU time 0.67 seconds
Started Feb 28 05:20:43 PM PST 24
Finished Feb 28 05:20:44 PM PST 24
Peak memory 195116 kb
Host smart-2771d005-80a8-45fb-885b-8d74ebdd8f96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443126395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2443126395
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.471001049
Short name T679
Test name
Test status
Simulation time 502698898 ps
CPU time 2.75 seconds
Started Feb 28 05:20:44 PM PST 24
Finished Feb 28 05:20:47 PM PST 24
Peak memory 198052 kb
Host smart-b4cbf15f-a57e-4798-b0c1-6247c79cf242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471001049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.471001049
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2954734923
Short name T435
Test name
Test status
Simulation time 53999792 ps
CPU time 0.95 seconds
Started Feb 28 05:20:37 PM PST 24
Finished Feb 28 05:20:38 PM PST 24
Peak memory 195512 kb
Host smart-fa67ee4a-b5fa-41c0-ae17-9aa009948945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954734923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2954734923
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2245439201
Short name T630
Test name
Test status
Simulation time 53362590 ps
CPU time 1.1 seconds
Started Feb 28 05:20:41 PM PST 24
Finished Feb 28 05:20:42 PM PST 24
Peak memory 195840 kb
Host smart-19c83e47-5b3b-494c-a01d-4e6c0cc48bae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245439201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2245439201
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.530894241
Short name T461
Test name
Test status
Simulation time 7544719012 ps
CPU time 47.73 seconds
Started Feb 28 05:20:40 PM PST 24
Finished Feb 28 05:21:28 PM PST 24
Peak memory 198204 kb
Host smart-a34bf67d-b6de-4784-adc2-97ebdca944fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530894241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.530894241
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3036045362
Short name T550
Test name
Test status
Simulation time 41986224 ps
CPU time 0.61 seconds
Started Feb 28 05:20:44 PM PST 24
Finished Feb 28 05:20:45 PM PST 24
Peak memory 193964 kb
Host smart-a1c57cea-1057-4043-be24-b37ce77bc6a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036045362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3036045362
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2015288111
Short name T466
Test name
Test status
Simulation time 164986557 ps
CPU time 0.85 seconds
Started Feb 28 05:20:46 PM PST 24
Finished Feb 28 05:20:47 PM PST 24
Peak memory 195460 kb
Host smart-31c537bf-c1f5-4a77-863e-270915015feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015288111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2015288111
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3218765124
Short name T157
Test name
Test status
Simulation time 1177670585 ps
CPU time 21.35 seconds
Started Feb 28 05:20:45 PM PST 24
Finished Feb 28 05:21:06 PM PST 24
Peak memory 197116 kb
Host smart-7cd2d09f-ea25-43cd-8da2-ba72ba03dce2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218765124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3218765124
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1872094584
Short name T339
Test name
Test status
Simulation time 232414403 ps
CPU time 1.12 seconds
Started Feb 28 05:20:45 PM PST 24
Finished Feb 28 05:20:46 PM PST 24
Peak memory 196732 kb
Host smart-ffe60906-f9d6-47c1-b2fd-5492f6535e76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872094584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1872094584
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3418832469
Short name T144
Test name
Test status
Simulation time 38510107 ps
CPU time 1.15 seconds
Started Feb 28 05:20:45 PM PST 24
Finished Feb 28 05:20:46 PM PST 24
Peak memory 196772 kb
Host smart-0f7761dd-af25-4ca1-9eb1-8b691e062626
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418832469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3418832469
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3558232652
Short name T534
Test name
Test status
Simulation time 24865543 ps
CPU time 1.06 seconds
Started Feb 28 05:20:45 PM PST 24
Finished Feb 28 05:20:47 PM PST 24
Peak memory 196780 kb
Host smart-165de41b-d9ac-4b98-aac6-a099f48d6e54
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558232652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3558232652
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2277054020
Short name T167
Test name
Test status
Simulation time 52248325 ps
CPU time 1.61 seconds
Started Feb 28 05:20:46 PM PST 24
Finished Feb 28 05:20:48 PM PST 24
Peak memory 196224 kb
Host smart-9bece2b5-34ce-4b98-9984-2ce90a894a82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277054020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2277054020
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1138275033
Short name T577
Test name
Test status
Simulation time 26415224 ps
CPU time 1.07 seconds
Started Feb 28 05:20:42 PM PST 24
Finished Feb 28 05:20:43 PM PST 24
Peak memory 195944 kb
Host smart-a9c22788-f7ce-4097-af90-0eb39bb4e371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138275033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1138275033
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2853263784
Short name T659
Test name
Test status
Simulation time 211446860 ps
CPU time 1.25 seconds
Started Feb 28 05:20:44 PM PST 24
Finished Feb 28 05:20:45 PM PST 24
Peak memory 197140 kb
Host smart-57363602-3fe5-49cb-a9db-1e18a8ce5423
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853263784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2853263784
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1676866365
Short name T309
Test name
Test status
Simulation time 480199171 ps
CPU time 2.46 seconds
Started Feb 28 05:20:47 PM PST 24
Finished Feb 28 05:20:50 PM PST 24
Peak memory 198080 kb
Host smart-b7af5905-69f3-428c-be2c-fde3568cfb25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676866365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1676866365
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3727484816
Short name T153
Test name
Test status
Simulation time 74260193 ps
CPU time 1.25 seconds
Started Feb 28 05:20:43 PM PST 24
Finished Feb 28 05:20:44 PM PST 24
Peak memory 195612 kb
Host smart-551e5059-5a61-498d-8061-2c422a4bb04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727484816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3727484816
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3298369222
Short name T169
Test name
Test status
Simulation time 119139998 ps
CPU time 1.11 seconds
Started Feb 28 05:20:40 PM PST 24
Finished Feb 28 05:20:42 PM PST 24
Peak memory 196464 kb
Host smart-7bf35db5-dd5e-4581-a584-8632f6eeb472
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298369222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3298369222
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.71540763
Short name T657
Test name
Test status
Simulation time 6103557426 ps
CPU time 143.67 seconds
Started Feb 28 05:20:47 PM PST 24
Finished Feb 28 05:23:11 PM PST 24
Peak memory 198268 kb
Host smart-698a42fe-e2bc-4c3b-bbae-994f90f94165
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71540763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gp
io_stress_all.71540763
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3584216988
Short name T646
Test name
Test status
Simulation time 18823322 ps
CPU time 0.55 seconds
Started Feb 28 05:20:55 PM PST 24
Finished Feb 28 05:20:56 PM PST 24
Peak memory 192720 kb
Host smart-05116876-fe31-49e2-ade4-cd52da694981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584216988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3584216988
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.4136180084
Short name T291
Test name
Test status
Simulation time 142528587 ps
CPU time 0.86 seconds
Started Feb 28 05:20:48 PM PST 24
Finished Feb 28 05:20:49 PM PST 24
Peak memory 197108 kb
Host smart-1da8dce5-09a1-4288-8aa3-d5fffbc193e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136180084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.4136180084
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.4168936083
Short name T128
Test name
Test status
Simulation time 2033611304 ps
CPU time 14.95 seconds
Started Feb 28 05:20:48 PM PST 24
Finished Feb 28 05:21:03 PM PST 24
Peak memory 197156 kb
Host smart-bd728120-f3fc-4e01-9be0-66191089dd56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168936083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.4168936083
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.798464970
Short name T418
Test name
Test status
Simulation time 351855418 ps
CPU time 1.03 seconds
Started Feb 28 05:20:49 PM PST 24
Finished Feb 28 05:20:51 PM PST 24
Peak memory 197220 kb
Host smart-ee19dda6-7b35-4ce8-a609-b54d453df5d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798464970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.798464970
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2902085266
Short name T696
Test name
Test status
Simulation time 48536823 ps
CPU time 1.4 seconds
Started Feb 28 05:20:49 PM PST 24
Finished Feb 28 05:20:50 PM PST 24
Peak memory 197260 kb
Host smart-914250bb-69e7-4a26-82aa-015fb1f02aab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902085266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2902085266
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.539534381
Short name T496
Test name
Test status
Simulation time 38175721 ps
CPU time 0.97 seconds
Started Feb 28 05:20:48 PM PST 24
Finished Feb 28 05:20:49 PM PST 24
Peak memory 195932 kb
Host smart-81b4e32a-51c5-48fb-891d-c5500a4b6a0e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539534381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.539534381
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2955265699
Short name T215
Test name
Test status
Simulation time 114675410 ps
CPU time 2.64 seconds
Started Feb 28 05:20:48 PM PST 24
Finished Feb 28 05:20:51 PM PST 24
Peak memory 198128 kb
Host smart-6f9c20c0-2c16-4b00-bf62-4b6ac1008b8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955265699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2955265699
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3730872236
Short name T315
Test name
Test status
Simulation time 17648940 ps
CPU time 0.76 seconds
Started Feb 28 05:20:48 PM PST 24
Finished Feb 28 05:20:49 PM PST 24
Peak memory 195392 kb
Host smart-976fd5ff-1948-4a8b-ad9d-7b3aa8de8cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730872236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3730872236
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.160757492
Short name T618
Test name
Test status
Simulation time 38567419 ps
CPU time 0.93 seconds
Started Feb 28 05:20:45 PM PST 24
Finished Feb 28 05:20:46 PM PST 24
Peak memory 195988 kb
Host smart-7856faca-a21d-455c-a5ad-d439580bb7b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160757492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.160757492
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.829575807
Short name T166
Test name
Test status
Simulation time 41774552 ps
CPU time 1.77 seconds
Started Feb 28 05:20:50 PM PST 24
Finished Feb 28 05:20:52 PM PST 24
Peak memory 198080 kb
Host smart-02cfebbc-f370-4aa6-b76b-9bb3dcd5e63c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829575807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.829575807
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1216528403
Short name T220
Test name
Test status
Simulation time 52332713 ps
CPU time 1.12 seconds
Started Feb 28 05:20:44 PM PST 24
Finished Feb 28 05:20:45 PM PST 24
Peak memory 196420 kb
Host smart-f9e9c09b-4df8-465f-80c7-b41c370eeb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216528403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1216528403
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1470407439
Short name T663
Test name
Test status
Simulation time 235157999 ps
CPU time 1.34 seconds
Started Feb 28 05:20:48 PM PST 24
Finished Feb 28 05:20:49 PM PST 24
Peak memory 198060 kb
Host smart-b7ca4013-aa29-4e17-8b18-a6c02732f347
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470407439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1470407439
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3666950910
Short name T360
Test name
Test status
Simulation time 85629591969 ps
CPU time 150.68 seconds
Started Feb 28 05:20:50 PM PST 24
Finished Feb 28 05:23:21 PM PST 24
Peak memory 198264 kb
Host smart-70105d9e-8648-40cc-9be1-3e9295c64b95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666950910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3666950910
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2063935393
Short name T710
Test name
Test status
Simulation time 98096292 ps
CPU time 0.56 seconds
Started Feb 28 05:19:47 PM PST 24
Finished Feb 28 05:19:48 PM PST 24
Peak memory 193920 kb
Host smart-d3b84265-841b-4697-9aff-057d74468ac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063935393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2063935393
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2431608838
Short name T184
Test name
Test status
Simulation time 79611000 ps
CPU time 0.87 seconds
Started Feb 28 05:19:43 PM PST 24
Finished Feb 28 05:19:44 PM PST 24
Peak memory 195428 kb
Host smart-c3d9af00-446c-44fb-88e2-79a713bb6220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431608838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2431608838
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.479945464
Short name T214
Test name
Test status
Simulation time 80575219 ps
CPU time 4.08 seconds
Started Feb 28 05:19:50 PM PST 24
Finished Feb 28 05:19:54 PM PST 24
Peak memory 196124 kb
Host smart-16a61b53-52c0-4fd5-947d-4a69f2c9a9c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479945464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.479945464
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2381615342
Short name T116
Test name
Test status
Simulation time 154089488 ps
CPU time 0.89 seconds
Started Feb 28 05:19:49 PM PST 24
Finished Feb 28 05:19:51 PM PST 24
Peak memory 197180 kb
Host smart-4c400cd3-7895-44e7-aca3-35c87034e5e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381615342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2381615342
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.670986467
Short name T102
Test name
Test status
Simulation time 249319246 ps
CPU time 1.15 seconds
Started Feb 28 05:19:49 PM PST 24
Finished Feb 28 05:19:51 PM PST 24
Peak memory 196264 kb
Host smart-ebfe7866-6c10-4f93-93c9-c92121922ca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670986467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.670986467
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2514018715
Short name T602
Test name
Test status
Simulation time 74851596 ps
CPU time 2.69 seconds
Started Feb 28 05:19:49 PM PST 24
Finished Feb 28 05:19:53 PM PST 24
Peak memory 196436 kb
Host smart-b2eee8f6-6c7a-43b9-9417-60eecbbaec81
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514018715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2514018715
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3873266243
Short name T485
Test name
Test status
Simulation time 145086921 ps
CPU time 1.31 seconds
Started Feb 28 05:19:47 PM PST 24
Finished Feb 28 05:19:49 PM PST 24
Peak memory 196884 kb
Host smart-05fb98c6-08d6-4235-8393-d3d8cf64c000
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873266243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3873266243
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1704940521
Short name T698
Test name
Test status
Simulation time 72801045 ps
CPU time 1 seconds
Started Feb 28 05:19:49 PM PST 24
Finished Feb 28 05:19:51 PM PST 24
Peak memory 196092 kb
Host smart-c7b4226a-6f3c-4e57-983a-dcf7dcfff8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704940521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1704940521
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.933694395
Short name T302
Test name
Test status
Simulation time 163195695 ps
CPU time 1.14 seconds
Started Feb 28 05:19:43 PM PST 24
Finished Feb 28 05:19:44 PM PST 24
Peak memory 196808 kb
Host smart-839f45b3-fd6c-4a9c-a2c5-6622c23c1369
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933694395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.933694395
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1172962041
Short name T62
Test name
Test status
Simulation time 204340469 ps
CPU time 5.12 seconds
Started Feb 28 05:19:50 PM PST 24
Finished Feb 28 05:19:56 PM PST 24
Peak memory 198096 kb
Host smart-06c72509-6c1a-4f18-87a2-58fe586c9d10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172962041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1172962041
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1208127635
Short name T43
Test name
Test status
Simulation time 134071773 ps
CPU time 0.78 seconds
Started Feb 28 05:19:50 PM PST 24
Finished Feb 28 05:19:51 PM PST 24
Peak memory 213812 kb
Host smart-d0de4fab-94f5-4701-b0ba-8c5496ac52d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208127635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1208127635
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3299662590
Short name T233
Test name
Test status
Simulation time 157097670 ps
CPU time 0.92 seconds
Started Feb 28 05:19:51 PM PST 24
Finished Feb 28 05:19:52 PM PST 24
Peak memory 195452 kb
Host smart-b0a31534-e065-4e6a-815b-1f5943be0166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299662590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3299662590
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.548250801
Short name T423
Test name
Test status
Simulation time 45868499 ps
CPU time 1.27 seconds
Started Feb 28 05:19:50 PM PST 24
Finished Feb 28 05:19:52 PM PST 24
Peak memory 196672 kb
Host smart-40420378-d7c8-46c8-8730-75d93ac93e08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548250801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.548250801
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1064680916
Short name T518
Test name
Test status
Simulation time 1578870742 ps
CPU time 52.2 seconds
Started Feb 28 05:19:48 PM PST 24
Finished Feb 28 05:20:40 PM PST 24
Peak memory 198172 kb
Host smart-307a89ec-7b91-40ea-8711-8253ecaecf19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064680916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1064680916
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.4032409945
Short name T260
Test name
Test status
Simulation time 46790090 ps
CPU time 0.57 seconds
Started Feb 28 05:20:56 PM PST 24
Finished Feb 28 05:20:58 PM PST 24
Peak memory 194112 kb
Host smart-6b9aa86c-95d5-4c67-9a81-d0400179d958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032409945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.4032409945
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3371074992
Short name T637
Test name
Test status
Simulation time 16203626 ps
CPU time 0.65 seconds
Started Feb 28 05:20:57 PM PST 24
Finished Feb 28 05:20:58 PM PST 24
Peak memory 194776 kb
Host smart-d65b0480-f4be-4a42-96c8-513bc6723980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371074992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3371074992
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3390237705
Short name T174
Test name
Test status
Simulation time 175097277 ps
CPU time 4.39 seconds
Started Feb 28 05:20:52 PM PST 24
Finished Feb 28 05:20:58 PM PST 24
Peak memory 195956 kb
Host smart-a6f862c6-a87c-426a-8bee-e7622cc6cca9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390237705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3390237705
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1025849111
Short name T314
Test name
Test status
Simulation time 73264079 ps
CPU time 0.93 seconds
Started Feb 28 05:20:56 PM PST 24
Finished Feb 28 05:20:58 PM PST 24
Peak memory 196668 kb
Host smart-c4635f67-053c-4caf-af1b-0e76f62ca774
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025849111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1025849111
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1105076850
Short name T325
Test name
Test status
Simulation time 80833616 ps
CPU time 1.34 seconds
Started Feb 28 05:20:56 PM PST 24
Finished Feb 28 05:20:59 PM PST 24
Peak memory 195940 kb
Host smart-f0b5a466-0723-41bb-805b-2bdfa07f3c40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105076850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1105076850
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3248446162
Short name T208
Test name
Test status
Simulation time 61635957 ps
CPU time 2.51 seconds
Started Feb 28 05:20:54 PM PST 24
Finished Feb 28 05:20:58 PM PST 24
Peak memory 198180 kb
Host smart-1273b66d-22d7-4b56-93f9-a5f08b562a8e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248446162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3248446162
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2208497609
Short name T150
Test name
Test status
Simulation time 89948119 ps
CPU time 1.02 seconds
Started Feb 28 05:20:51 PM PST 24
Finished Feb 28 05:20:52 PM PST 24
Peak memory 195720 kb
Host smart-f1539123-338a-4025-af8c-91616662e2aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208497609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2208497609
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2528528390
Short name T136
Test name
Test status
Simulation time 797761484 ps
CPU time 1.14 seconds
Started Feb 28 05:20:55 PM PST 24
Finished Feb 28 05:20:58 PM PST 24
Peak memory 196832 kb
Host smart-a862f597-3de3-4048-b4f9-db304c66cc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528528390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2528528390
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2189241562
Short name T235
Test name
Test status
Simulation time 116818000 ps
CPU time 0.83 seconds
Started Feb 28 05:20:53 PM PST 24
Finished Feb 28 05:20:55 PM PST 24
Peak memory 197360 kb
Host smart-3cea7a76-d7ae-479a-a4f8-8bf36cdca4c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189241562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2189241562
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3318717892
Short name T582
Test name
Test status
Simulation time 472281305 ps
CPU time 4.28 seconds
Started Feb 28 05:20:53 PM PST 24
Finished Feb 28 05:20:57 PM PST 24
Peak memory 198064 kb
Host smart-d1b9c191-94c4-4f98-b8c2-09cc4feebdb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318717892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3318717892
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3111422953
Short name T200
Test name
Test status
Simulation time 216726901 ps
CPU time 1.11 seconds
Started Feb 28 05:20:51 PM PST 24
Finished Feb 28 05:20:52 PM PST 24
Peak memory 196336 kb
Host smart-8b9ed27b-1862-4f90-8972-3d24914f4bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111422953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3111422953
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1010012589
Short name T382
Test name
Test status
Simulation time 64728031 ps
CPU time 0.88 seconds
Started Feb 28 05:20:54 PM PST 24
Finished Feb 28 05:20:56 PM PST 24
Peak memory 197052 kb
Host smart-8eb7c82b-96a6-4254-8083-06f6bdcf552e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010012589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1010012589
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1667141603
Short name T614
Test name
Test status
Simulation time 65011673476 ps
CPU time 78.81 seconds
Started Feb 28 05:20:53 PM PST 24
Finished Feb 28 05:22:12 PM PST 24
Peak memory 198216 kb
Host smart-291e42e0-ed01-4565-8102-0f35b599d9ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667141603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1667141603
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.494773632
Short name T653
Test name
Test status
Simulation time 14570035 ps
CPU time 0.58 seconds
Started Feb 28 05:20:56 PM PST 24
Finished Feb 28 05:20:58 PM PST 24
Peak memory 194580 kb
Host smart-7055a1e4-7f41-40ae-be9d-f9d0bdf56988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494773632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.494773632
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.786152726
Short name T127
Test name
Test status
Simulation time 381584953 ps
CPU time 0.96 seconds
Started Feb 28 05:20:58 PM PST 24
Finished Feb 28 05:20:59 PM PST 24
Peak memory 197172 kb
Host smart-a45f3603-c841-4834-9bbd-e2e36ec53db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786152726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.786152726
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1144293551
Short name T500
Test name
Test status
Simulation time 247455653 ps
CPU time 12.31 seconds
Started Feb 28 05:20:55 PM PST 24
Finished Feb 28 05:21:08 PM PST 24
Peak memory 197088 kb
Host smart-f1e034f3-6820-4cd7-8006-f8bcc9e114b8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144293551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1144293551
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.433486524
Short name T16
Test name
Test status
Simulation time 206222221 ps
CPU time 0.86 seconds
Started Feb 28 05:20:56 PM PST 24
Finished Feb 28 05:20:59 PM PST 24
Peak memory 195988 kb
Host smart-0accad07-3879-4880-9cc6-2be28af3def4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433486524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.433486524
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2165956501
Short name T331
Test name
Test status
Simulation time 190975574 ps
CPU time 1.6 seconds
Started Feb 28 05:20:58 PM PST 24
Finished Feb 28 05:21:00 PM PST 24
Peak memory 198080 kb
Host smart-29bfe891-04c7-49f7-b666-7e1a5eea0bf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165956501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2165956501
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.4018081406
Short name T125
Test name
Test status
Simulation time 43177887 ps
CPU time 1.17 seconds
Started Feb 28 05:20:58 PM PST 24
Finished Feb 28 05:21:00 PM PST 24
Peak memory 196312 kb
Host smart-36376e41-85fa-4fa1-b5be-4d544abe760c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018081406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.4018081406
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3232959204
Short name T105
Test name
Test status
Simulation time 83128244 ps
CPU time 2.5 seconds
Started Feb 28 05:20:56 PM PST 24
Finished Feb 28 05:21:00 PM PST 24
Peak memory 195956 kb
Host smart-f19abedc-06bd-435a-8c8a-a5e705fc6668
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232959204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3232959204
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1863731365
Short name T440
Test name
Test status
Simulation time 20488825 ps
CPU time 0.79 seconds
Started Feb 28 05:20:56 PM PST 24
Finished Feb 28 05:20:58 PM PST 24
Peak memory 195508 kb
Host smart-0b06497b-8850-4b11-b37f-76e839684718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863731365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1863731365
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3476567056
Short name T245
Test name
Test status
Simulation time 550490890 ps
CPU time 1.18 seconds
Started Feb 28 05:21:00 PM PST 24
Finished Feb 28 05:21:02 PM PST 24
Peak memory 195916 kb
Host smart-bb938cf2-50d9-4bec-a3cb-bc8d1c8cd4e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476567056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3476567056
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1056855317
Short name T303
Test name
Test status
Simulation time 159352525 ps
CPU time 2.42 seconds
Started Feb 28 05:20:55 PM PST 24
Finished Feb 28 05:20:59 PM PST 24
Peak memory 198088 kb
Host smart-f4fcd68d-203c-4490-8dff-c1be23e7e829
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056855317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1056855317
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.4022139023
Short name T188
Test name
Test status
Simulation time 161967826 ps
CPU time 1.52 seconds
Started Feb 28 05:20:56 PM PST 24
Finished Feb 28 05:20:58 PM PST 24
Peak memory 196276 kb
Host smart-14a5b025-7fe7-4dae-9450-ff8452595bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022139023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.4022139023
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2694852433
Short name T109
Test name
Test status
Simulation time 218027364 ps
CPU time 1.2 seconds
Started Feb 28 05:20:55 PM PST 24
Finished Feb 28 05:20:58 PM PST 24
Peak memory 195888 kb
Host smart-ffeca6d6-f6c7-4485-8f2c-16f5e5aa11dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694852433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2694852433
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1800747182
Short name T522
Test name
Test status
Simulation time 13012798017 ps
CPU time 180.29 seconds
Started Feb 28 05:20:55 PM PST 24
Finished Feb 28 05:23:57 PM PST 24
Peak memory 198232 kb
Host smart-30365fd2-5b64-42a7-826e-d12d85e29ff0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800747182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1800747182
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2382861546
Short name T147
Test name
Test status
Simulation time 17484123 ps
CPU time 0.63 seconds
Started Feb 28 05:21:04 PM PST 24
Finished Feb 28 05:21:05 PM PST 24
Peak memory 194120 kb
Host smart-a28c1d9a-3a17-4405-9eb8-5c3e5d32df8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382861546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2382861546
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3701000334
Short name T415
Test name
Test status
Simulation time 27967104 ps
CPU time 0.9 seconds
Started Feb 28 05:20:59 PM PST 24
Finished Feb 28 05:21:00 PM PST 24
Peak memory 196520 kb
Host smart-621cd7e9-ac6d-45cc-9745-92a24354f956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701000334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3701000334
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.939935967
Short name T675
Test name
Test status
Simulation time 218228269 ps
CPU time 5.95 seconds
Started Feb 28 05:20:58 PM PST 24
Finished Feb 28 05:21:05 PM PST 24
Peak memory 197104 kb
Host smart-19f64612-b5f7-4807-a0ef-692f273e4213
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939935967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.939935967
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3320740306
Short name T701
Test name
Test status
Simulation time 304626755 ps
CPU time 0.66 seconds
Started Feb 28 05:20:59 PM PST 24
Finished Feb 28 05:21:00 PM PST 24
Peak memory 195048 kb
Host smart-a98bd1ac-5dbf-46dd-9d17-7518713d4d86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320740306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3320740306
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3535546826
Short name T665
Test name
Test status
Simulation time 565183266 ps
CPU time 1.19 seconds
Started Feb 28 05:21:00 PM PST 24
Finished Feb 28 05:21:02 PM PST 24
Peak memory 196108 kb
Host smart-1345c298-b54f-4d94-bd9f-5738b640db53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535546826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3535546826
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3098168817
Short name T386
Test name
Test status
Simulation time 35211400 ps
CPU time 1.45 seconds
Started Feb 28 05:20:57 PM PST 24
Finished Feb 28 05:21:00 PM PST 24
Peak memory 198168 kb
Host smart-0e511710-cc62-457d-9667-d22cbc9df8e9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098168817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3098168817
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2685236925
Short name T492
Test name
Test status
Simulation time 72598808 ps
CPU time 2.64 seconds
Started Feb 28 05:20:59 PM PST 24
Finished Feb 28 05:21:02 PM PST 24
Peak memory 198120 kb
Host smart-fc4120b2-ba9f-4c22-a2a4-d7f7888aa2a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685236925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2685236925
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2031743664
Short name T394
Test name
Test status
Simulation time 54507872 ps
CPU time 0.85 seconds
Started Feb 28 05:21:00 PM PST 24
Finished Feb 28 05:21:01 PM PST 24
Peak memory 196284 kb
Host smart-240f6d8f-c142-4293-97a9-8e17f2b2279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031743664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2031743664
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.606962304
Short name T480
Test name
Test status
Simulation time 130953533 ps
CPU time 1.33 seconds
Started Feb 28 05:21:03 PM PST 24
Finished Feb 28 05:21:04 PM PST 24
Peak memory 198088 kb
Host smart-6de8c4f0-e613-47a4-aa6b-9a671936ef8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606962304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.606962304
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1560264347
Short name T156
Test name
Test status
Simulation time 67283605 ps
CPU time 1.59 seconds
Started Feb 28 05:21:07 PM PST 24
Finished Feb 28 05:21:09 PM PST 24
Peak memory 198108 kb
Host smart-0b5bd22a-ca24-47e8-a85d-095d1e7331b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560264347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1560264347
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.457980197
Short name T498
Test name
Test status
Simulation time 83167208 ps
CPU time 1.82 seconds
Started Feb 28 05:21:01 PM PST 24
Finished Feb 28 05:21:03 PM PST 24
Peak memory 196620 kb
Host smart-ba70c6b2-44d7-48e0-be25-7ae5ae866f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457980197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.457980197
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.145856299
Short name T359
Test name
Test status
Simulation time 219539239 ps
CPU time 1.37 seconds
Started Feb 28 05:21:01 PM PST 24
Finished Feb 28 05:21:03 PM PST 24
Peak memory 195820 kb
Host smart-57054bba-9dd1-4ddc-8a11-8048ebea428d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145856299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.145856299
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2279349313
Short name T308
Test name
Test status
Simulation time 49096762831 ps
CPU time 196.81 seconds
Started Feb 28 05:20:59 PM PST 24
Finished Feb 28 05:24:17 PM PST 24
Peak memory 198244 kb
Host smart-e438f3c7-92bd-4d82-80e2-027bfc493aad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279349313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2279349313
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.579371644
Short name T201
Test name
Test status
Simulation time 61500311 ps
CPU time 0.64 seconds
Started Feb 28 05:21:07 PM PST 24
Finished Feb 28 05:21:08 PM PST 24
Peak memory 194284 kb
Host smart-67b5fcb5-a319-4a0b-869c-39110d7f0d82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579371644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.579371644
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2753078619
Short name T363
Test name
Test status
Simulation time 99184170 ps
CPU time 0.88 seconds
Started Feb 28 05:21:01 PM PST 24
Finished Feb 28 05:21:02 PM PST 24
Peak memory 194208 kb
Host smart-9ce4a2dc-0cbe-4dbc-a809-1722bca019c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753078619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2753078619
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.38102292
Short name T495
Test name
Test status
Simulation time 350845365 ps
CPU time 5.13 seconds
Started Feb 28 05:21:05 PM PST 24
Finished Feb 28 05:21:10 PM PST 24
Peak memory 196816 kb
Host smart-23c97d1a-33f0-49b1-9bc8-4fae3c22b223
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38102292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stress
.38102292
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2683710661
Short name T149
Test name
Test status
Simulation time 53990236 ps
CPU time 0.85 seconds
Started Feb 28 05:21:03 PM PST 24
Finished Feb 28 05:21:04 PM PST 24
Peak memory 195984 kb
Host smart-387ec77c-d9a5-43bd-8a8f-8b13ce2cf57f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683710661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2683710661
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.4106297817
Short name T239
Test name
Test status
Simulation time 16433781 ps
CPU time 0.69 seconds
Started Feb 28 05:20:58 PM PST 24
Finished Feb 28 05:21:00 PM PST 24
Peak memory 195212 kb
Host smart-8eed2319-032b-4215-98c0-a7580348510c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106297817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.4106297817
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3043207789
Short name T490
Test name
Test status
Simulation time 36890878 ps
CPU time 1.62 seconds
Started Feb 28 05:21:03 PM PST 24
Finished Feb 28 05:21:05 PM PST 24
Peak memory 196424 kb
Host smart-33443c85-3115-4348-8fd3-5aba926c3fa2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043207789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3043207789
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.4237494284
Short name T319
Test name
Test status
Simulation time 82700541 ps
CPU time 1.16 seconds
Started Feb 28 05:21:07 PM PST 24
Finished Feb 28 05:21:09 PM PST 24
Peak memory 195500 kb
Host smart-fd4c627d-fce5-4a21-a942-208761c4e5e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237494284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.4237494284
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2881985578
Short name T182
Test name
Test status
Simulation time 128584436 ps
CPU time 1.18 seconds
Started Feb 28 05:20:59 PM PST 24
Finished Feb 28 05:21:00 PM PST 24
Peak memory 198132 kb
Host smart-9b05add8-957f-42a2-80e1-fef85dea673d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881985578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2881985578
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1686798457
Short name T97
Test name
Test status
Simulation time 113006039 ps
CPU time 1.09 seconds
Started Feb 28 05:20:59 PM PST 24
Finished Feb 28 05:21:01 PM PST 24
Peak memory 196212 kb
Host smart-ea8ee879-adb4-448f-8c9e-9adcaa5604d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686798457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1686798457
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3015930543
Short name T395
Test name
Test status
Simulation time 354642044 ps
CPU time 4.38 seconds
Started Feb 28 05:21:06 PM PST 24
Finished Feb 28 05:21:11 PM PST 24
Peak memory 198092 kb
Host smart-a0473c89-882d-4b02-a1b8-3a27d1d400c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015930543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3015930543
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3542955153
Short name T46
Test name
Test status
Simulation time 45976075 ps
CPU time 0.85 seconds
Started Feb 28 05:20:57 PM PST 24
Finished Feb 28 05:20:59 PM PST 24
Peak memory 196188 kb
Host smart-ad0034a4-b0dc-4c82-b660-cdd799017c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542955153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3542955153
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.925164259
Short name T537
Test name
Test status
Simulation time 414851186 ps
CPU time 1.2 seconds
Started Feb 28 05:20:59 PM PST 24
Finished Feb 28 05:21:00 PM PST 24
Peak memory 196832 kb
Host smart-ea09d80d-b08d-4cab-bd68-de501b6532c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925164259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.925164259
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2044171316
Short name T406
Test name
Test status
Simulation time 31738534589 ps
CPU time 214.67 seconds
Started Feb 28 05:21:06 PM PST 24
Finished Feb 28 05:24:41 PM PST 24
Peak memory 198220 kb
Host smart-e0069c24-69f9-445b-a3ca-750c83017a5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044171316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2044171316
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2330546655
Short name T507
Test name
Test status
Simulation time 81410671565 ps
CPU time 1142.33 seconds
Started Feb 28 05:21:02 PM PST 24
Finished Feb 28 05:40:05 PM PST 24
Peak memory 198324 kb
Host smart-1c3fa1fe-c3c8-4f98-9efa-4ca9278d602c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2330546655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2330546655
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.220740559
Short name T250
Test name
Test status
Simulation time 22932240 ps
CPU time 0.57 seconds
Started Feb 28 05:21:09 PM PST 24
Finished Feb 28 05:21:10 PM PST 24
Peak memory 193892 kb
Host smart-835e2bc0-3076-48cd-b7d0-e816cae35bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220740559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.220740559
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1007059871
Short name T641
Test name
Test status
Simulation time 91641580 ps
CPU time 0.93 seconds
Started Feb 28 05:21:05 PM PST 24
Finished Feb 28 05:21:06 PM PST 24
Peak memory 196492 kb
Host smart-23771777-9c25-420c-8674-7de2a5d6bd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007059871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1007059871
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2908360470
Short name T378
Test name
Test status
Simulation time 756496641 ps
CPU time 11.12 seconds
Started Feb 28 05:21:08 PM PST 24
Finished Feb 28 05:21:19 PM PST 24
Peak memory 195684 kb
Host smart-e18c52a0-5496-4fca-9bd2-5f5d142029f0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908360470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2908360470
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3407099410
Short name T320
Test name
Test status
Simulation time 200027985 ps
CPU time 1.24 seconds
Started Feb 28 05:21:03 PM PST 24
Finished Feb 28 05:21:05 PM PST 24
Peak memory 197840 kb
Host smart-21091b0d-286e-46a3-8ebc-f7c6a7fd6330
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407099410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3407099410
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1487545353
Short name T398
Test name
Test status
Simulation time 142860981 ps
CPU time 0.74 seconds
Started Feb 28 05:21:05 PM PST 24
Finished Feb 28 05:21:06 PM PST 24
Peak memory 195348 kb
Host smart-35f9dd3a-3736-43e5-8b6a-674234d838dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487545353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1487545353
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.644991658
Short name T617
Test name
Test status
Simulation time 788458967 ps
CPU time 2.52 seconds
Started Feb 28 05:21:05 PM PST 24
Finished Feb 28 05:21:08 PM PST 24
Peak memory 198076 kb
Host smart-40836576-fc07-4436-b3ca-326718ad74f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644991658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.644991658
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.4224279055
Short name T275
Test name
Test status
Simulation time 95246187 ps
CPU time 3 seconds
Started Feb 28 05:21:04 PM PST 24
Finished Feb 28 05:21:07 PM PST 24
Peak memory 197000 kb
Host smart-11d8ecb2-345f-4840-adbc-e4e6a14d5d12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224279055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.4224279055
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.483000041
Short name T712
Test name
Test status
Simulation time 228077539 ps
CPU time 1.38 seconds
Started Feb 28 05:21:03 PM PST 24
Finished Feb 28 05:21:05 PM PST 24
Peak memory 198156 kb
Host smart-08ec0e8c-bfb8-4806-b358-2a2e002d033c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483000041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.483000041
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2226882536
Short name T387
Test name
Test status
Simulation time 71535391 ps
CPU time 1.45 seconds
Started Feb 28 05:21:04 PM PST 24
Finished Feb 28 05:21:06 PM PST 24
Peak memory 197084 kb
Host smart-c42c397a-94cc-42bb-a119-c5516c708c0f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226882536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2226882536
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2387739368
Short name T290
Test name
Test status
Simulation time 1139892802 ps
CPU time 3.94 seconds
Started Feb 28 05:21:06 PM PST 24
Finished Feb 28 05:21:10 PM PST 24
Peak memory 198024 kb
Host smart-83b21d43-743d-401d-bb47-2b11bba830c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387739368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2387739368
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.574517484
Short name T410
Test name
Test status
Simulation time 65022508 ps
CPU time 1.12 seconds
Started Feb 28 05:21:02 PM PST 24
Finished Feb 28 05:21:03 PM PST 24
Peak memory 195528 kb
Host smart-b56c1938-ed41-4404-acfe-ca8501d49fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574517484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.574517484
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.922614804
Short name T583
Test name
Test status
Simulation time 31512147 ps
CPU time 0.92 seconds
Started Feb 28 05:21:08 PM PST 24
Finished Feb 28 05:21:09 PM PST 24
Peak memory 195328 kb
Host smart-08cc1869-c5bc-4925-ab35-22c42c1b4f24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922614804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.922614804
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1111985215
Short name T199
Test name
Test status
Simulation time 11317935468 ps
CPU time 165.56 seconds
Started Feb 28 05:21:04 PM PST 24
Finished Feb 28 05:23:50 PM PST 24
Peak memory 198212 kb
Host smart-09f94db0-1189-4d09-85d5-980aae882bcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111985215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1111985215
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.339437701
Short name T53
Test name
Test status
Simulation time 96370284578 ps
CPU time 1072.51 seconds
Started Feb 28 05:21:08 PM PST 24
Finished Feb 28 05:39:01 PM PST 24
Peak memory 198376 kb
Host smart-206b9db5-106b-44e4-aa16-deb579f96022
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=339437701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.339437701
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.210216831
Short name T38
Test name
Test status
Simulation time 36280467 ps
CPU time 0.55 seconds
Started Feb 28 05:21:18 PM PST 24
Finished Feb 28 05:21:19 PM PST 24
Peak memory 194048 kb
Host smart-126a2c47-8088-441c-b6fe-aaa5859af3a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210216831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.210216831
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3885441761
Short name T615
Test name
Test status
Simulation time 187713456 ps
CPU time 0.95 seconds
Started Feb 28 05:21:09 PM PST 24
Finished Feb 28 05:21:10 PM PST 24
Peak memory 196424 kb
Host smart-7a816f8c-82c5-49eb-99ae-173a2da10c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885441761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3885441761
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.216677826
Short name T706
Test name
Test status
Simulation time 652847314 ps
CPU time 22.63 seconds
Started Feb 28 05:21:14 PM PST 24
Finished Feb 28 05:21:36 PM PST 24
Peak memory 197056 kb
Host smart-7145db41-1385-43bf-a968-ea831f497d7f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216677826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.216677826
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2719671716
Short name T292
Test name
Test status
Simulation time 94394672 ps
CPU time 0.65 seconds
Started Feb 28 05:21:12 PM PST 24
Finished Feb 28 05:21:12 PM PST 24
Peak memory 195348 kb
Host smart-2a4acd05-29ee-4786-9157-76d4e8cd5ddb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719671716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2719671716
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1693841256
Short name T49
Test name
Test status
Simulation time 136260477 ps
CPU time 1.31 seconds
Started Feb 28 05:21:11 PM PST 24
Finished Feb 28 05:21:12 PM PST 24
Peak memory 195872 kb
Host smart-b76e54a9-66f3-43e8-92db-9d019821a86f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693841256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1693841256
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2297784748
Short name T680
Test name
Test status
Simulation time 39646657 ps
CPU time 1.07 seconds
Started Feb 28 05:21:08 PM PST 24
Finished Feb 28 05:21:09 PM PST 24
Peak memory 197036 kb
Host smart-59027e78-2ead-4f42-803b-9316262350ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297784748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2297784748
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3801009387
Short name T572
Test name
Test status
Simulation time 498594138 ps
CPU time 2.5 seconds
Started Feb 28 05:21:08 PM PST 24
Finished Feb 28 05:21:11 PM PST 24
Peak memory 197232 kb
Host smart-457e8bcb-dbf1-484e-aeee-a83c22ed3982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801009387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3801009387
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.988663381
Short name T616
Test name
Test status
Simulation time 23588606 ps
CPU time 1.15 seconds
Started Feb 28 05:21:09 PM PST 24
Finished Feb 28 05:21:10 PM PST 24
Peak memory 196840 kb
Host smart-9136f097-61ba-4c0f-8e5c-81635f9b9e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988663381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.988663381
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.897765208
Short name T506
Test name
Test status
Simulation time 15234744 ps
CPU time 0.68 seconds
Started Feb 28 05:21:07 PM PST 24
Finished Feb 28 05:21:08 PM PST 24
Peak memory 194456 kb
Host smart-513eb0ec-32e6-4755-8be2-3ecd82986d0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897765208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.897765208
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1460721792
Short name T9
Test name
Test status
Simulation time 521050453 ps
CPU time 2.52 seconds
Started Feb 28 05:21:11 PM PST 24
Finished Feb 28 05:21:14 PM PST 24
Peak memory 198104 kb
Host smart-bfcf1703-c915-4ce8-a031-2ea3d62a55c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460721792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1460721792
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2442795121
Short name T112
Test name
Test status
Simulation time 188774174 ps
CPU time 1.63 seconds
Started Feb 28 05:21:03 PM PST 24
Finished Feb 28 05:21:05 PM PST 24
Peak memory 198052 kb
Host smart-a0764c9f-06aa-43af-92e7-6e990e978235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442795121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2442795121
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.87052205
Short name T288
Test name
Test status
Simulation time 554533456 ps
CPU time 1.03 seconds
Started Feb 28 05:21:08 PM PST 24
Finished Feb 28 05:21:09 PM PST 24
Peak memory 195888 kb
Host smart-cd236b7f-7341-490e-81dd-55a07a3d22d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87052205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.87052205
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.737454742
Short name T600
Test name
Test status
Simulation time 3654284660 ps
CPU time 37.06 seconds
Started Feb 28 05:21:13 PM PST 24
Finished Feb 28 05:21:50 PM PST 24
Peak memory 198144 kb
Host smart-9b71c152-15ef-4c4e-99fa-3b4b8741488f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737454742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.737454742
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3873210953
Short name T261
Test name
Test status
Simulation time 44056186 ps
CPU time 0.59 seconds
Started Feb 28 05:21:16 PM PST 24
Finished Feb 28 05:21:16 PM PST 24
Peak memory 194176 kb
Host smart-cd4a072a-eaa4-43ba-bbfc-e530a09f0a40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873210953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3873210953
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3523907179
Short name T101
Test name
Test status
Simulation time 97949317 ps
CPU time 0.78 seconds
Started Feb 28 05:21:12 PM PST 24
Finished Feb 28 05:21:13 PM PST 24
Peak memory 196000 kb
Host smart-64aa954d-0aa6-46c4-9508-176bd065399d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523907179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3523907179
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2091469630
Short name T187
Test name
Test status
Simulation time 1146394496 ps
CPU time 19.36 seconds
Started Feb 28 05:21:20 PM PST 24
Finished Feb 28 05:21:40 PM PST 24
Peak memory 197124 kb
Host smart-c82d11ed-eb2d-41df-98bb-dc6b19581fe8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091469630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2091469630
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1921025541
Short name T639
Test name
Test status
Simulation time 77363731 ps
CPU time 1 seconds
Started Feb 28 05:21:11 PM PST 24
Finished Feb 28 05:21:12 PM PST 24
Peak memory 196620 kb
Host smart-c3df39ca-b05c-46b4-a39c-2567317b4af4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921025541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1921025541
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3952317641
Short name T207
Test name
Test status
Simulation time 427902727 ps
CPU time 1.03 seconds
Started Feb 28 05:21:11 PM PST 24
Finished Feb 28 05:21:12 PM PST 24
Peak memory 196136 kb
Host smart-b6d0ec4a-0ab0-42e2-852f-cc7a5a97a4f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952317641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3952317641
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3457164690
Short name T137
Test name
Test status
Simulation time 264637693 ps
CPU time 2.45 seconds
Started Feb 28 05:21:25 PM PST 24
Finished Feb 28 05:21:28 PM PST 24
Peak memory 198236 kb
Host smart-ca03bef2-9419-4dc3-9d78-1aae5e3e7e07
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457164690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3457164690
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3339679027
Short name T237
Test name
Test status
Simulation time 322500908 ps
CPU time 2.82 seconds
Started Feb 28 05:21:11 PM PST 24
Finished Feb 28 05:21:14 PM PST 24
Peak memory 195816 kb
Host smart-1a451f22-1520-4755-96b1-c09f575b67dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339679027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3339679027
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2746072537
Short name T306
Test name
Test status
Simulation time 55883603 ps
CPU time 0.86 seconds
Started Feb 28 05:21:13 PM PST 24
Finished Feb 28 05:21:14 PM PST 24
Peak memory 197324 kb
Host smart-0fbee987-9fd1-42c1-ac7f-f329d59d02f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746072537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2746072537
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3733952230
Short name T266
Test name
Test status
Simulation time 293956234 ps
CPU time 1.43 seconds
Started Feb 28 05:21:14 PM PST 24
Finished Feb 28 05:21:15 PM PST 24
Peak memory 197044 kb
Host smart-5bdc34f9-f252-4a49-9829-e4f1403e369b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733952230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3733952230
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2119656944
Short name T560
Test name
Test status
Simulation time 296914007 ps
CPU time 3.64 seconds
Started Feb 28 05:21:11 PM PST 24
Finished Feb 28 05:21:15 PM PST 24
Peak memory 198112 kb
Host smart-6fed19f6-c3d7-4257-a412-3bf264247cd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119656944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2119656944
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1431336823
Short name T677
Test name
Test status
Simulation time 23558332 ps
CPU time 0.89 seconds
Started Feb 28 05:21:21 PM PST 24
Finished Feb 28 05:21:22 PM PST 24
Peak memory 196132 kb
Host smart-e4d06287-6f17-4a1b-a273-da6b146083ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431336823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1431336823
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3635956998
Short name T678
Test name
Test status
Simulation time 83797565 ps
CPU time 0.68 seconds
Started Feb 28 05:21:14 PM PST 24
Finished Feb 28 05:21:15 PM PST 24
Peak memory 194092 kb
Host smart-8d07de11-064a-47d2-9eab-6d920493966d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635956998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3635956998
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3872656987
Short name T114
Test name
Test status
Simulation time 11236629570 ps
CPU time 173.93 seconds
Started Feb 28 05:21:17 PM PST 24
Finished Feb 28 05:24:11 PM PST 24
Peak memory 198312 kb
Host smart-acfd09c8-6ef0-47e5-bb9a-ea32e3004951
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872656987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3872656987
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.246639473
Short name T67
Test name
Test status
Simulation time 204506517434 ps
CPU time 772.74 seconds
Started Feb 28 05:21:13 PM PST 24
Finished Feb 28 05:34:06 PM PST 24
Peak memory 198344 kb
Host smart-08083262-ad7d-4b70-8edb-fd0718dfb706
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=246639473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.246639473
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3978141059
Short name T371
Test name
Test status
Simulation time 13390168 ps
CPU time 0.58 seconds
Started Feb 28 05:21:19 PM PST 24
Finished Feb 28 05:21:20 PM PST 24
Peak memory 194024 kb
Host smart-bcc2245e-a70e-4e47-b9bc-10e943fb1fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978141059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3978141059
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.541990050
Short name T634
Test name
Test status
Simulation time 27433801 ps
CPU time 0.67 seconds
Started Feb 28 05:21:16 PM PST 24
Finished Feb 28 05:21:17 PM PST 24
Peak memory 194208 kb
Host smart-bbc137f5-c646-4587-a593-6bceecf49619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541990050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.541990050
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3371795939
Short name T581
Test name
Test status
Simulation time 513934456 ps
CPU time 4.63 seconds
Started Feb 28 05:21:25 PM PST 24
Finished Feb 28 05:21:30 PM PST 24
Peak memory 196096 kb
Host smart-636211eb-a051-4231-8db3-88515333349b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371795939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3371795939
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.412858100
Short name T454
Test name
Test status
Simulation time 188738598 ps
CPU time 0.89 seconds
Started Feb 28 05:21:19 PM PST 24
Finished Feb 28 05:21:20 PM PST 24
Peak memory 195848 kb
Host smart-4cbf71d3-5cde-47b9-aa0d-efa9d1a81bbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412858100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.412858100
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.433953686
Short name T44
Test name
Test status
Simulation time 85582177 ps
CPU time 1.25 seconds
Started Feb 28 05:21:16 PM PST 24
Finished Feb 28 05:21:17 PM PST 24
Peak memory 196208 kb
Host smart-7e3983c1-dffe-4e72-b68b-14212d352997
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433953686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.433953686
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1177701483
Short name T442
Test name
Test status
Simulation time 100066533 ps
CPU time 1.3 seconds
Started Feb 28 05:21:15 PM PST 24
Finished Feb 28 05:21:16 PM PST 24
Peak memory 196700 kb
Host smart-2ccadbcd-8021-4012-b1af-57b6c93224be
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177701483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1177701483
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2570295080
Short name T488
Test name
Test status
Simulation time 655834997 ps
CPU time 2.68 seconds
Started Feb 28 05:21:16 PM PST 24
Finished Feb 28 05:21:19 PM PST 24
Peak memory 197100 kb
Host smart-2622bd8f-5d1b-444c-a540-f5d9c28df5ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570295080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2570295080
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2223806702
Short name T638
Test name
Test status
Simulation time 76386610 ps
CPU time 1.45 seconds
Started Feb 28 05:21:15 PM PST 24
Finished Feb 28 05:21:17 PM PST 24
Peak memory 195916 kb
Host smart-23244fb7-827f-4b78-9edf-baca240e76f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223806702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2223806702
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2368167264
Short name T358
Test name
Test status
Simulation time 256914162 ps
CPU time 1.26 seconds
Started Feb 28 05:21:17 PM PST 24
Finished Feb 28 05:21:18 PM PST 24
Peak memory 195940 kb
Host smart-26ae1653-60b7-4b79-b4c9-fe0884fa98a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368167264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2368167264
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1568519273
Short name T613
Test name
Test status
Simulation time 125480134 ps
CPU time 2.12 seconds
Started Feb 28 05:21:15 PM PST 24
Finished Feb 28 05:21:17 PM PST 24
Peak memory 198136 kb
Host smart-7db49ddd-ad1f-4cd6-ac33-b6e5d490baae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568519273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1568519273
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.531735644
Short name T651
Test name
Test status
Simulation time 93423274 ps
CPU time 1.42 seconds
Started Feb 28 05:21:14 PM PST 24
Finished Feb 28 05:21:16 PM PST 24
Peak memory 195636 kb
Host smart-b35febbc-3ed0-463a-bccb-cf70c54876fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531735644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.531735644
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4156490661
Short name T307
Test name
Test status
Simulation time 73458652 ps
CPU time 1.26 seconds
Started Feb 28 05:21:16 PM PST 24
Finished Feb 28 05:21:18 PM PST 24
Peak memory 196464 kb
Host smart-f89cdd8e-7f3a-430e-b326-6482375c6295
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156490661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4156490661
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3237559542
Short name T336
Test name
Test status
Simulation time 20853813377 ps
CPU time 127.99 seconds
Started Feb 28 05:21:18 PM PST 24
Finished Feb 28 05:23:26 PM PST 24
Peak memory 198236 kb
Host smart-f2b3c59e-13e8-4ae0-93bb-e79a6debf20b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237559542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3237559542
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2713420454
Short name T598
Test name
Test status
Simulation time 32485884 ps
CPU time 0.56 seconds
Started Feb 28 05:21:23 PM PST 24
Finished Feb 28 05:21:24 PM PST 24
Peak memory 194144 kb
Host smart-ee55f6ca-de1d-4d47-9830-3d0288b5158c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713420454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2713420454
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2459467988
Short name T478
Test name
Test status
Simulation time 23428849 ps
CPU time 0.68 seconds
Started Feb 28 05:21:20 PM PST 24
Finished Feb 28 05:21:21 PM PST 24
Peak memory 194072 kb
Host smart-87565af5-bf44-40a2-af82-23c960febd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459467988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2459467988
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3951476131
Short name T45
Test name
Test status
Simulation time 1297328692 ps
CPU time 18.49 seconds
Started Feb 28 05:21:26 PM PST 24
Finished Feb 28 05:21:44 PM PST 24
Peak memory 197016 kb
Host smart-72962049-84a2-40b3-89d4-0c030b97d00e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951476131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3951476131
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2180497601
Short name T509
Test name
Test status
Simulation time 148380727 ps
CPU time 0.68 seconds
Started Feb 28 05:21:21 PM PST 24
Finished Feb 28 05:21:22 PM PST 24
Peak memory 194648 kb
Host smart-ebae4194-7610-41c9-b2f9-29bd7a57b3e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180497601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2180497601
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1527080728
Short name T194
Test name
Test status
Simulation time 56787639 ps
CPU time 1.59 seconds
Started Feb 28 05:21:21 PM PST 24
Finished Feb 28 05:21:23 PM PST 24
Peak memory 198184 kb
Host smart-f8aaf22f-77ae-4f47-9a57-c6c5fdc63bba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527080728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1527080728
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3173951405
Short name T353
Test name
Test status
Simulation time 30514462 ps
CPU time 1.3 seconds
Started Feb 28 05:21:19 PM PST 24
Finished Feb 28 05:21:21 PM PST 24
Peak memory 196828 kb
Host smart-b605ab9a-e50f-4f08-95db-57973df0e329
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173951405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3173951405
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2284364583
Short name T59
Test name
Test status
Simulation time 726309635 ps
CPU time 2.36 seconds
Started Feb 28 05:21:21 PM PST 24
Finished Feb 28 05:21:24 PM PST 24
Peak memory 197140 kb
Host smart-251b877e-8acc-4026-b31a-a1e3846e36b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284364583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2284364583
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.960588722
Short name T113
Test name
Test status
Simulation time 221885706 ps
CPU time 1.29 seconds
Started Feb 28 05:21:20 PM PST 24
Finished Feb 28 05:21:22 PM PST 24
Peak memory 195876 kb
Host smart-329c6b94-cf15-42a0-a200-029d0b4c623b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960588722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.960588722
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2196934301
Short name T163
Test name
Test status
Simulation time 47654478 ps
CPU time 0.7 seconds
Started Feb 28 05:21:22 PM PST 24
Finished Feb 28 05:21:23 PM PST 24
Peak memory 194980 kb
Host smart-4fafb2f0-2407-4582-bcd9-9ee7f691aefe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196934301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2196934301
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1781884970
Short name T654
Test name
Test status
Simulation time 456413559 ps
CPU time 3.95 seconds
Started Feb 28 05:21:25 PM PST 24
Finished Feb 28 05:21:30 PM PST 24
Peak memory 198124 kb
Host smart-e3a794d7-2d41-4e80-a0c7-a9d638f956da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781884970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1781884970
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.128372812
Short name T51
Test name
Test status
Simulation time 141676893 ps
CPU time 0.87 seconds
Started Feb 28 05:21:18 PM PST 24
Finished Feb 28 05:21:19 PM PST 24
Peak memory 195392 kb
Host smart-6ecb4c54-1349-40e5-a3b5-c3f2c9eb76e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128372812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.128372812
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.125763418
Short name T270
Test name
Test status
Simulation time 32077281 ps
CPU time 0.99 seconds
Started Feb 28 05:21:26 PM PST 24
Finished Feb 28 05:21:27 PM PST 24
Peak memory 195664 kb
Host smart-959185a0-6880-4874-b7ce-9be6baf221fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125763418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.125763418
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2426095162
Short name T687
Test name
Test status
Simulation time 15898918184 ps
CPU time 124.12 seconds
Started Feb 28 05:21:19 PM PST 24
Finished Feb 28 05:23:24 PM PST 24
Peak memory 198240 kb
Host smart-4d37e304-cb36-4416-91bc-f14f4aebac28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426095162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2426095162
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1243885577
Short name T217
Test name
Test status
Simulation time 13271963 ps
CPU time 0.55 seconds
Started Feb 28 05:21:27 PM PST 24
Finished Feb 28 05:21:27 PM PST 24
Peak memory 194840 kb
Host smart-2de9e9b0-4056-4f08-ad6a-2bafea80e52f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243885577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1243885577
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.463607329
Short name T155
Test name
Test status
Simulation time 15253777 ps
CPU time 0.67 seconds
Started Feb 28 05:21:24 PM PST 24
Finished Feb 28 05:21:25 PM PST 24
Peak memory 194100 kb
Host smart-ee2b03f2-7f0e-4c17-9ca7-0466b0126e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463607329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.463607329
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.4014611722
Short name T632
Test name
Test status
Simulation time 416492558 ps
CPU time 12.17 seconds
Started Feb 28 05:21:25 PM PST 24
Finished Feb 28 05:21:38 PM PST 24
Peak memory 197104 kb
Host smart-54b28d81-f71c-435d-8fc8-ecf97b013e6c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014611722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.4014611722
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1115008176
Short name T527
Test name
Test status
Simulation time 23033359 ps
CPU time 0.67 seconds
Started Feb 28 05:21:29 PM PST 24
Finished Feb 28 05:21:29 PM PST 24
Peak memory 195292 kb
Host smart-6835090f-c2de-4e88-8159-e22b7c399475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115008176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1115008176
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3705319561
Short name T662
Test name
Test status
Simulation time 85624639 ps
CPU time 1.04 seconds
Started Feb 28 05:21:23 PM PST 24
Finished Feb 28 05:21:25 PM PST 24
Peak memory 196580 kb
Host smart-86d6993e-6974-4498-8571-b3f3b1e188d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705319561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3705319561
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1810666846
Short name T243
Test name
Test status
Simulation time 49142301 ps
CPU time 1.91 seconds
Started Feb 28 05:21:25 PM PST 24
Finished Feb 28 05:21:27 PM PST 24
Peak memory 196576 kb
Host smart-03330117-f4bf-41f5-8879-f9b65b7035d0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810666846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1810666846
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3189511956
Short name T422
Test name
Test status
Simulation time 466442615 ps
CPU time 3.03 seconds
Started Feb 28 05:21:24 PM PST 24
Finished Feb 28 05:21:27 PM PST 24
Peak memory 196592 kb
Host smart-6f25e55a-1deb-4248-8506-06f424ed25f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189511956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3189511956
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1006837484
Short name T407
Test name
Test status
Simulation time 20342212 ps
CPU time 0.8 seconds
Started Feb 28 05:21:24 PM PST 24
Finished Feb 28 05:21:25 PM PST 24
Peak memory 195424 kb
Host smart-9aa4e158-3be2-4683-aa9c-c4afd0ee3c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006837484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1006837484
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2528074427
Short name T425
Test name
Test status
Simulation time 37772946 ps
CPU time 0.88 seconds
Started Feb 28 05:21:24 PM PST 24
Finished Feb 28 05:21:25 PM PST 24
Peak memory 196176 kb
Host smart-3c1bf0f1-08a7-4be4-8d12-aced54517970
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528074427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2528074427
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1797979491
Short name T7
Test name
Test status
Simulation time 3314270840 ps
CPU time 5.62 seconds
Started Feb 28 05:21:27 PM PST 24
Finished Feb 28 05:21:32 PM PST 24
Peak memory 198100 kb
Host smart-56997bf9-c9be-4d6f-9636-cda8db854cfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797979491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1797979491
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2239385355
Short name T298
Test name
Test status
Simulation time 128750030 ps
CPU time 1.17 seconds
Started Feb 28 05:21:25 PM PST 24
Finished Feb 28 05:21:26 PM PST 24
Peak memory 195712 kb
Host smart-575bbbff-a21f-446c-bae5-abaa80756a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239385355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2239385355
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1845548620
Short name T323
Test name
Test status
Simulation time 266693150 ps
CPU time 1.17 seconds
Started Feb 28 05:21:26 PM PST 24
Finished Feb 28 05:21:27 PM PST 24
Peak memory 196464 kb
Host smart-641a10d0-d8ed-497b-8d67-35382c13dd86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845548620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1845548620
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.897323094
Short name T198
Test name
Test status
Simulation time 14075311466 ps
CPU time 195.19 seconds
Started Feb 28 05:21:27 PM PST 24
Finished Feb 28 05:24:42 PM PST 24
Peak memory 198240 kb
Host smart-1df96857-56dc-40c1-8690-44d2bf5a8f6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897323094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.897323094
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1816055938
Short name T520
Test name
Test status
Simulation time 14291466 ps
CPU time 0.61 seconds
Started Feb 28 05:19:52 PM PST 24
Finished Feb 28 05:19:53 PM PST 24
Peak memory 194816 kb
Host smart-b2b46ec2-37c1-4b13-8068-40148585666d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816055938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1816055938
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3647759380
Short name T354
Test name
Test status
Simulation time 17564170 ps
CPU time 0.72 seconds
Started Feb 28 05:19:49 PM PST 24
Finished Feb 28 05:19:51 PM PST 24
Peak memory 194204 kb
Host smart-0b88fa39-ff14-40e5-9601-6b76edf0d518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647759380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3647759380
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1963997014
Short name T183
Test name
Test status
Simulation time 2052531582 ps
CPU time 26.63 seconds
Started Feb 28 05:19:53 PM PST 24
Finished Feb 28 05:20:20 PM PST 24
Peak memory 195672 kb
Host smart-68382218-e4b4-4cf7-b310-4c917dc20a65
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963997014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1963997014
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.793841981
Short name T709
Test name
Test status
Simulation time 263196370 ps
CPU time 0.98 seconds
Started Feb 28 05:19:52 PM PST 24
Finished Feb 28 05:19:53 PM PST 24
Peak memory 196176 kb
Host smart-46fa49bb-caf7-4f7a-b38c-bb2bf18332a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793841981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.793841981
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1454901959
Short name T274
Test name
Test status
Simulation time 48965177 ps
CPU time 1.09 seconds
Started Feb 28 05:19:50 PM PST 24
Finished Feb 28 05:19:51 PM PST 24
Peak memory 196848 kb
Host smart-fba26394-7c4c-47c2-bffe-c568edaf77f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454901959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1454901959
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1518165673
Short name T326
Test name
Test status
Simulation time 256157141 ps
CPU time 2.72 seconds
Started Feb 28 05:19:51 PM PST 24
Finished Feb 28 05:19:54 PM PST 24
Peak memory 198104 kb
Host smart-defcac7c-5854-430f-a3d3-9e3f9dc133a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518165673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1518165673
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3983829472
Short name T433
Test name
Test status
Simulation time 193139038 ps
CPU time 1.24 seconds
Started Feb 28 05:19:52 PM PST 24
Finished Feb 28 05:19:53 PM PST 24
Peak memory 195668 kb
Host smart-7f4fbdfd-194b-4072-8077-193486d83ac1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983829472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3983829472
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1417626251
Short name T286
Test name
Test status
Simulation time 66203724 ps
CPU time 1.3 seconds
Started Feb 28 05:19:48 PM PST 24
Finished Feb 28 05:19:49 PM PST 24
Peak memory 196632 kb
Host smart-dfa3ed69-fe4b-4c19-8086-1ad730879552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417626251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1417626251
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3503410854
Short name T501
Test name
Test status
Simulation time 85140147 ps
CPU time 1.02 seconds
Started Feb 28 05:19:48 PM PST 24
Finished Feb 28 05:19:49 PM PST 24
Peak memory 196088 kb
Host smart-7aebb4c9-a525-49e2-bdb2-555627238d02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503410854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3503410854
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1548217819
Short name T574
Test name
Test status
Simulation time 424789773 ps
CPU time 5.52 seconds
Started Feb 28 05:19:53 PM PST 24
Finished Feb 28 05:19:59 PM PST 24
Peak memory 198036 kb
Host smart-194a2c66-d513-41c1-9c17-e0785f5ec00c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548217819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1548217819
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1969543607
Short name T33
Test name
Test status
Simulation time 348062725 ps
CPU time 0.92 seconds
Started Feb 28 05:19:52 PM PST 24
Finished Feb 28 05:19:53 PM PST 24
Peak memory 213808 kb
Host smart-63215031-2f53-4019-86f0-334656fa7888
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969543607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1969543607
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3057091778
Short name T620
Test name
Test status
Simulation time 197727916 ps
CPU time 1.11 seconds
Started Feb 28 05:19:46 PM PST 24
Finished Feb 28 05:19:47 PM PST 24
Peak memory 195772 kb
Host smart-3f89caec-7007-44d9-afb7-c7e1722a4b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057091778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3057091778
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3319658083
Short name T272
Test name
Test status
Simulation time 136099313 ps
CPU time 1.55 seconds
Started Feb 28 05:19:48 PM PST 24
Finished Feb 28 05:19:50 PM PST 24
Peak memory 198160 kb
Host smart-108fe2c0-9bf3-43eb-a295-fd5875196b45
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319658083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3319658083
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3363920183
Short name T2
Test name
Test status
Simulation time 30664454141 ps
CPU time 86.04 seconds
Started Feb 28 05:19:51 PM PST 24
Finished Feb 28 05:21:17 PM PST 24
Peak memory 198236 kb
Host smart-b2cbc4f9-6586-42e4-95e1-96231ff796ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363920183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3363920183
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.401155234
Short name T668
Test name
Test status
Simulation time 38780657934 ps
CPU time 464.82 seconds
Started Feb 28 05:19:50 PM PST 24
Finished Feb 28 05:27:35 PM PST 24
Peak memory 198384 kb
Host smart-39e4e59b-e492-402b-88a2-ecc0205754ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=401155234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.401155234
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.4276435468
Short name T685
Test name
Test status
Simulation time 44980333 ps
CPU time 0.57 seconds
Started Feb 28 05:21:36 PM PST 24
Finished Feb 28 05:21:37 PM PST 24
Peak memory 194172 kb
Host smart-52554f5c-4cf0-4b4a-ae1e-a05f553b1bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276435468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.4276435468
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.256904299
Short name T484
Test name
Test status
Simulation time 63959461 ps
CPU time 0.75 seconds
Started Feb 28 05:21:31 PM PST 24
Finished Feb 28 05:21:32 PM PST 24
Peak memory 195364 kb
Host smart-c2774dfa-973f-46cc-9f14-7b13af828ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256904299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.256904299
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2499207180
Short name T456
Test name
Test status
Simulation time 1722486068 ps
CPU time 22.46 seconds
Started Feb 28 05:21:34 PM PST 24
Finished Feb 28 05:21:56 PM PST 24
Peak memory 198172 kb
Host smart-f3466bd5-b179-4023-88f3-3c3c769c6272
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499207180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2499207180
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1905969448
Short name T474
Test name
Test status
Simulation time 146308069 ps
CPU time 1.13 seconds
Started Feb 28 05:21:34 PM PST 24
Finished Feb 28 05:21:35 PM PST 24
Peak memory 196656 kb
Host smart-5522fda5-0b43-41cb-80aa-0bf2d0c6bb96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905969448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1905969448
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2060015263
Short name T569
Test name
Test status
Simulation time 62816514 ps
CPU time 0.91 seconds
Started Feb 28 05:21:30 PM PST 24
Finished Feb 28 05:21:31 PM PST 24
Peak memory 196524 kb
Host smart-4f7d1bb5-ff61-4d47-9ba4-1dca7a068551
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060015263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2060015263
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1876856402
Short name T558
Test name
Test status
Simulation time 109054227 ps
CPU time 1.39 seconds
Started Feb 28 05:21:30 PM PST 24
Finished Feb 28 05:21:32 PM PST 24
Peak memory 198180 kb
Host smart-5f72b0ee-fcd3-4466-90a7-51cd26f59053
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876856402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1876856402
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3959810946
Short name T535
Test name
Test status
Simulation time 135841966 ps
CPU time 2.28 seconds
Started Feb 28 05:21:30 PM PST 24
Finished Feb 28 05:21:33 PM PST 24
Peak memory 196628 kb
Host smart-a14cc7ab-c527-4d8c-9e3d-cf425502c552
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959810946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3959810946
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3476322457
Short name T231
Test name
Test status
Simulation time 78165644 ps
CPU time 0.81 seconds
Started Feb 28 05:21:36 PM PST 24
Finished Feb 28 05:21:37 PM PST 24
Peak memory 196484 kb
Host smart-c87f4bd0-9f42-4f0c-ad41-81dbf0008aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476322457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3476322457
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2092039749
Short name T640
Test name
Test status
Simulation time 17637152 ps
CPU time 0.73 seconds
Started Feb 28 05:21:30 PM PST 24
Finished Feb 28 05:21:31 PM PST 24
Peak memory 195388 kb
Host smart-94d7a597-2c02-443a-a462-4cff275c818f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092039749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2092039749
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.957050374
Short name T393
Test name
Test status
Simulation time 1059198405 ps
CPU time 6.08 seconds
Started Feb 28 05:21:34 PM PST 24
Finished Feb 28 05:21:40 PM PST 24
Peak memory 198036 kb
Host smart-60782d91-123c-4e25-9305-cb534b5cc3d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957050374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.957050374
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1768379610
Short name T661
Test name
Test status
Simulation time 289121480 ps
CPU time 0.8 seconds
Started Feb 28 05:21:30 PM PST 24
Finished Feb 28 05:21:30 PM PST 24
Peak memory 195920 kb
Host smart-6d510a29-6bff-4081-a175-d557b57efc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768379610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1768379610
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3879706452
Short name T533
Test name
Test status
Simulation time 52284275 ps
CPU time 0.92 seconds
Started Feb 28 05:21:25 PM PST 24
Finished Feb 28 05:21:26 PM PST 24
Peak memory 196308 kb
Host smart-a1f28418-1863-49a8-ac1a-589195886f9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879706452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3879706452
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2644954319
Short name T528
Test name
Test status
Simulation time 5323872592 ps
CPU time 111.11 seconds
Started Feb 28 05:21:33 PM PST 24
Finished Feb 28 05:23:24 PM PST 24
Peak memory 198184 kb
Host smart-9000a1ba-01e1-44ff-83e5-3bbd67d4d341
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644954319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2644954319
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.47703932
Short name T316
Test name
Test status
Simulation time 87104151 ps
CPU time 0.58 seconds
Started Feb 28 05:21:34 PM PST 24
Finished Feb 28 05:21:35 PM PST 24
Peak memory 194144 kb
Host smart-d3be397e-1e7b-44e5-9115-979460725f57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47703932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.47703932
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2950045619
Short name T26
Test name
Test status
Simulation time 13845372 ps
CPU time 0.65 seconds
Started Feb 28 05:21:33 PM PST 24
Finished Feb 28 05:21:34 PM PST 24
Peak memory 194772 kb
Host smart-9d876c56-09c7-4ad2-b626-b991f6abfff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950045619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2950045619
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.964361585
Short name T329
Test name
Test status
Simulation time 216194815 ps
CPU time 5.31 seconds
Started Feb 28 05:21:36 PM PST 24
Finished Feb 28 05:21:42 PM PST 24
Peak memory 196488 kb
Host smart-cfd8d352-e181-4859-9e25-b20dab83880d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964361585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.964361585
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.212722798
Short name T565
Test name
Test status
Simulation time 141763558 ps
CPU time 1.01 seconds
Started Feb 28 05:21:33 PM PST 24
Finished Feb 28 05:21:34 PM PST 24
Peak memory 197832 kb
Host smart-3046ab7c-4375-41af-9805-d4e2a2338851
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212722798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.212722798
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3259851983
Short name T356
Test name
Test status
Simulation time 67209004 ps
CPU time 0.83 seconds
Started Feb 28 05:21:35 PM PST 24
Finished Feb 28 05:21:36 PM PST 24
Peak memory 195496 kb
Host smart-646f9f7f-70ae-4d22-a414-c8bda44c4c31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259851983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3259851983
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2201195039
Short name T368
Test name
Test status
Simulation time 323282615 ps
CPU time 3.13 seconds
Started Feb 28 05:21:32 PM PST 24
Finished Feb 28 05:21:35 PM PST 24
Peak memory 198192 kb
Host smart-556d594e-e2b9-4553-ae6f-66589130fd4d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201195039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2201195039
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1144802133
Short name T645
Test name
Test status
Simulation time 88348533 ps
CPU time 1.79 seconds
Started Feb 28 05:21:30 PM PST 24
Finished Feb 28 05:21:32 PM PST 24
Peak memory 196120 kb
Host smart-73067811-c1c7-45e8-844a-55c103c7733b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144802133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1144802133
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3769258742
Short name T516
Test name
Test status
Simulation time 187556120 ps
CPU time 1.28 seconds
Started Feb 28 05:21:35 PM PST 24
Finished Feb 28 05:21:37 PM PST 24
Peak memory 195868 kb
Host smart-89a783cc-7d11-4718-b3fb-913110e21e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769258742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3769258742
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.4088490788
Short name T621
Test name
Test status
Simulation time 32116157 ps
CPU time 1.3 seconds
Started Feb 28 05:21:33 PM PST 24
Finished Feb 28 05:21:34 PM PST 24
Peak memory 197124 kb
Host smart-d6960eb5-941d-468e-9dad-c922c58f67cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088490788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.4088490788
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1115725365
Short name T604
Test name
Test status
Simulation time 107546115 ps
CPU time 1.72 seconds
Started Feb 28 05:21:31 PM PST 24
Finished Feb 28 05:21:33 PM PST 24
Peak memory 198084 kb
Host smart-41e066d7-dca6-4835-8b9d-b61f6a82979e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115725365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1115725365
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3485079667
Short name T256
Test name
Test status
Simulation time 64031814 ps
CPU time 1.21 seconds
Started Feb 28 05:21:33 PM PST 24
Finished Feb 28 05:21:34 PM PST 24
Peak memory 195668 kb
Host smart-2477fa47-dba6-4ce8-80c0-1d1c8bea9116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485079667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3485079667
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3945715711
Short name T317
Test name
Test status
Simulation time 29890564 ps
CPU time 0.81 seconds
Started Feb 28 05:21:34 PM PST 24
Finished Feb 28 05:21:35 PM PST 24
Peak memory 195912 kb
Host smart-9b70a728-0f34-4acf-85c3-f8494c7dd35a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945715711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3945715711
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2999903104
Short name T297
Test name
Test status
Simulation time 37729614495 ps
CPU time 128.01 seconds
Started Feb 28 05:21:33 PM PST 24
Finished Feb 28 05:23:41 PM PST 24
Peak memory 198184 kb
Host smart-5499edcc-2444-4713-a6c0-e9e19b1742ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999903104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2999903104
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3921920876
Short name T37
Test name
Test status
Simulation time 15876086 ps
CPU time 0.62 seconds
Started Feb 28 05:21:36 PM PST 24
Finished Feb 28 05:21:36 PM PST 24
Peak memory 194036 kb
Host smart-4c4c8bc8-ab5c-4b5b-b1fa-b4c1f389004b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921920876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3921920876
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2582434851
Short name T531
Test name
Test status
Simulation time 166879157 ps
CPU time 0.61 seconds
Started Feb 28 05:21:37 PM PST 24
Finished Feb 28 05:21:37 PM PST 24
Peak memory 194588 kb
Host smart-22c67d05-0310-4486-b2b8-32be8871b547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582434851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2582434851
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1525791090
Short name T575
Test name
Test status
Simulation time 698284624 ps
CPU time 23.93 seconds
Started Feb 28 05:21:34 PM PST 24
Finished Feb 28 05:21:58 PM PST 24
Peak memory 195664 kb
Host smart-4702a644-5db1-4085-8dd1-c22661d8fbee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525791090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1525791090
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.4212284558
Short name T377
Test name
Test status
Simulation time 77105663 ps
CPU time 1.15 seconds
Started Feb 28 05:21:34 PM PST 24
Finished Feb 28 05:21:35 PM PST 24
Peak memory 196740 kb
Host smart-6d5c720a-aeac-4d51-a63f-ea5afdfad14b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212284558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.4212284558
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2305553971
Short name T674
Test name
Test status
Simulation time 28275929 ps
CPU time 0.95 seconds
Started Feb 28 05:21:35 PM PST 24
Finished Feb 28 05:21:36 PM PST 24
Peak memory 195876 kb
Host smart-289f1334-fce4-47e4-a450-bf2529927b5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305553971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2305553971
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3963302334
Short name T566
Test name
Test status
Simulation time 173738858 ps
CPU time 1.68 seconds
Started Feb 28 05:21:34 PM PST 24
Finished Feb 28 05:21:36 PM PST 24
Peak memory 198240 kb
Host smart-bc7db1fd-9dd5-4d55-83aa-7e40a1d9c57c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963302334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3963302334
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2560021252
Short name T334
Test name
Test status
Simulation time 175134738 ps
CPU time 3.16 seconds
Started Feb 28 05:21:34 PM PST 24
Finished Feb 28 05:21:38 PM PST 24
Peak memory 197328 kb
Host smart-acab353b-0cda-4529-88c1-546f0ef152a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560021252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2560021252
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.4159575043
Short name T380
Test name
Test status
Simulation time 41065136 ps
CPU time 0.89 seconds
Started Feb 28 05:21:32 PM PST 24
Finished Feb 28 05:21:33 PM PST 24
Peak memory 195840 kb
Host smart-b2abe39a-c46e-4541-8cf1-91df7220515c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159575043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.4159575043
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2746095350
Short name T148
Test name
Test status
Simulation time 25029373 ps
CPU time 1.03 seconds
Started Feb 28 05:21:36 PM PST 24
Finished Feb 28 05:21:37 PM PST 24
Peak memory 196704 kb
Host smart-fc935590-8a34-48e1-a715-118f764eb1dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746095350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2746095350
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3603050716
Short name T4
Test name
Test status
Simulation time 955723996 ps
CPU time 2.81 seconds
Started Feb 28 05:21:38 PM PST 24
Finished Feb 28 05:21:41 PM PST 24
Peak memory 198028 kb
Host smart-78ee1767-bf6c-4b3f-84b8-dba392621615
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603050716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3603050716
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2949577374
Short name T381
Test name
Test status
Simulation time 119570397 ps
CPU time 0.76 seconds
Started Feb 28 05:21:34 PM PST 24
Finished Feb 28 05:21:35 PM PST 24
Peak memory 194952 kb
Host smart-3d902584-0854-45ec-9afe-a65e4e391280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949577374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2949577374
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.438846493
Short name T345
Test name
Test status
Simulation time 68847480 ps
CPU time 1.35 seconds
Started Feb 28 05:21:37 PM PST 24
Finished Feb 28 05:21:38 PM PST 24
Peak memory 196580 kb
Host smart-6846bb11-90a7-4da8-8e2e-86fdfb22f17b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438846493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.438846493
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.769869877
Short name T561
Test name
Test status
Simulation time 25074730278 ps
CPU time 210.22 seconds
Started Feb 28 05:21:35 PM PST 24
Finished Feb 28 05:25:05 PM PST 24
Peak memory 198332 kb
Host smart-220e0f04-77b1-42ec-b0e8-acf0de0ea12b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769869877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.769869877
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3775056842
Short name T192
Test name
Test status
Simulation time 13990112 ps
CPU time 0.59 seconds
Started Feb 28 05:21:39 PM PST 24
Finished Feb 28 05:21:40 PM PST 24
Peak memory 194880 kb
Host smart-63cbc8f9-fbf6-4182-b732-2a0dfa57bc9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775056842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3775056842
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1212203768
Short name T230
Test name
Test status
Simulation time 32053316 ps
CPU time 0.74 seconds
Started Feb 28 05:21:39 PM PST 24
Finished Feb 28 05:21:40 PM PST 24
Peak memory 195324 kb
Host smart-d4efce30-9258-482a-b19a-f6ae3a7421af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212203768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1212203768
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2822846894
Short name T635
Test name
Test status
Simulation time 512964195 ps
CPU time 12.65 seconds
Started Feb 28 05:21:38 PM PST 24
Finished Feb 28 05:21:51 PM PST 24
Peak memory 197048 kb
Host smart-845e5da3-4894-4d79-8003-4c4473f4afd2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822846894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2822846894
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3369245480
Short name T213
Test name
Test status
Simulation time 246788534 ps
CPU time 0.91 seconds
Started Feb 28 05:21:40 PM PST 24
Finished Feb 28 05:21:41 PM PST 24
Peak memory 196252 kb
Host smart-3b3ee6df-ff7d-4288-94db-9d737ea32734
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369245480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3369245480
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2247688903
Short name T361
Test name
Test status
Simulation time 93994942 ps
CPU time 1.09 seconds
Started Feb 28 05:21:38 PM PST 24
Finished Feb 28 05:21:40 PM PST 24
Peak memory 195908 kb
Host smart-a7ee5b9f-9905-42fb-8d0f-68096f05a45a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247688903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2247688903
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1634255526
Short name T23
Test name
Test status
Simulation time 84356182 ps
CPU time 1.86 seconds
Started Feb 28 05:21:38 PM PST 24
Finished Feb 28 05:21:40 PM PST 24
Peak memory 198080 kb
Host smart-25184570-95c5-4ebe-b40f-c93f8df87024
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634255526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1634255526
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.910461900
Short name T255
Test name
Test status
Simulation time 222143956 ps
CPU time 1.98 seconds
Started Feb 28 05:21:40 PM PST 24
Finished Feb 28 05:21:42 PM PST 24
Peak memory 196328 kb
Host smart-e3f5f13a-d130-4dd6-b194-5e2dbe30a8d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910461900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
910461900
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.307133450
Short name T655
Test name
Test status
Simulation time 142381458 ps
CPU time 1 seconds
Started Feb 28 05:21:40 PM PST 24
Finished Feb 28 05:21:41 PM PST 24
Peak memory 196076 kb
Host smart-6911a893-9aa7-45a5-b872-36b47143c960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307133450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.307133450
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3258860695
Short name T11
Test name
Test status
Simulation time 19529451 ps
CPU time 0.71 seconds
Started Feb 28 05:21:41 PM PST 24
Finished Feb 28 05:21:42 PM PST 24
Peak memory 195040 kb
Host smart-9accc1c4-a7f0-4dd1-ac4a-4bd2e84d9473
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258860695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3258860695
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3757700942
Short name T445
Test name
Test status
Simulation time 960365873 ps
CPU time 2.76 seconds
Started Feb 28 05:21:37 PM PST 24
Finished Feb 28 05:21:40 PM PST 24
Peak memory 198032 kb
Host smart-a425198b-d920-4aa2-8741-af1bd471a727
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757700942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3757700942
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3373449213
Short name T438
Test name
Test status
Simulation time 114408219 ps
CPU time 1.32 seconds
Started Feb 28 05:21:38 PM PST 24
Finished Feb 28 05:21:39 PM PST 24
Peak memory 196588 kb
Host smart-7d2cff89-48ea-46c0-8673-2accc07f3e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373449213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3373449213
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.418535302
Short name T584
Test name
Test status
Simulation time 160817762 ps
CPU time 1.35 seconds
Started Feb 28 05:21:36 PM PST 24
Finished Feb 28 05:21:38 PM PST 24
Peak memory 196832 kb
Host smart-57274e07-f612-45c5-8d9b-b7cefce4c113
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418535302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.418535302
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1043629640
Short name T343
Test name
Test status
Simulation time 17253094006 ps
CPU time 141.54 seconds
Started Feb 28 05:21:38 PM PST 24
Finished Feb 28 05:23:59 PM PST 24
Peak memory 198212 kb
Host smart-d89a1cfd-43cc-4253-9eb3-512c8161af19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043629640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1043629640
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2931613900
Short name T467
Test name
Test status
Simulation time 34325415 ps
CPU time 0.6 seconds
Started Feb 28 05:21:44 PM PST 24
Finished Feb 28 05:21:44 PM PST 24
Peak memory 194156 kb
Host smart-3c95c114-d746-4160-8e96-91a9a535251e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931613900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2931613900
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3694507659
Short name T388
Test name
Test status
Simulation time 57152588 ps
CPU time 0.8 seconds
Started Feb 28 05:21:43 PM PST 24
Finished Feb 28 05:21:44 PM PST 24
Peak memory 196004 kb
Host smart-b0d78d25-ed14-4cce-bfc1-cf9330e941cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694507659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3694507659
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.4123773861
Short name T695
Test name
Test status
Simulation time 891336172 ps
CPU time 12.51 seconds
Started Feb 28 05:21:47 PM PST 24
Finished Feb 28 05:22:00 PM PST 24
Peak memory 197080 kb
Host smart-80621f34-885f-4260-825c-559a26cff5ba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123773861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.4123773861
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3934110204
Short name T338
Test name
Test status
Simulation time 166886863 ps
CPU time 1.18 seconds
Started Feb 28 05:21:44 PM PST 24
Finished Feb 28 05:21:45 PM PST 24
Peak memory 196704 kb
Host smart-84c09ace-9989-4cf9-b146-b7bedb096875
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934110204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3934110204
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2361220303
Short name T130
Test name
Test status
Simulation time 66681981 ps
CPU time 1.13 seconds
Started Feb 28 05:21:45 PM PST 24
Finished Feb 28 05:21:47 PM PST 24
Peak memory 196056 kb
Host smart-35e88508-949a-4c13-b601-77fff9128e71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361220303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2361220303
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1071885792
Short name T132
Test name
Test status
Simulation time 217479421 ps
CPU time 4.31 seconds
Started Feb 28 05:21:42 PM PST 24
Finished Feb 28 05:21:47 PM PST 24
Peak memory 198160 kb
Host smart-7db31c43-5c33-4503-9bc9-8fff5bdad6ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071885792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1071885792
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.4274766259
Short name T546
Test name
Test status
Simulation time 206652205 ps
CPU time 2.7 seconds
Started Feb 28 05:21:44 PM PST 24
Finished Feb 28 05:21:47 PM PST 24
Peak memory 198160 kb
Host smart-3b2fb59c-c1a8-4808-9cf0-6aebce948973
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274766259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.4274766259
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.4072055704
Short name T108
Test name
Test status
Simulation time 98917030 ps
CPU time 0.81 seconds
Started Feb 28 05:21:41 PM PST 24
Finished Feb 28 05:21:42 PM PST 24
Peak memory 195560 kb
Host smart-5db3eca4-3654-4fbd-bbd4-7b74fe811295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072055704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.4072055704
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.497554383
Short name T421
Test name
Test status
Simulation time 65390786 ps
CPU time 0.99 seconds
Started Feb 28 05:21:42 PM PST 24
Finished Feb 28 05:21:43 PM PST 24
Peak memory 196712 kb
Host smart-c6b4b11f-1a8e-472e-8cca-e03634e73a4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497554383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.497554383
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.927358023
Short name T450
Test name
Test status
Simulation time 340721276 ps
CPU time 4.22 seconds
Started Feb 28 05:21:45 PM PST 24
Finished Feb 28 05:21:49 PM PST 24
Peak memory 198196 kb
Host smart-41f7ca2b-94ae-41ff-b8b8-6c98227f07d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927358023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran
dom_long_reg_writes_reg_reads.927358023
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.1335689085
Short name T486
Test name
Test status
Simulation time 117456883 ps
CPU time 0.87 seconds
Started Feb 28 05:21:40 PM PST 24
Finished Feb 28 05:21:41 PM PST 24
Peak memory 195416 kb
Host smart-4e812294-225b-4694-aa1c-498c646c13b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335689085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.1335689085
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2249832652
Short name T176
Test name
Test status
Simulation time 126006161 ps
CPU time 1.21 seconds
Started Feb 28 05:21:39 PM PST 24
Finished Feb 28 05:21:41 PM PST 24
Peak memory 196320 kb
Host smart-63711693-522c-4a85-954c-de671455f80b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249832652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2249832652
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3969028179
Short name T412
Test name
Test status
Simulation time 56394519235 ps
CPU time 200.21 seconds
Started Feb 28 05:21:45 PM PST 24
Finished Feb 28 05:25:06 PM PST 24
Peak memory 198208 kb
Host smart-32fdc9c3-0ba7-4988-a93b-5cabe74c4521
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969028179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3969028179
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.1947786701
Short name T652
Test name
Test status
Simulation time 24040632891 ps
CPU time 277.64 seconds
Started Feb 28 05:21:46 PM PST 24
Finished Feb 28 05:26:24 PM PST 24
Peak memory 198300 kb
Host smart-b0a39ae2-b008-47cc-a4cd-7828285c1f52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1947786701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.1947786701
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3465124491
Short name T631
Test name
Test status
Simulation time 14228506 ps
CPU time 0.58 seconds
Started Feb 28 05:21:47 PM PST 24
Finished Feb 28 05:21:47 PM PST 24
Peak memory 194100 kb
Host smart-5f502b6a-ec76-4e35-9288-2d3d1d366517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465124491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3465124491
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3680748745
Short name T384
Test name
Test status
Simulation time 146794396 ps
CPU time 0.9 seconds
Started Feb 28 05:21:46 PM PST 24
Finished Feb 28 05:21:47 PM PST 24
Peak memory 197392 kb
Host smart-7fce4a2e-5827-4bb7-b7ba-1d10383da49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680748745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3680748745
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2802787640
Short name T124
Test name
Test status
Simulation time 2016399598 ps
CPU time 11.44 seconds
Started Feb 28 05:21:46 PM PST 24
Finished Feb 28 05:21:58 PM PST 24
Peak memory 197104 kb
Host smart-1f359e72-08d9-452a-81bb-5d2f3ce0abab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802787640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2802787640
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2182323618
Short name T283
Test name
Test status
Simulation time 68518481 ps
CPU time 1.06 seconds
Started Feb 28 05:21:45 PM PST 24
Finished Feb 28 05:21:46 PM PST 24
Peak memory 196476 kb
Host smart-293ce810-ba50-417a-8eba-31cca0641fa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182323618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2182323618
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1992899370
Short name T429
Test name
Test status
Simulation time 197208232 ps
CPU time 1.1 seconds
Started Feb 28 05:21:45 PM PST 24
Finished Feb 28 05:21:47 PM PST 24
Peak memory 196636 kb
Host smart-88286e7c-4d95-489d-b9a3-1af6615d1e11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992899370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1992899370
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.734144224
Short name T692
Test name
Test status
Simulation time 379227576 ps
CPU time 2.77 seconds
Started Feb 28 05:21:45 PM PST 24
Finished Feb 28 05:21:48 PM PST 24
Peak memory 198220 kb
Host smart-c7860d51-a097-410a-a7a5-d341febd87dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734144224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.734144224
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1043881098
Short name T322
Test name
Test status
Simulation time 78202099 ps
CPU time 2.76 seconds
Started Feb 28 05:21:47 PM PST 24
Finished Feb 28 05:21:50 PM PST 24
Peak memory 197052 kb
Host smart-75ef2747-1a04-4719-a3bb-76ea5b4d2eab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043881098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1043881098
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3565948104
Short name T457
Test name
Test status
Simulation time 105169541 ps
CPU time 0.84 seconds
Started Feb 28 05:21:45 PM PST 24
Finished Feb 28 05:21:46 PM PST 24
Peak memory 196432 kb
Host smart-dda76b6f-a5a5-438b-8f6b-71cc55de7db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565948104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3565948104
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3165241519
Short name T240
Test name
Test status
Simulation time 305354586 ps
CPU time 1.06 seconds
Started Feb 28 05:21:48 PM PST 24
Finished Feb 28 05:21:49 PM PST 24
Peak memory 196796 kb
Host smart-4bd67712-4398-4446-abc6-3a871732af39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165241519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3165241519
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3244814427
Short name T603
Test name
Test status
Simulation time 357805857 ps
CPU time 3.69 seconds
Started Feb 28 05:21:45 PM PST 24
Finished Feb 28 05:21:49 PM PST 24
Peak memory 198068 kb
Host smart-3a14b7b0-d7c3-4d8c-8e75-0400d86fe640
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244814427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3244814427
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2040262884
Short name T264
Test name
Test status
Simulation time 67526544 ps
CPU time 0.97 seconds
Started Feb 28 05:21:44 PM PST 24
Finished Feb 28 05:21:45 PM PST 24
Peak memory 195616 kb
Host smart-054e0370-3531-4dc9-926a-dc4887b8d572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040262884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2040262884
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2073341885
Short name T204
Test name
Test status
Simulation time 63348425 ps
CPU time 1.27 seconds
Started Feb 28 05:21:42 PM PST 24
Finished Feb 28 05:21:44 PM PST 24
Peak memory 195548 kb
Host smart-a971e3bc-369c-4a43-9f0c-62dbbe8a4a65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073341885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2073341885
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.884658806
Short name T552
Test name
Test status
Simulation time 33667812371 ps
CPU time 215.44 seconds
Started Feb 28 05:21:47 PM PST 24
Finished Feb 28 05:25:23 PM PST 24
Peak memory 198224 kb
Host smart-64ff3b0d-bf83-4f2b-bcbe-5cbf40cec702
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884658806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.884658806
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4001781709
Short name T497
Test name
Test status
Simulation time 39518772 ps
CPU time 0.58 seconds
Started Feb 28 05:21:50 PM PST 24
Finished Feb 28 05:21:51 PM PST 24
Peak memory 194680 kb
Host smart-94777d5d-1cc7-4044-9539-a758942be7bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001781709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4001781709
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1963650613
Short name T667
Test name
Test status
Simulation time 29807547 ps
CPU time 0.76 seconds
Started Feb 28 05:21:48 PM PST 24
Finished Feb 28 05:21:50 PM PST 24
Peak memory 195336 kb
Host smart-08e15d52-3850-4987-b10e-0f6f92e61786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963650613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1963650613
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3346688849
Short name T567
Test name
Test status
Simulation time 120354664 ps
CPU time 3.76 seconds
Started Feb 28 05:21:53 PM PST 24
Finished Feb 28 05:21:57 PM PST 24
Peak memory 195992 kb
Host smart-7d32faae-beff-479b-a57a-60bd387cfcd9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346688849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3346688849
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2950184927
Short name T313
Test name
Test status
Simulation time 117530430 ps
CPU time 0.69 seconds
Started Feb 28 05:21:50 PM PST 24
Finished Feb 28 05:21:51 PM PST 24
Peak memory 194688 kb
Host smart-a69eaab1-068f-475d-aeac-7d91e75c4404
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950184927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2950184927
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2315937996
Short name T660
Test name
Test status
Simulation time 25916992 ps
CPU time 0.71 seconds
Started Feb 28 05:21:52 PM PST 24
Finished Feb 28 05:21:53 PM PST 24
Peak memory 194432 kb
Host smart-ec8c2324-9062-4a25-93e3-fd85b00e6f03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315937996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2315937996
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.481079148
Short name T17
Test name
Test status
Simulation time 94604628 ps
CPU time 3.74 seconds
Started Feb 28 05:21:51 PM PST 24
Finished Feb 28 05:21:55 PM PST 24
Peak memory 198232 kb
Host smart-8fcbb59b-4670-4d19-976c-75139e9a4eef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481079148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.481079148
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2768098730
Short name T311
Test name
Test status
Simulation time 127424565 ps
CPU time 4.02 seconds
Started Feb 28 05:21:49 PM PST 24
Finished Feb 28 05:21:54 PM PST 24
Peak memory 196644 kb
Host smart-c23c7bd5-6755-45d5-bfe9-6911b943f415
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768098730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2768098730
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3815723810
Short name T594
Test name
Test status
Simulation time 97430305 ps
CPU time 1.24 seconds
Started Feb 28 05:21:50 PM PST 24
Finished Feb 28 05:21:52 PM PST 24
Peak memory 195968 kb
Host smart-b5a17baa-51a1-441c-859c-c7c67aa11e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815723810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3815723810
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2465132881
Short name T364
Test name
Test status
Simulation time 16557229 ps
CPU time 0.67 seconds
Started Feb 28 05:21:48 PM PST 24
Finished Feb 28 05:21:50 PM PST 24
Peak memory 194356 kb
Host smart-5fa91df1-b04b-4544-80c4-6057e1b6c8d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465132881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2465132881
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1186413128
Short name T103
Test name
Test status
Simulation time 160249426 ps
CPU time 2.11 seconds
Started Feb 28 05:21:48 PM PST 24
Finished Feb 28 05:21:50 PM PST 24
Peak memory 198116 kb
Host smart-6613b0c8-b5f4-4535-a222-648e8d5f8c6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186413128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1186413128
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.452683181
Short name T350
Test name
Test status
Simulation time 70681827 ps
CPU time 1.09 seconds
Started Feb 28 05:21:47 PM PST 24
Finished Feb 28 05:21:48 PM PST 24
Peak memory 195668 kb
Host smart-33abb2bd-bd51-4f9f-8be3-c001ecbd1c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452683181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.452683181
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3602814175
Short name T121
Test name
Test status
Simulation time 173981370 ps
CPU time 1.33 seconds
Started Feb 28 05:21:47 PM PST 24
Finished Feb 28 05:21:49 PM PST 24
Peak memory 196828 kb
Host smart-da5410ba-8f12-49cb-9ecb-bcfbfa0d8687
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602814175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3602814175
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2755021981
Short name T417
Test name
Test status
Simulation time 21305493436 ps
CPU time 274.39 seconds
Started Feb 28 05:21:51 PM PST 24
Finished Feb 28 05:26:26 PM PST 24
Peak memory 198260 kb
Host smart-f54ae42f-202f-4553-b339-c9ea97c523bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755021981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2755021981
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.3364379698
Short name T562
Test name
Test status
Simulation time 27124434789 ps
CPU time 390.69 seconds
Started Feb 28 05:21:49 PM PST 24
Finished Feb 28 05:28:21 PM PST 24
Peak memory 198276 kb
Host smart-600b2a38-066f-4e64-aabd-1809211ad9b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3364379698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.3364379698
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.17529086
Short name T643
Test name
Test status
Simulation time 62791188 ps
CPU time 0.61 seconds
Started Feb 28 05:21:56 PM PST 24
Finished Feb 28 05:21:57 PM PST 24
Peak memory 193968 kb
Host smart-9742ab42-23cb-48c0-aaf2-ca405f93f7c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17529086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.17529086
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1241759270
Short name T170
Test name
Test status
Simulation time 136497813 ps
CPU time 0.97 seconds
Started Feb 28 05:21:55 PM PST 24
Finished Feb 28 05:21:56 PM PST 24
Peak memory 196516 kb
Host smart-836c618a-a91c-445b-8646-2854fd937a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241759270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1241759270
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3323040042
Short name T449
Test name
Test status
Simulation time 243205897 ps
CPU time 8.23 seconds
Started Feb 28 05:21:54 PM PST 24
Finished Feb 28 05:22:03 PM PST 24
Peak memory 198108 kb
Host smart-32bf56d0-79c6-4965-bb02-16e597116d51
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323040042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3323040042
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.4271885289
Short name T273
Test name
Test status
Simulation time 220386515 ps
CPU time 1.02 seconds
Started Feb 28 05:21:53 PM PST 24
Finished Feb 28 05:21:55 PM PST 24
Peak memory 197332 kb
Host smart-b4a54b59-b796-4854-b08c-af7dad0be921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271885289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.4271885289
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2741089119
Short name T203
Test name
Test status
Simulation time 290622094 ps
CPU time 1.25 seconds
Started Feb 28 05:21:55 PM PST 24
Finished Feb 28 05:21:56 PM PST 24
Peak memory 196976 kb
Host smart-e55ac58a-5270-4d3b-ab8f-1030bcbe5d45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741089119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2741089119
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.872101013
Short name T238
Test name
Test status
Simulation time 49195811 ps
CPU time 1.92 seconds
Started Feb 28 05:21:55 PM PST 24
Finished Feb 28 05:21:57 PM PST 24
Peak memory 198256 kb
Host smart-b1f4c035-74c0-4966-9f70-94cb506ed102
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872101013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.872101013
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3069835090
Short name T463
Test name
Test status
Simulation time 456901065 ps
CPU time 2.67 seconds
Started Feb 28 05:21:55 PM PST 24
Finished Feb 28 05:21:58 PM PST 24
Peak memory 195972 kb
Host smart-6c62848b-c144-4280-84d3-8b202d1ef7d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069835090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3069835090
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2877529864
Short name T285
Test name
Test status
Simulation time 172998454 ps
CPU time 1.21 seconds
Started Feb 28 05:21:52 PM PST 24
Finished Feb 28 05:21:53 PM PST 24
Peak memory 196604 kb
Host smart-05583464-e15c-466e-8a94-8861194c7b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877529864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2877529864
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3711931364
Short name T376
Test name
Test status
Simulation time 40959229 ps
CPU time 1.12 seconds
Started Feb 28 05:21:55 PM PST 24
Finished Feb 28 05:21:56 PM PST 24
Peak memory 196056 kb
Host smart-f03c824a-a0ee-40c4-abd7-cef056d14828
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711931364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3711931364
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.983942117
Short name T265
Test name
Test status
Simulation time 27792054 ps
CPU time 1.31 seconds
Started Feb 28 05:21:55 PM PST 24
Finished Feb 28 05:21:56 PM PST 24
Peak memory 198084 kb
Host smart-9ca21599-f00a-4928-a0d1-d91935292c2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983942117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.983942117
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.433683794
Short name T58
Test name
Test status
Simulation time 102904959 ps
CPU time 1 seconds
Started Feb 28 05:21:56 PM PST 24
Finished Feb 28 05:21:57 PM PST 24
Peak memory 195724 kb
Host smart-d8559a25-0793-4184-9025-3d498f7dfc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433683794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.433683794
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1902644486
Short name T252
Test name
Test status
Simulation time 93414304 ps
CPU time 1.32 seconds
Started Feb 28 05:21:53 PM PST 24
Finished Feb 28 05:21:55 PM PST 24
Peak memory 198096 kb
Host smart-b28119f1-2d56-4cbf-bba3-1f1950bb66d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902644486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1902644486
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1236978972
Short name T428
Test name
Test status
Simulation time 3142683209 ps
CPU time 82.81 seconds
Started Feb 28 05:21:56 PM PST 24
Finished Feb 28 05:23:19 PM PST 24
Peak memory 198260 kb
Host smart-7cd4ee0b-7b5a-48ab-882d-568205d947f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236978972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1236978972
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.63941080
Short name T57
Test name
Test status
Simulation time 273347784727 ps
CPU time 1939.26 seconds
Started Feb 28 05:21:56 PM PST 24
Finished Feb 28 05:54:15 PM PST 24
Peak memory 198328 kb
Host smart-0076a26f-0e63-4fd5-8525-c19034d4b280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=63941080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.63941080
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2021398389
Short name T212
Test name
Test status
Simulation time 10899432 ps
CPU time 0.58 seconds
Started Feb 28 05:21:58 PM PST 24
Finished Feb 28 05:21:59 PM PST 24
Peak memory 193928 kb
Host smart-628d1514-ecdc-47c8-ac24-73fd75d2424e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021398389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2021398389
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2830369899
Short name T190
Test name
Test status
Simulation time 430011991 ps
CPU time 0.9 seconds
Started Feb 28 05:21:56 PM PST 24
Finished Feb 28 05:21:57 PM PST 24
Peak memory 196000 kb
Host smart-97c54055-8572-4d08-b9c9-9332e4457668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830369899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2830369899
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2338454250
Short name T647
Test name
Test status
Simulation time 1234738284 ps
CPU time 21.24 seconds
Started Feb 28 05:21:58 PM PST 24
Finished Feb 28 05:22:20 PM PST 24
Peak memory 196948 kb
Host smart-931923f4-c001-43a5-893d-9fe52b66f094
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338454250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2338454250
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2862324323
Short name T241
Test name
Test status
Simulation time 62333178 ps
CPU time 0.84 seconds
Started Feb 28 05:22:00 PM PST 24
Finished Feb 28 05:22:02 PM PST 24
Peak memory 195944 kb
Host smart-6b55b513-ac21-4e2e-91dc-2e07ca00448b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862324323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2862324323
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3603885504
Short name T512
Test name
Test status
Simulation time 794020969 ps
CPU time 1.17 seconds
Started Feb 28 05:22:00 PM PST 24
Finished Feb 28 05:22:01 PM PST 24
Peak memory 195828 kb
Host smart-2fba2253-2114-41be-a337-35b91ecea74b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603885504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3603885504
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.4151999888
Short name T152
Test name
Test status
Simulation time 376051024 ps
CPU time 3.67 seconds
Started Feb 28 05:22:01 PM PST 24
Finished Feb 28 05:22:05 PM PST 24
Peak memory 198132 kb
Host smart-a7a6e993-b075-408a-b501-98a9364e64d5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151999888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.4151999888
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1494329740
Short name T464
Test name
Test status
Simulation time 278600904 ps
CPU time 3.41 seconds
Started Feb 28 05:21:57 PM PST 24
Finished Feb 28 05:22:00 PM PST 24
Peak memory 198160 kb
Host smart-9bb026c6-6731-4e81-9169-5d2dd4a3a523
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494329740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1494329740
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2099717716
Short name T555
Test name
Test status
Simulation time 41980690 ps
CPU time 1.01 seconds
Started Feb 28 05:21:59 PM PST 24
Finished Feb 28 05:22:00 PM PST 24
Peak memory 196816 kb
Host smart-50842a1b-ff56-494d-823f-32fba6891f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099717716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2099717716
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2708361962
Short name T365
Test name
Test status
Simulation time 51008810 ps
CPU time 1.35 seconds
Started Feb 28 05:21:58 PM PST 24
Finished Feb 28 05:22:00 PM PST 24
Peak memory 196980 kb
Host smart-8f41048a-7a60-44ca-9657-43698aa4f68f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708361962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2708361962
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.97679275
Short name T5
Test name
Test status
Simulation time 1070233756 ps
CPU time 4.42 seconds
Started Feb 28 05:21:59 PM PST 24
Finished Feb 28 05:22:04 PM PST 24
Peak memory 198108 kb
Host smart-99cd7922-3fdc-470d-a20d-7377c8d4a130
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97679275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand
om_long_reg_writes_reg_reads.97679275
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2992419028
Short name T189
Test name
Test status
Simulation time 262643095 ps
CPU time 1.22 seconds
Started Feb 28 05:21:55 PM PST 24
Finished Feb 28 05:21:57 PM PST 24
Peak memory 195636 kb
Host smart-8a3b664b-c28c-458a-b7d6-395a95b94d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992419028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2992419028
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1339432040
Short name T179
Test name
Test status
Simulation time 57253745 ps
CPU time 0.92 seconds
Started Feb 28 05:21:55 PM PST 24
Finished Feb 28 05:21:56 PM PST 24
Peak memory 195796 kb
Host smart-008813d0-b7cf-4c05-b641-1bcce9a995e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339432040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1339432040
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1120016661
Short name T282
Test name
Test status
Simulation time 7492718086 ps
CPU time 122.8 seconds
Started Feb 28 05:22:01 PM PST 24
Finished Feb 28 05:24:04 PM PST 24
Peak memory 198252 kb
Host smart-e0f48330-9ebf-4ade-a42e-ec1ca1fecd5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120016661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1120016661
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1374981149
Short name T446
Test name
Test status
Simulation time 58727157639 ps
CPU time 982.57 seconds
Started Feb 28 05:22:00 PM PST 24
Finished Feb 28 05:38:23 PM PST 24
Peak memory 198352 kb
Host smart-6483f652-0e38-42f7-ba52-607fadc77785
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1374981149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1374981149
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2730084975
Short name T318
Test name
Test status
Simulation time 43095811 ps
CPU time 0.58 seconds
Started Feb 28 05:22:08 PM PST 24
Finished Feb 28 05:22:09 PM PST 24
Peak memory 193952 kb
Host smart-80c6e014-1872-4ec9-a95a-288e311c5a7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730084975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2730084975
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.772570675
Short name T206
Test name
Test status
Simulation time 82296155 ps
CPU time 0.82 seconds
Started Feb 28 05:22:02 PM PST 24
Finished Feb 28 05:22:03 PM PST 24
Peak memory 196112 kb
Host smart-7154cd4f-5df9-4fdb-b754-ae6b537afa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772570675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.772570675
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3781055514
Short name T465
Test name
Test status
Simulation time 603223114 ps
CPU time 20.47 seconds
Started Feb 28 05:22:02 PM PST 24
Finished Feb 28 05:22:23 PM PST 24
Peak memory 196580 kb
Host smart-eaaf7f39-4628-4c74-9acd-3727a36603a9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781055514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3781055514
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2414764695
Short name T689
Test name
Test status
Simulation time 463440497 ps
CPU time 1.09 seconds
Started Feb 28 05:22:07 PM PST 24
Finished Feb 28 05:22:09 PM PST 24
Peak memory 196580 kb
Host smart-ec6230cb-afb6-41cf-8464-3665c8bcfb14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414764695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2414764695
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2616701781
Short name T564
Test name
Test status
Simulation time 153748163 ps
CPU time 0.86 seconds
Started Feb 28 05:22:01 PM PST 24
Finished Feb 28 05:22:02 PM PST 24
Peak memory 195636 kb
Host smart-c8fe6c50-6638-46d0-85bc-826c1a27ad22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616701781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2616701781
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.676998753
Short name T691
Test name
Test status
Simulation time 74310267 ps
CPU time 3.19 seconds
Started Feb 28 05:22:01 PM PST 24
Finished Feb 28 05:22:04 PM PST 24
Peak memory 196504 kb
Host smart-4116dda0-2b58-4a47-a13a-4d9328517056
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676998753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.676998753
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1448179241
Short name T592
Test name
Test status
Simulation time 115276651 ps
CPU time 3.49 seconds
Started Feb 28 05:22:04 PM PST 24
Finished Feb 28 05:22:08 PM PST 24
Peak memory 196864 kb
Host smart-bd2fb159-3a51-44f8-9301-690ac436876b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448179241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1448179241
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2795648746
Short name T186
Test name
Test status
Simulation time 466806142 ps
CPU time 1.14 seconds
Started Feb 28 05:22:00 PM PST 24
Finished Feb 28 05:22:02 PM PST 24
Peak memory 196748 kb
Host smart-d848a3f7-5983-4970-a477-d03dd502720f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795648746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2795648746
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.611809534
Short name T159
Test name
Test status
Simulation time 76372824 ps
CPU time 0.83 seconds
Started Feb 28 05:22:09 PM PST 24
Finished Feb 28 05:22:10 PM PST 24
Peak memory 195612 kb
Host smart-9dfc441e-ec2b-4208-83d6-535c5a3414f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611809534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.611809534
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1316102163
Short name T372
Test name
Test status
Simulation time 163702150 ps
CPU time 2.9 seconds
Started Feb 28 05:22:09 PM PST 24
Finished Feb 28 05:22:12 PM PST 24
Peak memory 198116 kb
Host smart-ac468c19-0d53-4bbf-b48e-ac30829db327
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316102163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1316102163
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2061079581
Short name T168
Test name
Test status
Simulation time 180453234 ps
CPU time 1.22 seconds
Started Feb 28 05:21:56 PM PST 24
Finished Feb 28 05:21:58 PM PST 24
Peak memory 195772 kb
Host smart-ce01d817-b6a8-411d-926e-8d193496bf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061079581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2061079581
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1602149605
Short name T573
Test name
Test status
Simulation time 40669762 ps
CPU time 1.12 seconds
Started Feb 28 05:22:03 PM PST 24
Finished Feb 28 05:22:04 PM PST 24
Peak memory 195620 kb
Host smart-b4582dfa-fdda-46af-894d-c2be366641f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602149605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1602149605
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2684141764
Short name T623
Test name
Test status
Simulation time 32368117284 ps
CPU time 81.43 seconds
Started Feb 28 05:22:08 PM PST 24
Finished Feb 28 05:23:29 PM PST 24
Peak memory 198232 kb
Host smart-ae1804b4-a39b-4870-b901-9d368a2892c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684141764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2684141764
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.533828010
Short name T455
Test name
Test status
Simulation time 39081339011 ps
CPU time 544.46 seconds
Started Feb 28 05:22:06 PM PST 24
Finished Feb 28 05:31:11 PM PST 24
Peak memory 198360 kb
Host smart-8e249542-7423-419f-b1bf-dd175e07dbec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=533828010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.533828010
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1754135874
Short name T408
Test name
Test status
Simulation time 22561886 ps
CPU time 0.59 seconds
Started Feb 28 05:19:54 PM PST 24
Finished Feb 28 05:19:55 PM PST 24
Peak memory 194144 kb
Host smart-f8728bd0-d9aa-40f3-89f8-c04150e931ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754135874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1754135874
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3714806768
Short name T540
Test name
Test status
Simulation time 30879720 ps
CPU time 0.7 seconds
Started Feb 28 05:19:52 PM PST 24
Finished Feb 28 05:19:52 PM PST 24
Peak memory 194228 kb
Host smart-6d1e2225-2ef5-43ca-a421-01fd1c7c284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714806768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3714806768
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3334503678
Short name T346
Test name
Test status
Simulation time 200136385 ps
CPU time 6.92 seconds
Started Feb 28 05:19:51 PM PST 24
Finished Feb 28 05:19:58 PM PST 24
Peak memory 198112 kb
Host smart-8122c2f1-8bdf-41c8-bc98-7e11b5209e11
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334503678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3334503678
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.911300531
Short name T441
Test name
Test status
Simulation time 200687243 ps
CPU time 0.87 seconds
Started Feb 28 05:19:55 PM PST 24
Finished Feb 28 05:19:56 PM PST 24
Peak memory 196840 kb
Host smart-a1a5aed8-8fc1-492d-8622-31f2fd5fad79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911300531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.911300531
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2902668082
Short name T588
Test name
Test status
Simulation time 209843547 ps
CPU time 0.75 seconds
Started Feb 28 05:19:51 PM PST 24
Finished Feb 28 05:19:52 PM PST 24
Peak memory 195164 kb
Host smart-e8f5769c-e64a-4aa0-aab2-0d69758177f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902668082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2902668082
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3583365156
Short name T636
Test name
Test status
Simulation time 285598945 ps
CPU time 3.1 seconds
Started Feb 28 05:19:54 PM PST 24
Finished Feb 28 05:19:57 PM PST 24
Peak memory 198188 kb
Host smart-ebbb2ea5-c314-4d96-b030-99ceb6ed7750
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583365156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3583365156
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2529824808
Short name T477
Test name
Test status
Simulation time 258023502 ps
CPU time 2.85 seconds
Started Feb 28 05:19:55 PM PST 24
Finished Feb 28 05:19:58 PM PST 24
Peak memory 197284 kb
Host smart-8eeabc61-7187-4a93-b341-13a338bf75a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529824808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2529824808
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2716000239
Short name T284
Test name
Test status
Simulation time 19299870 ps
CPU time 0.89 seconds
Started Feb 28 05:19:55 PM PST 24
Finished Feb 28 05:19:56 PM PST 24
Peak memory 196732 kb
Host smart-110ad421-d617-476c-abae-024d02ccaa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716000239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2716000239
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.544330943
Short name T489
Test name
Test status
Simulation time 143864480 ps
CPU time 1.3 seconds
Started Feb 28 05:19:52 PM PST 24
Finished Feb 28 05:19:53 PM PST 24
Peak memory 198088 kb
Host smart-3441e108-f120-472f-a939-d1e52fd863d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544330943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.544330943
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2529618894
Short name T609
Test name
Test status
Simulation time 486847648 ps
CPU time 7.31 seconds
Started Feb 28 05:19:50 PM PST 24
Finished Feb 28 05:19:58 PM PST 24
Peak memory 198132 kb
Host smart-cfdf9076-8cb1-43c2-bf4c-ba719f95e92b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529618894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2529618894
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3118281596
Short name T42
Test name
Test status
Simulation time 93032327 ps
CPU time 0.86 seconds
Started Feb 28 05:19:56 PM PST 24
Finished Feb 28 05:19:57 PM PST 24
Peak memory 213840 kb
Host smart-a43674de-e191-4e69-91f4-7564b84afe04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118281596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3118281596
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2866399978
Short name T253
Test name
Test status
Simulation time 45326507 ps
CPU time 1.02 seconds
Started Feb 28 05:19:53 PM PST 24
Finished Feb 28 05:19:54 PM PST 24
Peak memory 196556 kb
Host smart-f90f0ec3-2c9e-42bd-8c77-be33d6fd5ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866399978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2866399978
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.480469547
Short name T633
Test name
Test status
Simulation time 436545291 ps
CPU time 1.44 seconds
Started Feb 28 05:19:52 PM PST 24
Finished Feb 28 05:19:53 PM PST 24
Peak memory 195856 kb
Host smart-d33e0d88-ac41-4dcc-9c06-d3aab2aee6e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480469547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.480469547
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.153173379
Short name T8
Test name
Test status
Simulation time 17249926427 ps
CPU time 185.12 seconds
Started Feb 28 05:19:56 PM PST 24
Finished Feb 28 05:23:01 PM PST 24
Peak memory 198224 kb
Host smart-89f19a0f-1522-491b-a1bb-ab3c2c7adfe6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153173379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.153173379
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3362588902
Short name T544
Test name
Test status
Simulation time 28783574 ps
CPU time 0.57 seconds
Started Feb 28 05:22:08 PM PST 24
Finished Feb 28 05:22:09 PM PST 24
Peak memory 193960 kb
Host smart-49525cd6-4e66-4ced-a6d3-dec60c235941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362588902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3362588902
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.68531992
Short name T22
Test name
Test status
Simulation time 16936313 ps
CPU time 0.64 seconds
Started Feb 28 05:22:11 PM PST 24
Finished Feb 28 05:22:12 PM PST 24
Peak memory 194016 kb
Host smart-fcf6891a-5677-456b-97ab-8a9e2450ffd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68531992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.68531992
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1380505333
Short name T65
Test name
Test status
Simulation time 355518083 ps
CPU time 19.18 seconds
Started Feb 28 05:22:08 PM PST 24
Finished Feb 28 05:22:28 PM PST 24
Peak memory 196004 kb
Host smart-738b135b-8c15-48c3-b5e0-14cc8afa582e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380505333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1380505333
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.1207403442
Short name T202
Test name
Test status
Simulation time 36266605 ps
CPU time 0.61 seconds
Started Feb 28 05:22:06 PM PST 24
Finished Feb 28 05:22:07 PM PST 24
Peak memory 194440 kb
Host smart-8684c6ab-a422-4884-bd98-f99e58e53c47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207403442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.1207403442
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2989975481
Short name T219
Test name
Test status
Simulation time 34926197 ps
CPU time 0.84 seconds
Started Feb 28 05:22:08 PM PST 24
Finished Feb 28 05:22:09 PM PST 24
Peak memory 195556 kb
Host smart-140b1b0c-bbba-4840-819a-70f9aee76036
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989975481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2989975481
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3319707839
Short name T263
Test name
Test status
Simulation time 271691136 ps
CPU time 2.93 seconds
Started Feb 28 05:22:08 PM PST 24
Finished Feb 28 05:22:12 PM PST 24
Peak memory 198228 kb
Host smart-605bc524-a6fb-4bac-ae22-acb40b64dbd8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319707839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3319707839
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3616485223
Short name T122
Test name
Test status
Simulation time 564171593 ps
CPU time 2.48 seconds
Started Feb 28 05:22:09 PM PST 24
Finished Feb 28 05:22:12 PM PST 24
Peak memory 196964 kb
Host smart-01a082c5-56e2-417d-a658-e0fe96ead362
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616485223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3616485223
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.490945239
Short name T483
Test name
Test status
Simulation time 21214274 ps
CPU time 0.89 seconds
Started Feb 28 05:22:07 PM PST 24
Finished Feb 28 05:22:08 PM PST 24
Peak memory 196188 kb
Host smart-7395e307-f7ab-4932-8e20-950fcc7d898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490945239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.490945239
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2569845681
Short name T482
Test name
Test status
Simulation time 31025165 ps
CPU time 1.17 seconds
Started Feb 28 05:22:07 PM PST 24
Finished Feb 28 05:22:08 PM PST 24
Peak memory 196632 kb
Host smart-89d39853-b3dc-406c-be0c-cc802bee9a3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569845681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2569845681
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3665997111
Short name T420
Test name
Test status
Simulation time 170019113 ps
CPU time 3.05 seconds
Started Feb 28 05:22:07 PM PST 24
Finished Feb 28 05:22:11 PM PST 24
Peak memory 198092 kb
Host smart-80825bbb-2d6e-4008-9a48-f49a59f08b6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665997111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3665997111
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2503454291
Short name T590
Test name
Test status
Simulation time 44370698 ps
CPU time 0.95 seconds
Started Feb 28 05:22:09 PM PST 24
Finished Feb 28 05:22:10 PM PST 24
Peak memory 196316 kb
Host smart-62ad864c-c083-422d-9a7e-1988481e5beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503454291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2503454291
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3680902006
Short name T276
Test name
Test status
Simulation time 184560990 ps
CPU time 1.05 seconds
Started Feb 28 05:22:06 PM PST 24
Finished Feb 28 05:22:07 PM PST 24
Peak memory 195516 kb
Host smart-4d88475e-e171-4c72-a394-e2f55b54a9d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680902006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3680902006
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2394439109
Short name T521
Test name
Test status
Simulation time 5859200171 ps
CPU time 163.3 seconds
Started Feb 28 05:22:08 PM PST 24
Finished Feb 28 05:24:51 PM PST 24
Peak memory 198248 kb
Host smart-da15d7f3-25d8-4347-a032-7390d5428c76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394439109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2394439109
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.82550616
Short name T278
Test name
Test status
Simulation time 22564337 ps
CPU time 0.6 seconds
Started Feb 28 05:22:10 PM PST 24
Finished Feb 28 05:22:11 PM PST 24
Peak memory 193868 kb
Host smart-6b612f82-1d86-412e-9e0a-4e5bfad093ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82550616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.82550616
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.4247879617
Short name T570
Test name
Test status
Simulation time 38551713 ps
CPU time 0.77 seconds
Started Feb 28 05:22:09 PM PST 24
Finished Feb 28 05:22:10 PM PST 24
Peak memory 196136 kb
Host smart-b5adeb84-b455-4cac-892f-f52c777670db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247879617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.4247879617
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1967457225
Short name T545
Test name
Test status
Simulation time 499552815 ps
CPU time 28.34 seconds
Started Feb 28 05:22:10 PM PST 24
Finished Feb 28 05:22:39 PM PST 24
Peak memory 197084 kb
Host smart-1a31db93-7dca-4045-871d-dcf258ebaf66
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967457225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1967457225
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1671686864
Short name T403
Test name
Test status
Simulation time 46352017 ps
CPU time 0.68 seconds
Started Feb 28 05:22:10 PM PST 24
Finished Feb 28 05:22:11 PM PST 24
Peak memory 195496 kb
Host smart-faac723b-d0cf-422b-baf3-db17cef2c3bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671686864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1671686864
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.448287141
Short name T487
Test name
Test status
Simulation time 96993056 ps
CPU time 1.54 seconds
Started Feb 28 05:22:10 PM PST 24
Finished Feb 28 05:22:12 PM PST 24
Peak memory 198172 kb
Host smart-971e8363-da6b-4baa-97fb-f951b88092fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448287141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.448287141
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.917449740
Short name T424
Test name
Test status
Simulation time 21149507 ps
CPU time 0.93 seconds
Started Feb 28 05:22:11 PM PST 24
Finished Feb 28 05:22:13 PM PST 24
Peak memory 196116 kb
Host smart-1e837f80-abcc-47fb-a9dd-a3fcf7acbe19
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917449740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.917449740
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3500803495
Short name T222
Test name
Test status
Simulation time 357364081 ps
CPU time 2.73 seconds
Started Feb 28 05:22:18 PM PST 24
Finished Feb 28 05:22:21 PM PST 24
Peak memory 197256 kb
Host smart-1d3d98f5-9535-4ed1-95d4-fe45c52dd18c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500803495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3500803495
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3349360296
Short name T462
Test name
Test status
Simulation time 203546189 ps
CPU time 1.34 seconds
Started Feb 28 05:22:10 PM PST 24
Finished Feb 28 05:22:12 PM PST 24
Peak memory 197232 kb
Host smart-7197a829-99bb-4db1-a27b-edf1f93a8c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349360296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3349360296
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1002313141
Short name T405
Test name
Test status
Simulation time 116950425 ps
CPU time 1.23 seconds
Started Feb 28 05:22:07 PM PST 24
Finished Feb 28 05:22:08 PM PST 24
Peak memory 197220 kb
Host smart-3d796ffe-2748-4f60-891d-7dd70819ccb9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002313141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1002313141
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.717064447
Short name T197
Test name
Test status
Simulation time 95101387 ps
CPU time 1.34 seconds
Started Feb 28 05:22:18 PM PST 24
Finished Feb 28 05:22:20 PM PST 24
Peak memory 198068 kb
Host smart-c72900c2-7374-40aa-a17b-3b9d9d75ed7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717064447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.717064447
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3335577347
Short name T703
Test name
Test status
Simulation time 265807553 ps
CPU time 1.03 seconds
Started Feb 28 05:22:11 PM PST 24
Finished Feb 28 05:22:12 PM PST 24
Peak memory 195784 kb
Host smart-3199e3a9-1eaa-4f25-9fc1-444ac4e3cf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335577347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3335577347
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.833741459
Short name T289
Test name
Test status
Simulation time 112037401 ps
CPU time 0.92 seconds
Started Feb 28 05:22:10 PM PST 24
Finished Feb 28 05:22:11 PM PST 24
Peak memory 195492 kb
Host smart-5a621392-28de-4bfa-a438-b8f19fed9315
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833741459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.833741459
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2480598751
Short name T699
Test name
Test status
Simulation time 3796284854 ps
CPU time 120.35 seconds
Started Feb 28 05:22:12 PM PST 24
Finished Feb 28 05:24:13 PM PST 24
Peak memory 198340 kb
Host smart-077352bf-ba7c-4368-b5f6-dd89e66c68b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480598751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2480598751
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3089100382
Short name T686
Test name
Test status
Simulation time 12515473 ps
CPU time 0.55 seconds
Started Feb 28 05:22:14 PM PST 24
Finished Feb 28 05:22:15 PM PST 24
Peak memory 193960 kb
Host smart-1610287d-bddd-4f58-98ef-c9506aa1acfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089100382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3089100382
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1330764642
Short name T697
Test name
Test status
Simulation time 49466357 ps
CPU time 0.82 seconds
Started Feb 28 05:22:11 PM PST 24
Finished Feb 28 05:22:12 PM PST 24
Peak memory 196080 kb
Host smart-ecb3f07d-90ee-4f84-9c2c-71d0ab45a176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330764642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1330764642
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3057346228
Short name T104
Test name
Test status
Simulation time 91064791 ps
CPU time 4.98 seconds
Started Feb 28 05:22:12 PM PST 24
Finished Feb 28 05:22:18 PM PST 24
Peak memory 195632 kb
Host smart-bf512001-622b-4e8d-a793-e9e1008c69d3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057346228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3057346228
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3046424370
Short name T19
Test name
Test status
Simulation time 292751682 ps
CPU time 0.96 seconds
Started Feb 28 05:22:15 PM PST 24
Finished Feb 28 05:22:17 PM PST 24
Peak memory 197736 kb
Host smart-f10a62c9-777a-4f4b-831e-a55ab5540e59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046424370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3046424370
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.4018510078
Short name T337
Test name
Test status
Simulation time 36099589 ps
CPU time 1.14 seconds
Started Feb 28 05:22:17 PM PST 24
Finished Feb 28 05:22:18 PM PST 24
Peak memory 196608 kb
Host smart-8f5f8349-7c68-4688-bb79-a3cff30167d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018510078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.4018510078
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2956193806
Short name T310
Test name
Test status
Simulation time 102974735 ps
CPU time 1.3 seconds
Started Feb 28 05:22:11 PM PST 24
Finished Feb 28 05:22:13 PM PST 24
Peak memory 196832 kb
Host smart-324ac0c3-9de5-4a39-8bce-1838631556c3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956193806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2956193806
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3971324188
Short name T476
Test name
Test status
Simulation time 131822926 ps
CPU time 1.31 seconds
Started Feb 28 05:22:10 PM PST 24
Finished Feb 28 05:22:12 PM PST 24
Peak memory 197504 kb
Host smart-9c8da05b-0219-49ef-9339-1e2a43aef387
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971324188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3971324188
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3248670153
Short name T251
Test name
Test status
Simulation time 109762121 ps
CPU time 1.19 seconds
Started Feb 28 05:22:12 PM PST 24
Finished Feb 28 05:22:14 PM PST 24
Peak memory 196120 kb
Host smart-816dbb73-7ad4-430d-bf5c-84b6563517aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248670153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3248670153
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.12542480
Short name T134
Test name
Test status
Simulation time 149746614 ps
CPU time 1.1 seconds
Started Feb 28 05:22:12 PM PST 24
Finished Feb 28 05:22:14 PM PST 24
Peak memory 196172 kb
Host smart-bb550974-bdb4-4abb-a585-8ef481ec8b11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12542480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup_
pulldown.12542480
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.4283122299
Short name T324
Test name
Test status
Simulation time 610595813 ps
CPU time 2.22 seconds
Started Feb 28 05:22:15 PM PST 24
Finished Feb 28 05:22:18 PM PST 24
Peak memory 198112 kb
Host smart-3c9328cb-0c9e-492e-9545-179e01b45092
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283122299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.4283122299
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2227208674
Short name T611
Test name
Test status
Simulation time 73909214 ps
CPU time 1.12 seconds
Started Feb 28 05:22:11 PM PST 24
Finished Feb 28 05:22:13 PM PST 24
Peak memory 195896 kb
Host smart-c06cedd2-c4c0-4ae1-bd80-e5477f99420c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227208674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2227208674
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.346250821
Short name T262
Test name
Test status
Simulation time 75186327 ps
CPU time 1.34 seconds
Started Feb 28 05:22:17 PM PST 24
Finished Feb 28 05:22:19 PM PST 24
Peak memory 195664 kb
Host smart-e4411eca-c00d-4e3c-9fa1-95737445e8f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346250821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.346250821
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1635060706
Short name T142
Test name
Test status
Simulation time 18251224856 ps
CPU time 142.47 seconds
Started Feb 28 05:22:17 PM PST 24
Finished Feb 28 05:24:40 PM PST 24
Peak memory 198180 kb
Host smart-74e522c2-16c8-4f58-831c-e20eb5bfe595
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635060706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1635060706
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.139350052
Short name T68
Test name
Test status
Simulation time 144024560590 ps
CPU time 2353.78 seconds
Started Feb 28 05:22:15 PM PST 24
Finished Feb 28 06:01:30 PM PST 24
Peak memory 198400 kb
Host smart-30ddf08a-5fad-46fd-a097-8710391f283b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=139350052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.139350052
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.697308506
Short name T98
Test name
Test status
Simulation time 24051594 ps
CPU time 0.57 seconds
Started Feb 28 05:22:16 PM PST 24
Finished Feb 28 05:22:17 PM PST 24
Peak memory 193976 kb
Host smart-402223a4-f69e-4040-8e28-515714322462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697308506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.697308506
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.136444372
Short name T676
Test name
Test status
Simulation time 87349864 ps
CPU time 0.71 seconds
Started Feb 28 05:22:17 PM PST 24
Finished Feb 28 05:22:18 PM PST 24
Peak memory 194148 kb
Host smart-999f0c4d-94d3-48b7-9ea1-80414617c83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136444372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.136444372
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.491729153
Short name T158
Test name
Test status
Simulation time 4450940487 ps
CPU time 22.08 seconds
Started Feb 28 05:22:16 PM PST 24
Finished Feb 28 05:22:38 PM PST 24
Peak memory 196924 kb
Host smart-9539582e-466e-4958-960d-67b578600ff6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491729153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.491729153
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2889855974
Short name T332
Test name
Test status
Simulation time 185373187 ps
CPU time 0.88 seconds
Started Feb 28 05:22:15 PM PST 24
Finished Feb 28 05:22:16 PM PST 24
Peak memory 195904 kb
Host smart-14ab0576-a56e-48a7-bd48-eb91c066ac52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889855974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2889855974
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3208941758
Short name T472
Test name
Test status
Simulation time 149417547 ps
CPU time 1.31 seconds
Started Feb 28 05:22:15 PM PST 24
Finished Feb 28 05:22:17 PM PST 24
Peak memory 196116 kb
Host smart-0ccbbd2f-ccb2-4b73-8691-1bf4ca0f83fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208941758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3208941758
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2608637749
Short name T340
Test name
Test status
Simulation time 117304584 ps
CPU time 2.65 seconds
Started Feb 28 05:22:13 PM PST 24
Finished Feb 28 05:22:16 PM PST 24
Peak memory 198140 kb
Host smart-d191140a-3070-44e5-ad88-5e7e0cd47479
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608637749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2608637749
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3572547624
Short name T593
Test name
Test status
Simulation time 87748469 ps
CPU time 2.03 seconds
Started Feb 28 05:22:14 PM PST 24
Finished Feb 28 05:22:17 PM PST 24
Peak memory 196108 kb
Host smart-d17d7c6d-77a0-4812-86b4-3e5a56df4fb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572547624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3572547624
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1786643331
Short name T629
Test name
Test status
Simulation time 38637549 ps
CPU time 0.71 seconds
Started Feb 28 05:22:16 PM PST 24
Finished Feb 28 05:22:17 PM PST 24
Peak memory 196104 kb
Host smart-999e3d09-bbb8-41fc-8db6-6cae64ef7e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786643331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1786643331
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1122533467
Short name T658
Test name
Test status
Simulation time 29794477 ps
CPU time 0.83 seconds
Started Feb 28 05:22:13 PM PST 24
Finished Feb 28 05:22:15 PM PST 24
Peak memory 196284 kb
Host smart-9807c624-229a-412f-8197-f5e020883da2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122533467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1122533467
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.944854679
Short name T479
Test name
Test status
Simulation time 90241235 ps
CPU time 4.29 seconds
Started Feb 28 05:22:16 PM PST 24
Finished Feb 28 05:22:20 PM PST 24
Peak memory 197864 kb
Host smart-fb67108a-f173-44a9-8b14-38e1e388ca6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944854679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.944854679
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1604298041
Short name T568
Test name
Test status
Simulation time 162871537 ps
CPU time 1.11 seconds
Started Feb 28 05:22:16 PM PST 24
Finished Feb 28 05:22:17 PM PST 24
Peak memory 196340 kb
Host smart-342e6391-d56a-4805-88fd-06ce5280952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604298041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1604298041
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1745079263
Short name T234
Test name
Test status
Simulation time 65723251 ps
CPU time 0.89 seconds
Started Feb 28 05:22:14 PM PST 24
Finished Feb 28 05:22:16 PM PST 24
Peak memory 195396 kb
Host smart-63e8a457-ea25-45e9-9583-dd969e790a0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745079263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1745079263
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2456882668
Short name T664
Test name
Test status
Simulation time 5405024052 ps
CPU time 77.91 seconds
Started Feb 28 05:22:14 PM PST 24
Finished Feb 28 05:23:33 PM PST 24
Peak memory 198228 kb
Host smart-e783e4e0-a5ef-45a2-aa89-4ffa326c7f2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456882668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2456882668
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.497599818
Short name T681
Test name
Test status
Simulation time 33218696 ps
CPU time 0.56 seconds
Started Feb 28 05:22:19 PM PST 24
Finished Feb 28 05:22:20 PM PST 24
Peak memory 193996 kb
Host smart-d78abd34-60d0-4aee-811d-5d0dd6af65ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497599818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.497599818
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2111764503
Short name T178
Test name
Test status
Simulation time 109112026 ps
CPU time 0.93 seconds
Started Feb 28 05:22:23 PM PST 24
Finished Feb 28 05:22:24 PM PST 24
Peak memory 195736 kb
Host smart-e95e3b23-f0d7-48f4-8767-ed5ce3bda74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111764503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2111764503
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.820294434
Short name T160
Test name
Test status
Simulation time 548172264 ps
CPU time 14.48 seconds
Started Feb 28 05:22:19 PM PST 24
Finished Feb 28 05:22:34 PM PST 24
Peak memory 195592 kb
Host smart-911f7eca-244d-49fa-92fc-7c1867d6f159
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820294434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.820294434
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1124630097
Short name T333
Test name
Test status
Simulation time 550451728 ps
CPU time 0.98 seconds
Started Feb 28 05:22:17 PM PST 24
Finished Feb 28 05:22:19 PM PST 24
Peak memory 196452 kb
Host smart-116f8300-0c06-4d7d-845f-c96bd640040f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124630097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1124630097
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1625448088
Short name T549
Test name
Test status
Simulation time 250663791 ps
CPU time 1.2 seconds
Started Feb 28 05:22:19 PM PST 24
Finished Feb 28 05:22:21 PM PST 24
Peak memory 196152 kb
Host smart-79d772c5-a647-41bd-95b0-2753e7fff965
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625448088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1625448088
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3574193831
Short name T48
Test name
Test status
Simulation time 24279259 ps
CPU time 1.12 seconds
Started Feb 28 05:22:18 PM PST 24
Finished Feb 28 05:22:19 PM PST 24
Peak memory 196288 kb
Host smart-ef4b9df3-4a34-453b-adbe-890c4a9b7a8b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574193831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3574193831
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3527366868
Short name T191
Test name
Test status
Simulation time 427732608 ps
CPU time 2.36 seconds
Started Feb 28 05:22:20 PM PST 24
Finished Feb 28 05:22:23 PM PST 24
Peak memory 195916 kb
Host smart-f4be441d-5363-4240-b5ad-b4ae2c05a8a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527366868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3527366868
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3826496329
Short name T690
Test name
Test status
Simulation time 31552993 ps
CPU time 0.84 seconds
Started Feb 28 05:22:21 PM PST 24
Finished Feb 28 05:22:22 PM PST 24
Peak memory 196208 kb
Host smart-0102b6b8-0bc9-4d51-9960-926cc4aeb6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826496329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3826496329
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2689195973
Short name T47
Test name
Test status
Simulation time 35966024 ps
CPU time 0.65 seconds
Started Feb 28 05:22:20 PM PST 24
Finished Feb 28 05:22:21 PM PST 24
Peak memory 194260 kb
Host smart-5b5d3f2f-5754-422f-ad70-c22247a40507
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689195973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2689195973
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1765718766
Short name T349
Test name
Test status
Simulation time 361108396 ps
CPU time 4.29 seconds
Started Feb 28 05:22:18 PM PST 24
Finished Feb 28 05:22:22 PM PST 24
Peak memory 198108 kb
Host smart-07a6d784-3600-4669-b1d0-d73e0734b465
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765718766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1765718766
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2757386121
Short name T164
Test name
Test status
Simulation time 74771096 ps
CPU time 1.31 seconds
Started Feb 28 05:22:16 PM PST 24
Finished Feb 28 05:22:18 PM PST 24
Peak memory 196708 kb
Host smart-ad163db9-fddf-4c31-ad29-6dd8a2fb15c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757386121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2757386121
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.858242103
Short name T295
Test name
Test status
Simulation time 38631209 ps
CPU time 1.07 seconds
Started Feb 28 05:22:22 PM PST 24
Finished Feb 28 05:22:24 PM PST 24
Peak memory 195748 kb
Host smart-94ccf045-553b-4545-82bc-03af73d0dade
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858242103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.858242103
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1680298197
Short name T321
Test name
Test status
Simulation time 6291626937 ps
CPU time 47.37 seconds
Started Feb 28 05:22:19 PM PST 24
Finished Feb 28 05:23:06 PM PST 24
Peak memory 198232 kb
Host smart-8cb43902-d60a-4565-8674-56e7bce043d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680298197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1680298197
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.313772103
Short name T55
Test name
Test status
Simulation time 90656257435 ps
CPU time 1992.22 seconds
Started Feb 28 05:22:19 PM PST 24
Finished Feb 28 05:55:32 PM PST 24
Peak memory 198396 kb
Host smart-afc6bd58-9354-4727-b003-6da00f137958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=313772103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.313772103
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.876114614
Short name T366
Test name
Test status
Simulation time 16131170 ps
CPU time 0.57 seconds
Started Feb 28 05:22:23 PM PST 24
Finished Feb 28 05:22:24 PM PST 24
Peak memory 194824 kb
Host smart-1f8c1e4b-f266-4895-a79e-447a6f406d32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876114614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.876114614
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2270157436
Short name T402
Test name
Test status
Simulation time 32595309 ps
CPU time 0.75 seconds
Started Feb 28 05:22:24 PM PST 24
Finished Feb 28 05:22:25 PM PST 24
Peak memory 195260 kb
Host smart-de1ca4da-e488-4c9c-a25a-d25be421e3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270157436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2270157436
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1441795496
Short name T225
Test name
Test status
Simulation time 1283640922 ps
CPU time 15.62 seconds
Started Feb 28 05:22:23 PM PST 24
Finished Feb 28 05:22:39 PM PST 24
Peak memory 196988 kb
Host smart-c3c38e0a-b78b-4893-b908-79b917cfd837
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441795496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1441795496
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2967052827
Short name T644
Test name
Test status
Simulation time 46426139 ps
CPU time 0.89 seconds
Started Feb 28 05:22:26 PM PST 24
Finished Feb 28 05:22:27 PM PST 24
Peak memory 195896 kb
Host smart-3c69840a-c93e-4612-8b7f-6dfb6ebda990
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967052827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2967052827
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.910585769
Short name T24
Test name
Test status
Simulation time 393190025 ps
CPU time 1.1 seconds
Started Feb 28 05:22:24 PM PST 24
Finished Feb 28 05:22:26 PM PST 24
Peak memory 196108 kb
Host smart-265cf931-c9fc-4055-a5ed-e66e25c8d8f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910585769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.910585769
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.588574447
Short name T649
Test name
Test status
Simulation time 58950811 ps
CPU time 2.37 seconds
Started Feb 28 05:22:24 PM PST 24
Finished Feb 28 05:22:27 PM PST 24
Peak memory 198192 kb
Host smart-6102c69c-d729-4a8a-8c07-e1a684c26906
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588574447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.588574447
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.854572093
Short name T475
Test name
Test status
Simulation time 162519527 ps
CPU time 2.61 seconds
Started Feb 28 05:22:23 PM PST 24
Finished Feb 28 05:22:26 PM PST 24
Peak memory 198176 kb
Host smart-460cd63a-bfd1-4263-89fb-a0bc01a7551e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854572093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
854572093
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2343044071
Short name T181
Test name
Test status
Simulation time 17019404 ps
CPU time 0.77 seconds
Started Feb 28 05:22:24 PM PST 24
Finished Feb 28 05:22:25 PM PST 24
Peak memory 195488 kb
Host smart-00ecae90-2eaa-4e35-a2e0-aeb37d5318d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343044071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2343044071
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1491292719
Short name T619
Test name
Test status
Simulation time 110976354 ps
CPU time 1.08 seconds
Started Feb 28 05:22:25 PM PST 24
Finished Feb 28 05:22:26 PM PST 24
Peak memory 196620 kb
Host smart-4de87ec5-a50c-4cf8-9bc0-fba37b176f21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491292719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1491292719
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.692597469
Short name T700
Test name
Test status
Simulation time 450647666 ps
CPU time 4.14 seconds
Started Feb 28 05:22:22 PM PST 24
Finished Feb 28 05:22:27 PM PST 24
Peak memory 198040 kb
Host smart-e0f554e2-7c19-4e14-ace3-7f0766bd8d08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692597469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.692597469
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1988160075
Short name T355
Test name
Test status
Simulation time 30518867 ps
CPU time 0.89 seconds
Started Feb 28 05:22:19 PM PST 24
Finished Feb 28 05:22:20 PM PST 24
Peak memory 195520 kb
Host smart-ebad8c85-a34d-4fb4-a93d-2671a2106203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988160075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1988160075
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.91786957
Short name T599
Test name
Test status
Simulation time 72361570 ps
CPU time 1.27 seconds
Started Feb 28 05:22:26 PM PST 24
Finished Feb 28 05:22:27 PM PST 24
Peak memory 195852 kb
Host smart-2bc6a6f8-3189-4225-99b7-64917f918ebc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91786957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.91786957
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1255571736
Short name T459
Test name
Test status
Simulation time 4126324211 ps
CPU time 116.38 seconds
Started Feb 28 05:22:24 PM PST 24
Finished Feb 28 05:24:20 PM PST 24
Peak memory 198188 kb
Host smart-3e8e9b3c-85e6-4901-9240-440338709cc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255571736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1255571736
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.625414772
Short name T434
Test name
Test status
Simulation time 65512305 ps
CPU time 0.61 seconds
Started Feb 28 05:22:29 PM PST 24
Finished Feb 28 05:22:30 PM PST 24
Peak memory 194600 kb
Host smart-c29a1584-6a64-4db0-b78b-a828eb2c17c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625414772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.625414772
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.271912599
Short name T539
Test name
Test status
Simulation time 101300686 ps
CPU time 0.78 seconds
Started Feb 28 05:22:32 PM PST 24
Finished Feb 28 05:22:33 PM PST 24
Peak memory 194200 kb
Host smart-1bf4ccc7-dabe-43cd-b34f-acab74aa272d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271912599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.271912599
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.4083299018
Short name T471
Test name
Test status
Simulation time 397156608 ps
CPU time 6.84 seconds
Started Feb 28 05:22:28 PM PST 24
Finished Feb 28 05:22:35 PM PST 24
Peak memory 195636 kb
Host smart-d0c5a4ad-9fba-43bd-907f-6adf6ce607ac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083299018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.4083299018
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1967978391
Short name T601
Test name
Test status
Simulation time 19137866 ps
CPU time 0.64 seconds
Started Feb 28 05:22:30 PM PST 24
Finished Feb 28 05:22:31 PM PST 24
Peak memory 195184 kb
Host smart-a765faa4-97a7-4123-a4d2-6c453784fb7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967978391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1967978391
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1651708070
Short name T140
Test name
Test status
Simulation time 441738026 ps
CPU time 1.34 seconds
Started Feb 28 05:22:27 PM PST 24
Finished Feb 28 05:22:29 PM PST 24
Peak memory 195868 kb
Host smart-733d3d10-4323-4f9b-9551-ad3140a016cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651708070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1651708070
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1730141304
Short name T493
Test name
Test status
Simulation time 197426681 ps
CPU time 2.56 seconds
Started Feb 28 05:22:29 PM PST 24
Finished Feb 28 05:22:32 PM PST 24
Peak memory 198180 kb
Host smart-08ee08f9-028c-45ca-90b5-475a895c6175
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730141304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1730141304
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.892152593
Short name T553
Test name
Test status
Simulation time 34734591 ps
CPU time 1.16 seconds
Started Feb 28 05:22:28 PM PST 24
Finished Feb 28 05:22:30 PM PST 24
Peak memory 196548 kb
Host smart-7e253a26-3857-49c9-aca3-291432cbc82e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892152593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
892152593
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1526247376
Short name T357
Test name
Test status
Simulation time 45518346 ps
CPU time 1.08 seconds
Started Feb 28 05:22:29 PM PST 24
Finished Feb 28 05:22:30 PM PST 24
Peak memory 196108 kb
Host smart-44b90317-5256-4e59-8b0d-b66f7ca623d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526247376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1526247376
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3274041959
Short name T145
Test name
Test status
Simulation time 25829933 ps
CPU time 1.03 seconds
Started Feb 28 05:22:26 PM PST 24
Finished Feb 28 05:22:27 PM PST 24
Peak memory 196644 kb
Host smart-c36fc02d-be96-494b-b248-d392b3872706
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274041959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3274041959
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3117865190
Short name T458
Test name
Test status
Simulation time 261161896 ps
CPU time 4.37 seconds
Started Feb 28 05:22:28 PM PST 24
Finished Feb 28 05:22:33 PM PST 24
Peak memory 198072 kb
Host smart-efb8baa5-c71e-40a5-9384-9e673c408917
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117865190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3117865190
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.877390308
Short name T513
Test name
Test status
Simulation time 159184067 ps
CPU time 1.48 seconds
Started Feb 28 05:22:23 PM PST 24
Finished Feb 28 05:22:25 PM PST 24
Peak memory 196356 kb
Host smart-4c9c6898-724a-4574-ba91-0104edaf3f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877390308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.877390308
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2704409003
Short name T443
Test name
Test status
Simulation time 152584105 ps
CPU time 1.07 seconds
Started Feb 28 05:22:25 PM PST 24
Finished Feb 28 05:22:26 PM PST 24
Peak memory 195828 kb
Host smart-432cf537-5668-4619-bd72-9fbbae95bd6f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704409003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2704409003
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1878389916
Short name T195
Test name
Test status
Simulation time 1675322178 ps
CPU time 23.96 seconds
Started Feb 28 05:22:29 PM PST 24
Finished Feb 28 05:22:53 PM PST 24
Peak memory 198076 kb
Host smart-af6b08a6-e6a7-4c7e-aff6-f78552b66c3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878389916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1878389916
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.1617141817
Short name T28
Test name
Test status
Simulation time 35750775630 ps
CPU time 801.51 seconds
Started Feb 28 05:22:29 PM PST 24
Finished Feb 28 05:35:51 PM PST 24
Peak memory 198308 kb
Host smart-3f1aeb09-457c-48d2-b74e-01ab6f7845a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1617141817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.1617141817
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3659841263
Short name T523
Test name
Test status
Simulation time 52960297 ps
CPU time 0.58 seconds
Started Feb 28 05:22:31 PM PST 24
Finished Feb 28 05:22:32 PM PST 24
Peak memory 194140 kb
Host smart-76fe95ed-2b5d-42c9-bb34-28b90d82d36c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659841263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3659841263
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2751843746
Short name T708
Test name
Test status
Simulation time 85278598 ps
CPU time 0.85 seconds
Started Feb 28 05:22:33 PM PST 24
Finished Feb 28 05:22:34 PM PST 24
Peak memory 195448 kb
Host smart-0afdab1b-0bdb-4eff-8083-3871b5cffb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751843746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2751843746
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3512280439
Short name T347
Test name
Test status
Simulation time 1795923739 ps
CPU time 14.46 seconds
Started Feb 28 05:22:35 PM PST 24
Finished Feb 28 05:22:49 PM PST 24
Peak memory 197080 kb
Host smart-cb672836-f366-4cda-88b3-336a26e1e0bc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512280439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3512280439
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3507932618
Short name T595
Test name
Test status
Simulation time 320319900 ps
CPU time 1.09 seconds
Started Feb 28 05:22:34 PM PST 24
Finished Feb 28 05:22:35 PM PST 24
Peak memory 196628 kb
Host smart-033398cd-1598-4619-bd4a-e7fb15579c34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507932618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3507932618
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2454166834
Short name T229
Test name
Test status
Simulation time 92242840 ps
CPU time 1.55 seconds
Started Feb 28 05:22:31 PM PST 24
Finished Feb 28 05:22:33 PM PST 24
Peak memory 197024 kb
Host smart-bd87deb3-2a8a-4019-9dc1-6a2f6750edee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454166834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2454166834
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.360890868
Short name T369
Test name
Test status
Simulation time 239814396 ps
CPU time 1.77 seconds
Started Feb 28 05:22:32 PM PST 24
Finished Feb 28 05:22:34 PM PST 24
Peak memory 196856 kb
Host smart-3a651bb5-9eb1-48c8-81d8-e8c6b8151eeb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360890868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.360890868
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1060490943
Short name T244
Test name
Test status
Simulation time 72654677 ps
CPU time 1.73 seconds
Started Feb 28 05:22:31 PM PST 24
Finished Feb 28 05:22:33 PM PST 24
Peak memory 196328 kb
Host smart-4dc0d320-2abe-4d78-8305-3c96da818864
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060490943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1060490943
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1817758819
Short name T146
Test name
Test status
Simulation time 108318327 ps
CPU time 0.95 seconds
Started Feb 28 05:22:27 PM PST 24
Finished Feb 28 05:22:28 PM PST 24
Peak memory 196780 kb
Host smart-03877b57-e2a8-4c87-9d3a-0c5f9e033566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817758819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1817758819
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2512909480
Short name T530
Test name
Test status
Simulation time 149045224 ps
CPU time 1.16 seconds
Started Feb 28 05:22:25 PM PST 24
Finished Feb 28 05:22:27 PM PST 24
Peak memory 196724 kb
Host smart-a08def4f-6a0b-4d34-946e-739bcaf1c35e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512909480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2512909480
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1490515197
Short name T6
Test name
Test status
Simulation time 4274890688 ps
CPU time 5.64 seconds
Started Feb 28 05:22:33 PM PST 24
Finished Feb 28 05:22:39 PM PST 24
Peak memory 198164 kb
Host smart-b7efe2cd-7e2d-416c-affe-f69b9b66a20a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490515197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1490515197
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1162905133
Short name T139
Test name
Test status
Simulation time 74985056 ps
CPU time 1.16 seconds
Started Feb 28 05:22:29 PM PST 24
Finished Feb 28 05:22:30 PM PST 24
Peak memory 195832 kb
Host smart-5d3879cf-b7c7-424f-ad9e-5e00b5925ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162905133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1162905133
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.162495653
Short name T460
Test name
Test status
Simulation time 440609760 ps
CPU time 1.21 seconds
Started Feb 28 05:22:29 PM PST 24
Finished Feb 28 05:22:30 PM PST 24
Peak memory 195968 kb
Host smart-ea70e3d6-ed12-43f4-bde2-583bfa0a271f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162495653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.162495653
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2948900801
Short name T694
Test name
Test status
Simulation time 4662798145 ps
CPU time 136.34 seconds
Started Feb 28 05:22:35 PM PST 24
Finished Feb 28 05:24:51 PM PST 24
Peak memory 198252 kb
Host smart-c561033a-9f81-4cc7-8c51-a1925ab4a9ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948900801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2948900801
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.660915398
Short name T305
Test name
Test status
Simulation time 14687814 ps
CPU time 0.59 seconds
Started Feb 28 05:22:40 PM PST 24
Finished Feb 28 05:22:41 PM PST 24
Peak memory 193972 kb
Host smart-a5183295-9c77-4a69-ac4f-ff52b309fe3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660915398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.660915398
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3079188514
Short name T396
Test name
Test status
Simulation time 34137358 ps
CPU time 0.76 seconds
Started Feb 28 05:22:34 PM PST 24
Finished Feb 28 05:22:35 PM PST 24
Peak memory 195260 kb
Host smart-4696eb7c-643b-4d41-bbe7-0b30b191c716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079188514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3079188514
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1721835346
Short name T269
Test name
Test status
Simulation time 728711584 ps
CPU time 5.86 seconds
Started Feb 28 05:22:33 PM PST 24
Finished Feb 28 05:22:39 PM PST 24
Peak memory 196428 kb
Host smart-fa08546c-7a06-4ab9-99c5-947c60471b7e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721835346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1721835346
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1343509442
Short name T391
Test name
Test status
Simulation time 40073731 ps
CPU time 0.73 seconds
Started Feb 28 05:22:36 PM PST 24
Finished Feb 28 05:22:36 PM PST 24
Peak memory 195088 kb
Host smart-43fc6e5d-7647-4bb7-b86e-f023ce258e6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343509442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1343509442
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3904421636
Short name T711
Test name
Test status
Simulation time 61887346 ps
CPU time 0.83 seconds
Started Feb 28 05:22:35 PM PST 24
Finished Feb 28 05:22:36 PM PST 24
Peak memory 196156 kb
Host smart-7239c04b-4e26-4188-9e21-843e563eaf6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904421636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3904421636
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3724226963
Short name T580
Test name
Test status
Simulation time 28666746 ps
CPU time 1.33 seconds
Started Feb 28 05:22:36 PM PST 24
Finished Feb 28 05:22:38 PM PST 24
Peak memory 196988 kb
Host smart-d366d4f0-7575-487c-8d40-badf4ebf0a0f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724226963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3724226963
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1533765727
Short name T143
Test name
Test status
Simulation time 22501228 ps
CPU time 0.97 seconds
Started Feb 28 05:22:33 PM PST 24
Finished Feb 28 05:22:34 PM PST 24
Peak memory 196268 kb
Host smart-136769a3-6fa7-48c2-b51e-fd1e4699befa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533765727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1533765727
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3872694466
Short name T666
Test name
Test status
Simulation time 22376489 ps
CPU time 0.89 seconds
Started Feb 28 05:22:37 PM PST 24
Finished Feb 28 05:22:38 PM PST 24
Peak memory 195956 kb
Host smart-22ec8ad1-60f4-4199-b701-ec4c1d04c79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872694466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3872694466
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1410531213
Short name T669
Test name
Test status
Simulation time 1045179486 ps
CPU time 1.19 seconds
Started Feb 28 05:22:35 PM PST 24
Finished Feb 28 05:22:37 PM PST 24
Peak memory 195896 kb
Host smart-dce80c3c-41fb-45dd-a587-00d446329d33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410531213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1410531213
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.322178642
Short name T672
Test name
Test status
Simulation time 281682790 ps
CPU time 3.82 seconds
Started Feb 28 05:22:36 PM PST 24
Finished Feb 28 05:22:39 PM PST 24
Peak memory 198056 kb
Host smart-4c52ea86-4e16-4539-8d8c-34e13b0e9466
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322178642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.322178642
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1242609427
Short name T504
Test name
Test status
Simulation time 59573778 ps
CPU time 0.81 seconds
Started Feb 28 05:22:32 PM PST 24
Finished Feb 28 05:22:33 PM PST 24
Peak memory 195284 kb
Host smart-e802596b-e762-48fa-a7ee-b0f449774ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242609427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1242609427
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2961011987
Short name T448
Test name
Test status
Simulation time 152878056 ps
CPU time 1.37 seconds
Started Feb 28 05:22:32 PM PST 24
Finished Feb 28 05:22:34 PM PST 24
Peak memory 197240 kb
Host smart-98a27b6a-15a4-4fce-95f0-a9da4c0e0fca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961011987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2961011987
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2127459524
Short name T656
Test name
Test status
Simulation time 7295626807 ps
CPU time 143.72 seconds
Started Feb 28 05:22:39 PM PST 24
Finished Feb 28 05:25:03 PM PST 24
Peak memory 198204 kb
Host smart-0462926e-9ec5-467e-99c3-922607808c58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127459524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2127459524
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.4113829891
Short name T597
Test name
Test status
Simulation time 46693323850 ps
CPU time 600.46 seconds
Started Feb 28 05:22:39 PM PST 24
Finished Feb 28 05:32:40 PM PST 24
Peak memory 198280 kb
Host smart-05cbeccb-5b2f-4ce6-907f-85abebcfb3f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4113829891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.4113829891
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2165022366
Short name T397
Test name
Test status
Simulation time 13099061 ps
CPU time 0.57 seconds
Started Feb 28 05:22:44 PM PST 24
Finished Feb 28 05:22:45 PM PST 24
Peak memory 193940 kb
Host smart-3b81caae-b915-48a8-be1b-6b6a5bd6b75e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165022366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2165022366
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.440839045
Short name T342
Test name
Test status
Simulation time 81229682 ps
CPU time 0.9 seconds
Started Feb 28 05:22:45 PM PST 24
Finished Feb 28 05:22:46 PM PST 24
Peak memory 195300 kb
Host smart-4c6e0c1f-662c-4404-bbe8-9b0c7fae140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440839045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.440839045
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3290138330
Short name T267
Test name
Test status
Simulation time 363807128 ps
CPU time 11.78 seconds
Started Feb 28 05:22:42 PM PST 24
Finished Feb 28 05:22:55 PM PST 24
Peak memory 198112 kb
Host smart-6f60c33e-81fe-441e-90b1-ad9f486988a1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290138330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3290138330
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2765838473
Short name T587
Test name
Test status
Simulation time 835192441 ps
CPU time 1.04 seconds
Started Feb 28 05:22:41 PM PST 24
Finished Feb 28 05:22:42 PM PST 24
Peak memory 196452 kb
Host smart-55bd2d23-68cd-44ff-8757-d5380fcf5f47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765838473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2765838473
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3716538491
Short name T400
Test name
Test status
Simulation time 40741087 ps
CPU time 0.97 seconds
Started Feb 28 05:22:43 PM PST 24
Finished Feb 28 05:22:44 PM PST 24
Peak memory 196520 kb
Host smart-d8415a9e-598a-46c6-a572-96238de9e6d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716538491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3716538491
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2374588151
Short name T218
Test name
Test status
Simulation time 78029286 ps
CPU time 3.32 seconds
Started Feb 28 05:22:45 PM PST 24
Finished Feb 28 05:22:48 PM PST 24
Peak memory 198136 kb
Host smart-51a66755-e525-40f8-a5a9-b329eaaffef0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374588151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2374588151
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3730102833
Short name T18
Test name
Test status
Simulation time 315852296 ps
CPU time 1.78 seconds
Started Feb 28 05:22:43 PM PST 24
Finished Feb 28 05:22:46 PM PST 24
Peak memory 195856 kb
Host smart-21e24c50-be76-4ab2-800a-006dff5118a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730102833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3730102833
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1955982832
Short name T499
Test name
Test status
Simulation time 35009868 ps
CPU time 1.03 seconds
Started Feb 28 05:22:38 PM PST 24
Finished Feb 28 05:22:39 PM PST 24
Peak memory 196124 kb
Host smart-ddde3402-0d66-4ced-9e11-70d6a7553691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955982832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1955982832
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.92748905
Short name T151
Test name
Test status
Simulation time 66993196 ps
CPU time 0.66 seconds
Started Feb 28 05:22:40 PM PST 24
Finished Feb 28 05:22:41 PM PST 24
Peak memory 194356 kb
Host smart-490a7a28-7129-48b9-b4ee-f4d5f499c240
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92748905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup_
pulldown.92748905
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2503388496
Short name T135
Test name
Test status
Simulation time 114773205 ps
CPU time 1.67 seconds
Started Feb 28 05:22:44 PM PST 24
Finished Feb 28 05:22:46 PM PST 24
Peak memory 198096 kb
Host smart-007f5553-3135-4f01-95f4-f8624075af48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503388496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2503388496
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3098894861
Short name T470
Test name
Test status
Simulation time 315274108 ps
CPU time 1.13 seconds
Started Feb 28 05:22:39 PM PST 24
Finished Feb 28 05:22:40 PM PST 24
Peak memory 195900 kb
Host smart-8cc1155a-3179-40aa-94cf-36c46cbcec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098894861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3098894861
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1105319751
Short name T650
Test name
Test status
Simulation time 100389123 ps
CPU time 0.92 seconds
Started Feb 28 05:22:39 PM PST 24
Finished Feb 28 05:22:41 PM PST 24
Peak memory 195616 kb
Host smart-0aac718d-18e8-49cd-8689-239d35559739
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105319751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1105319751
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1560298775
Short name T254
Test name
Test status
Simulation time 4855777043 ps
CPU time 33.55 seconds
Started Feb 28 05:22:44 PM PST 24
Finished Feb 28 05:23:17 PM PST 24
Peak memory 198172 kb
Host smart-33b56add-ac30-4eff-8b43-2f2ff4ecd22e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560298775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1560298775
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.591711849
Short name T280
Test name
Test status
Simulation time 20601599 ps
CPU time 0.62 seconds
Started Feb 28 05:20:02 PM PST 24
Finished Feb 28 05:20:04 PM PST 24
Peak memory 193960 kb
Host smart-cb955b29-19ca-484c-9d03-6a7a6663b80b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591711849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.591711849
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1192558621
Short name T426
Test name
Test status
Simulation time 119326628 ps
CPU time 0.92 seconds
Started Feb 28 05:19:56 PM PST 24
Finished Feb 28 05:19:57 PM PST 24
Peak memory 196124 kb
Host smart-8412c203-f20c-49d2-a034-c6726dbae051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192558621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1192558621
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2729343596
Short name T437
Test name
Test status
Simulation time 212444626 ps
CPU time 10.79 seconds
Started Feb 28 05:19:56 PM PST 24
Finished Feb 28 05:20:07 PM PST 24
Peak memory 196844 kb
Host smart-ca9b137b-b497-4713-bfae-232d1bf5c3ac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729343596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2729343596
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1083945679
Short name T110
Test name
Test status
Simulation time 61939124 ps
CPU time 0.73 seconds
Started Feb 28 05:19:57 PM PST 24
Finished Feb 28 05:19:58 PM PST 24
Peak memory 194852 kb
Host smart-76fc211d-5b45-41d6-a99c-d55ad64f5b66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083945679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1083945679
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2720306838
Short name T118
Test name
Test status
Simulation time 94880537 ps
CPU time 0.94 seconds
Started Feb 28 05:19:57 PM PST 24
Finished Feb 28 05:19:58 PM PST 24
Peak memory 196200 kb
Host smart-6e9afbbb-ab26-4b11-9818-3d5cea7270bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720306838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2720306838
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2587353965
Short name T224
Test name
Test status
Simulation time 62048247 ps
CPU time 1.34 seconds
Started Feb 28 05:19:58 PM PST 24
Finished Feb 28 05:19:59 PM PST 24
Peak memory 198212 kb
Host smart-0e099227-1b36-4304-afa4-28307524ed55
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587353965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2587353965
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.174214657
Short name T578
Test name
Test status
Simulation time 82790507 ps
CPU time 2.56 seconds
Started Feb 28 05:19:54 PM PST 24
Finished Feb 28 05:19:57 PM PST 24
Peak memory 198144 kb
Host smart-bd8f4921-a191-4b00-a9e6-9a5a4c7138a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174214657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.174214657
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.5399053
Short name T683
Test name
Test status
Simulation time 23301017 ps
CPU time 0.77 seconds
Started Feb 28 05:19:56 PM PST 24
Finished Feb 28 05:19:57 PM PST 24
Peak memory 196196 kb
Host smart-c14139f0-65eb-4976-ba37-a592c1e5b83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5399053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.5399053
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3854357479
Short name T362
Test name
Test status
Simulation time 22268883 ps
CPU time 0.78 seconds
Started Feb 28 05:19:56 PM PST 24
Finished Feb 28 05:19:56 PM PST 24
Peak memory 195512 kb
Host smart-024a6bbe-1f7b-4337-9647-0f5aee65e62e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854357479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3854357479
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2196988447
Short name T61
Test name
Test status
Simulation time 314029607 ps
CPU time 3.86 seconds
Started Feb 28 05:19:56 PM PST 24
Finished Feb 28 05:20:00 PM PST 24
Peak memory 198100 kb
Host smart-c74e4b7f-2d96-4615-94db-8b06861cd4c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196988447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2196988447
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1045738399
Short name T165
Test name
Test status
Simulation time 153721727 ps
CPU time 0.88 seconds
Started Feb 28 05:19:56 PM PST 24
Finished Feb 28 05:19:57 PM PST 24
Peak memory 195428 kb
Host smart-69c8e460-e81d-4d4f-8d83-1e3499ea84fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045738399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1045738399
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1586677005
Short name T481
Test name
Test status
Simulation time 177346983 ps
CPU time 0.98 seconds
Started Feb 28 05:19:55 PM PST 24
Finished Feb 28 05:19:56 PM PST 24
Peak memory 196316 kb
Host smart-7d5b0175-d3d1-4d0f-820b-00c4efcf89e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586677005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1586677005
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2122866573
Short name T610
Test name
Test status
Simulation time 22509370094 ps
CPU time 173.96 seconds
Started Feb 28 05:20:00 PM PST 24
Finished Feb 28 05:22:54 PM PST 24
Peak memory 198216 kb
Host smart-ab6e8b6d-1ab8-446c-a41e-a133d0e56e7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122866573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2122866573
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2927710722
Short name T693
Test name
Test status
Simulation time 15137564 ps
CPU time 0.58 seconds
Started Feb 28 05:20:03 PM PST 24
Finished Feb 28 05:20:04 PM PST 24
Peak memory 193984 kb
Host smart-7428b98e-3881-409c-a618-7f2570f307b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927710722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2927710722
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1241198141
Short name T304
Test name
Test status
Simulation time 29030067 ps
CPU time 0.81 seconds
Started Feb 28 05:20:02 PM PST 24
Finished Feb 28 05:20:03 PM PST 24
Peak memory 194932 kb
Host smart-c297bdb1-4fd0-42cf-9b0f-25713370773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241198141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1241198141
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.404309346
Short name T344
Test name
Test status
Simulation time 863544689 ps
CPU time 6.27 seconds
Started Feb 28 05:20:00 PM PST 24
Finished Feb 28 05:20:07 PM PST 24
Peak memory 195696 kb
Host smart-4cece338-56ec-48df-bae5-dee1872ae53d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404309346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.404309346
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3894516481
Short name T14
Test name
Test status
Simulation time 182249666 ps
CPU time 0.85 seconds
Started Feb 28 05:20:01 PM PST 24
Finished Feb 28 05:20:02 PM PST 24
Peak memory 195896 kb
Host smart-cf8fd109-4724-4000-a216-071c6d1e56a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894516481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3894516481
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1970718531
Short name T327
Test name
Test status
Simulation time 313175292 ps
CPU time 1.55 seconds
Started Feb 28 05:20:04 PM PST 24
Finished Feb 28 05:20:06 PM PST 24
Peak memory 197204 kb
Host smart-eda2d144-49a1-43c0-b0af-1e91f35b85da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970718531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1970718531
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3270783306
Short name T524
Test name
Test status
Simulation time 23041573 ps
CPU time 1.11 seconds
Started Feb 28 05:20:00 PM PST 24
Finished Feb 28 05:20:01 PM PST 24
Peak memory 196304 kb
Host smart-01096d82-9178-4ed0-8d2c-8e9bd58e1b72
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270783306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3270783306
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.4000777397
Short name T330
Test name
Test status
Simulation time 105626247 ps
CPU time 1.67 seconds
Started Feb 28 05:20:00 PM PST 24
Finished Feb 28 05:20:02 PM PST 24
Peak memory 196068 kb
Host smart-eac8a8f9-e9a8-44cb-922f-b499d0e8d5aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000777397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
4000777397
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2784485463
Short name T547
Test name
Test status
Simulation time 23893587 ps
CPU time 0.82 seconds
Started Feb 28 05:20:02 PM PST 24
Finished Feb 28 05:20:03 PM PST 24
Peak memory 196256 kb
Host smart-be10b9b4-467a-438a-9d13-7081e56c8e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784485463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2784485463
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2698349928
Short name T228
Test name
Test status
Simulation time 68844440 ps
CPU time 1.29 seconds
Started Feb 28 05:20:01 PM PST 24
Finished Feb 28 05:20:03 PM PST 24
Peak memory 197108 kb
Host smart-923388a6-6e11-4683-95a9-ea56a72e2056
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698349928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2698349928
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2871779355
Short name T514
Test name
Test status
Simulation time 1017529581 ps
CPU time 5.21 seconds
Started Feb 28 05:20:00 PM PST 24
Finished Feb 28 05:20:06 PM PST 24
Peak memory 198100 kb
Host smart-35f4ca57-fd6a-4e4f-9428-e81e210bd87c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871779355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2871779355
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1521554392
Short name T185
Test name
Test status
Simulation time 111652371 ps
CPU time 0.95 seconds
Started Feb 28 05:20:02 PM PST 24
Finished Feb 28 05:20:03 PM PST 24
Peak memory 196616 kb
Host smart-53f83761-bb85-4b29-8418-1d3fb7a84940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521554392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1521554392
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2150217426
Short name T171
Test name
Test status
Simulation time 116707877 ps
CPU time 0.82 seconds
Started Feb 28 05:20:01 PM PST 24
Finished Feb 28 05:20:02 PM PST 24
Peak memory 195384 kb
Host smart-333031b8-d07d-4901-9f62-c6fedd0c01cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150217426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2150217426
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3789687427
Short name T559
Test name
Test status
Simulation time 16408593132 ps
CPU time 102.69 seconds
Started Feb 28 05:20:01 PM PST 24
Finished Feb 28 05:21:44 PM PST 24
Peak memory 198228 kb
Host smart-36abe9a2-29af-4497-bdc3-a3b1918c9c0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789687427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3789687427
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1545249559
Short name T27
Test name
Test status
Simulation time 403742739732 ps
CPU time 1905.54 seconds
Started Feb 28 05:20:01 PM PST 24
Finished Feb 28 05:51:47 PM PST 24
Peak memory 198360 kb
Host smart-fe273b28-eed7-4f7a-ad87-9c5a3cb7058c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1545249559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1545249559
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3653147387
Short name T419
Test name
Test status
Simulation time 42667967 ps
CPU time 0.57 seconds
Started Feb 28 05:20:07 PM PST 24
Finished Feb 28 05:20:07 PM PST 24
Peak memory 193724 kb
Host smart-085b87ad-adfb-4a6b-a8ae-378bb2e03abd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653147387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3653147387
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1526496059
Short name T99
Test name
Test status
Simulation time 79801207 ps
CPU time 0.78 seconds
Started Feb 28 05:20:04 PM PST 24
Finished Feb 28 05:20:05 PM PST 24
Peak memory 195384 kb
Host smart-36710b2f-963b-4ab6-95b2-8d1203f4b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526496059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1526496059
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1560880513
Short name T374
Test name
Test status
Simulation time 710624059 ps
CPU time 24.97 seconds
Started Feb 28 05:20:05 PM PST 24
Finished Feb 28 05:20:31 PM PST 24
Peak memory 197048 kb
Host smart-62a0e063-777a-4099-9d63-9c724b1bc218
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560880513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1560880513
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.528808132
Short name T625
Test name
Test status
Simulation time 80185130 ps
CPU time 1.01 seconds
Started Feb 28 05:20:04 PM PST 24
Finished Feb 28 05:20:05 PM PST 24
Peak memory 197280 kb
Host smart-6f45025e-7712-436c-aead-41d9138eb502
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528808132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.528808132
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2538321302
Short name T536
Test name
Test status
Simulation time 109597190 ps
CPU time 1.68 seconds
Started Feb 28 05:20:07 PM PST 24
Finished Feb 28 05:20:08 PM PST 24
Peak memory 196708 kb
Host smart-50d752f7-9e79-44d1-a037-3d477c4409b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538321302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2538321302
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.141014341
Short name T430
Test name
Test status
Simulation time 89796543 ps
CPU time 3.48 seconds
Started Feb 28 05:20:05 PM PST 24
Finished Feb 28 05:20:09 PM PST 24
Peak memory 198196 kb
Host smart-d73fc9e5-8121-4e5e-9702-eaefe22f245a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141014341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.141014341
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3181573333
Short name T370
Test name
Test status
Simulation time 153881602 ps
CPU time 3.06 seconds
Started Feb 28 05:20:09 PM PST 24
Finished Feb 28 05:20:12 PM PST 24
Peak memory 197204 kb
Host smart-d53e5aff-03c9-4a07-86c3-f00938079b3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181573333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3181573333
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3560043369
Short name T100
Test name
Test status
Simulation time 65387529 ps
CPU time 1.19 seconds
Started Feb 28 05:20:03 PM PST 24
Finished Feb 28 05:20:05 PM PST 24
Peak memory 195928 kb
Host smart-a6e68a33-e2bc-4d4a-87e3-dda2fc5f1c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560043369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3560043369
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.582742284
Short name T622
Test name
Test status
Simulation time 117949401 ps
CPU time 0.76 seconds
Started Feb 28 05:20:03 PM PST 24
Finished Feb 28 05:20:04 PM PST 24
Peak memory 195524 kb
Host smart-d14e497e-6e34-4d05-923e-e29f5fa39767
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582742284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.582742284
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2807467820
Short name T63
Test name
Test status
Simulation time 104803392 ps
CPU time 2.58 seconds
Started Feb 28 05:20:11 PM PST 24
Finished Feb 28 05:20:13 PM PST 24
Peak memory 198000 kb
Host smart-044f7c6c-2948-4065-b537-40faea46df05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807467820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2807467820
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.622976912
Short name T223
Test name
Test status
Simulation time 119408818 ps
CPU time 0.83 seconds
Started Feb 28 05:19:59 PM PST 24
Finished Feb 28 05:20:00 PM PST 24
Peak memory 196356 kb
Host smart-69f5e38d-3085-4b5d-bdd5-0b13dfdf3c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622976912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.622976912
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3731818107
Short name T227
Test name
Test status
Simulation time 85937698 ps
CPU time 0.92 seconds
Started Feb 28 05:20:00 PM PST 24
Finished Feb 28 05:20:01 PM PST 24
Peak memory 197044 kb
Host smart-baebff71-6d77-494b-bade-f50d8c7a4543
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731818107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3731818107
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.471079698
Short name T126
Test name
Test status
Simulation time 11552363158 ps
CPU time 160.63 seconds
Started Feb 28 05:20:03 PM PST 24
Finished Feb 28 05:22:44 PM PST 24
Peak memory 198224 kb
Host smart-4f0dc3c5-1ccc-4ee2-aa8d-89065cacbdcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471079698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.471079698
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3221434091
Short name T277
Test name
Test status
Simulation time 20294431 ps
CPU time 0.58 seconds
Started Feb 28 05:20:08 PM PST 24
Finished Feb 28 05:20:09 PM PST 24
Peak memory 194112 kb
Host smart-c3d8e63e-83a7-4a5b-990c-6d2edbb9eb9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221434091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3221434091
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.557543083
Short name T66
Test name
Test status
Simulation time 75798869 ps
CPU time 0.76 seconds
Started Feb 28 05:20:05 PM PST 24
Finished Feb 28 05:20:06 PM PST 24
Peak memory 196004 kb
Host smart-576c11e6-8aed-441e-b0da-7f1f6b05c3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557543083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.557543083
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2457269192
Short name T563
Test name
Test status
Simulation time 748406009 ps
CPU time 5.47 seconds
Started Feb 28 05:20:08 PM PST 24
Finished Feb 28 05:20:14 PM PST 24
Peak memory 195664 kb
Host smart-64c4c2f4-218a-4868-82fe-df46ab792112
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457269192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2457269192
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3129021928
Short name T296
Test name
Test status
Simulation time 54742312 ps
CPU time 0.81 seconds
Started Feb 28 05:20:06 PM PST 24
Finished Feb 28 05:20:07 PM PST 24
Peak memory 196132 kb
Host smart-704d47a9-b029-415d-85d9-2340b6cdf252
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129021928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3129021928
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.912564484
Short name T707
Test name
Test status
Simulation time 102415350 ps
CPU time 0.97 seconds
Started Feb 28 05:20:04 PM PST 24
Finished Feb 28 05:20:06 PM PST 24
Peak memory 196760 kb
Host smart-429d4f3c-1513-4d20-8fb7-2d969be3a76f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912564484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.912564484
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1152244939
Short name T300
Test name
Test status
Simulation time 313118726 ps
CPU time 2.56 seconds
Started Feb 28 05:20:07 PM PST 24
Finished Feb 28 05:20:10 PM PST 24
Peak memory 198192 kb
Host smart-b9a281c9-9e25-44dd-9021-84fbdf3a9178
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152244939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1152244939
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1876618609
Short name T452
Test name
Test status
Simulation time 104358507 ps
CPU time 3.21 seconds
Started Feb 28 05:20:05 PM PST 24
Finished Feb 28 05:20:08 PM PST 24
Peak memory 195908 kb
Host smart-822fb2ca-3bfe-4f87-812c-739b48fe014d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876618609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1876618609
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2528699159
Short name T249
Test name
Test status
Simulation time 101012132 ps
CPU time 1.24 seconds
Started Feb 28 05:20:08 PM PST 24
Finished Feb 28 05:20:09 PM PST 24
Peak memory 197052 kb
Host smart-39575753-7c57-43a6-a0de-6230a785b1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528699159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2528699159
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1663380705
Short name T591
Test name
Test status
Simulation time 299505344 ps
CPU time 1.33 seconds
Started Feb 28 05:20:03 PM PST 24
Finished Feb 28 05:20:05 PM PST 24
Peak memory 195960 kb
Host smart-82738287-2f1c-4ee9-b68d-811362083ee1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663380705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1663380705
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.252862865
Short name T409
Test name
Test status
Simulation time 292759052 ps
CPU time 4.72 seconds
Started Feb 28 05:20:10 PM PST 24
Finished Feb 28 05:20:15 PM PST 24
Peak memory 198064 kb
Host smart-1e62bb74-b01b-479e-8cbc-63992b8fb363
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252862865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.252862865
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3426994726
Short name T532
Test name
Test status
Simulation time 22017240 ps
CPU time 0.84 seconds
Started Feb 28 05:20:11 PM PST 24
Finished Feb 28 05:20:12 PM PST 24
Peak memory 195308 kb
Host smart-35c7288c-be93-4db6-8acf-0de716da7ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426994726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3426994726
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2687275308
Short name T688
Test name
Test status
Simulation time 37213087 ps
CPU time 1.07 seconds
Started Feb 28 05:20:10 PM PST 24
Finished Feb 28 05:20:11 PM PST 24
Peak memory 195812 kb
Host smart-1175a839-086e-4858-a16e-8914ddce9909
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687275308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2687275308
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.181837825
Short name T115
Test name
Test status
Simulation time 2686012187 ps
CPU time 22.1 seconds
Started Feb 28 05:20:08 PM PST 24
Finished Feb 28 05:20:31 PM PST 24
Peak memory 198144 kb
Host smart-b5ee9e74-4935-4fb0-a76b-629890b45638
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181837825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.181837825
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2551943121
Short name T205
Test name
Test status
Simulation time 17445878 ps
CPU time 0.62 seconds
Started Feb 28 05:20:13 PM PST 24
Finished Feb 28 05:20:14 PM PST 24
Peak memory 194744 kb
Host smart-0a8ce7a9-ffc5-4922-aa89-3d502d7f2a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551943121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2551943121
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1958494672
Short name T242
Test name
Test status
Simulation time 24895275 ps
CPU time 0.83 seconds
Started Feb 28 05:20:09 PM PST 24
Finished Feb 28 05:20:10 PM PST 24
Peak memory 195388 kb
Host smart-d3d40739-9cec-453a-b19f-8b6a6ef95e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958494672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1958494672
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1111805302
Short name T12
Test name
Test status
Simulation time 606354562 ps
CPU time 11.22 seconds
Started Feb 28 05:20:12 PM PST 24
Finished Feb 28 05:20:23 PM PST 24
Peak memory 198160 kb
Host smart-4d4c0247-92c1-4695-88df-9b809ac52818
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111805302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1111805302
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3044492112
Short name T10
Test name
Test status
Simulation time 326159651 ps
CPU time 1.09 seconds
Started Feb 28 05:20:22 PM PST 24
Finished Feb 28 05:20:23 PM PST 24
Peak memory 196676 kb
Host smart-155a4e1a-9241-443d-aa2e-3fe3a6a1187e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044492112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3044492112
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.863956532
Short name T624
Test name
Test status
Simulation time 192465941 ps
CPU time 1.36 seconds
Started Feb 28 05:20:22 PM PST 24
Finished Feb 28 05:20:23 PM PST 24
Peak memory 196888 kb
Host smart-f04a9b7c-0b84-4a6f-ba99-2bfa460c7be6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863956532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.863956532
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.923177215
Short name T328
Test name
Test status
Simulation time 46833580 ps
CPU time 2.05 seconds
Started Feb 28 05:20:08 PM PST 24
Finished Feb 28 05:20:11 PM PST 24
Peak memory 198132 kb
Host smart-293aad8a-b94e-472c-873f-64ad3178dd7c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923177215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.923177215
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3900402609
Short name T427
Test name
Test status
Simulation time 43997668 ps
CPU time 1.2 seconds
Started Feb 28 05:20:08 PM PST 24
Finished Feb 28 05:20:10 PM PST 24
Peak memory 196508 kb
Host smart-2a639ca5-5497-424b-bb2c-5abe7fbd4c40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900402609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3900402609
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3705298786
Short name T548
Test name
Test status
Simulation time 48193244 ps
CPU time 1.04 seconds
Started Feb 28 05:20:09 PM PST 24
Finished Feb 28 05:20:10 PM PST 24
Peak memory 196068 kb
Host smart-2b7247a0-2263-4514-b327-ab661319ba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705298786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3705298786
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2759668721
Short name T154
Test name
Test status
Simulation time 85196367 ps
CPU time 1.03 seconds
Started Feb 28 05:20:11 PM PST 24
Finished Feb 28 05:20:12 PM PST 24
Peak memory 195876 kb
Host smart-0e29754f-f7b7-4b7c-be16-97c1cb3a398b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759668721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2759668721
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2054766280
Short name T1
Test name
Test status
Simulation time 441845855 ps
CPU time 2.94 seconds
Started Feb 28 05:20:11 PM PST 24
Finished Feb 28 05:20:15 PM PST 24
Peak memory 198080 kb
Host smart-75c27a88-413e-4d53-8e8c-385a8b5d4b25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054766280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2054766280
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3851093725
Short name T258
Test name
Test status
Simulation time 54420663 ps
CPU time 1.19 seconds
Started Feb 28 05:20:10 PM PST 24
Finished Feb 28 05:20:11 PM PST 24
Peak memory 195664 kb
Host smart-a098ef0f-37d2-4bf9-b96b-4c37727727f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851093725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3851093725
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.4290689729
Short name T628
Test name
Test status
Simulation time 42487018 ps
CPU time 1.24 seconds
Started Feb 28 05:20:09 PM PST 24
Finished Feb 28 05:20:10 PM PST 24
Peak memory 198136 kb
Host smart-c35ec009-2307-4ed6-802c-2f29ca06a377
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290689729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.4290689729
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.796467450
Short name T511
Test name
Test status
Simulation time 1847606346 ps
CPU time 22.86 seconds
Started Feb 28 05:20:22 PM PST 24
Finished Feb 28 05:20:45 PM PST 24
Peak memory 197820 kb
Host smart-72759fd2-9a97-47e3-a2bd-9b21bfffe1a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796467450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.796467450
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.69155277
Short name T54
Test name
Test status
Simulation time 799119367734 ps
CPU time 3169.09 seconds
Started Feb 28 05:20:22 PM PST 24
Finished Feb 28 06:13:11 PM PST 24
Peak memory 198060 kb
Host smart-f741a538-5db3-4301-9a32-e854ba9a594b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=69155277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.69155277
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.330285429
Short name T940
Test name
Test status
Simulation time 64643611 ps
CPU time 1.05 seconds
Started Feb 28 04:22:25 PM PST 24
Finished Feb 28 04:22:27 PM PST 24
Peak memory 198272 kb
Host smart-14abcc99-5302-4afb-ade1-180665e642a6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=330285429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.330285429
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2887997538
Short name T901
Test name
Test status
Simulation time 49660729 ps
CPU time 1.14 seconds
Started Feb 28 04:22:14 PM PST 24
Finished Feb 28 04:22:16 PM PST 24
Peak memory 198372 kb
Host smart-77fb2101-4236-4fb1-bd52-5e9470aab724
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887997538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2887997538
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3695475967
Short name T843
Test name
Test status
Simulation time 345389874 ps
CPU time 1.33 seconds
Started Feb 28 04:22:16 PM PST 24
Finished Feb 28 04:22:19 PM PST 24
Peak memory 198372 kb
Host smart-a54918f1-5d3f-42eb-9f85-4da0a6a5e66e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3695475967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3695475967
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.875076623
Short name T858
Test name
Test status
Simulation time 264317865 ps
CPU time 1.22 seconds
Started Feb 28 04:22:36 PM PST 24
Finished Feb 28 04:22:37 PM PST 24
Peak memory 197288 kb
Host smart-889596cd-6c4a-4452-8f26-e38ee2529a4c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875076623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.875076623
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.4039477201
Short name T932
Test name
Test status
Simulation time 102451567 ps
CPU time 0.93 seconds
Started Feb 28 04:22:26 PM PST 24
Finished Feb 28 04:22:27 PM PST 24
Peak memory 198160 kb
Host smart-e44c56fc-79af-40cd-9374-eeae69364281
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4039477201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.4039477201
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3356927117
Short name T936
Test name
Test status
Simulation time 77665293 ps
CPU time 1.27 seconds
Started Feb 28 04:22:10 PM PST 24
Finished Feb 28 04:22:11 PM PST 24
Peak memory 196384 kb
Host smart-33014a6e-867f-43e2-b036-98741134bcb7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356927117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3356927117
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1652113714
Short name T884
Test name
Test status
Simulation time 302471476 ps
CPU time 1.34 seconds
Started Feb 28 04:22:35 PM PST 24
Finished Feb 28 04:22:36 PM PST 24
Peak memory 197328 kb
Host smart-65e61179-c3b1-4fd6-8c21-afa044eb99a6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1652113714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1652113714
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.149184151
Short name T919
Test name
Test status
Simulation time 27122064 ps
CPU time 0.73 seconds
Started Feb 28 04:22:22 PM PST 24
Finished Feb 28 04:22:23 PM PST 24
Peak memory 196412 kb
Host smart-7163d0ba-c147-464c-9268-f3e2e93db757
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149184151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.149184151
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3021079495
Short name T928
Test name
Test status
Simulation time 115970125 ps
CPU time 1.1 seconds
Started Feb 28 04:22:24 PM PST 24
Finished Feb 28 04:22:25 PM PST 24
Peak memory 196800 kb
Host smart-dd606a48-e85d-4c75-b131-06e78d557436
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3021079495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3021079495
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1519740488
Short name T873
Test name
Test status
Simulation time 43824340 ps
CPU time 1.18 seconds
Started Feb 28 04:22:37 PM PST 24
Finished Feb 28 04:22:39 PM PST 24
Peak memory 197064 kb
Host smart-1be5bdc8-080f-46cc-9b65-cb8990dc494c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519740488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1519740488
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.425505052
Short name T860
Test name
Test status
Simulation time 23301373 ps
CPU time 0.76 seconds
Started Feb 28 04:22:16 PM PST 24
Finished Feb 28 04:22:19 PM PST 24
Peak memory 195552 kb
Host smart-962edbae-d73b-49bb-a5a4-4706ba9fae98
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=425505052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.425505052
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1250803182
Short name T864
Test name
Test status
Simulation time 226805224 ps
CPU time 1.18 seconds
Started Feb 28 04:22:14 PM PST 24
Finished Feb 28 04:22:17 PM PST 24
Peak memory 198372 kb
Host smart-00070391-2fd8-42f2-b4de-50e55104ceb3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250803182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1250803182
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3278533140
Short name T900
Test name
Test status
Simulation time 43989845 ps
CPU time 0.95 seconds
Started Feb 28 04:22:18 PM PST 24
Finished Feb 28 04:22:20 PM PST 24
Peak memory 196008 kb
Host smart-ae84bd91-149d-4aba-bada-8a0d0b6ce606
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3278533140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3278533140
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3315584340
Short name T861
Test name
Test status
Simulation time 44376305 ps
CPU time 0.76 seconds
Started Feb 28 04:22:20 PM PST 24
Finished Feb 28 04:22:21 PM PST 24
Peak memory 195596 kb
Host smart-99d17256-c1d1-4fc5-b605-f216a53857fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315584340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3315584340
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2288754366
Short name T915
Test name
Test status
Simulation time 126237119 ps
CPU time 1.29 seconds
Started Feb 28 04:22:43 PM PST 24
Finished Feb 28 04:22:45 PM PST 24
Peak memory 196928 kb
Host smart-b564da11-51e8-4b07-833a-eb628a554b47
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2288754366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2288754366
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3681999615
Short name T925
Test name
Test status
Simulation time 147179980 ps
CPU time 0.84 seconds
Started Feb 28 04:22:21 PM PST 24
Finished Feb 28 04:22:22 PM PST 24
Peak memory 196528 kb
Host smart-9b2c0817-fb99-44c2-a965-60aaa42ea179
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681999615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3681999615
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2291887861
Short name T921
Test name
Test status
Simulation time 41260015 ps
CPU time 0.91 seconds
Started Feb 28 04:22:22 PM PST 24
Finished Feb 28 04:22:23 PM PST 24
Peak memory 196676 kb
Host smart-5df12503-1726-4984-80ee-d22432b45843
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2291887861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2291887861
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4184840922
Short name T890
Test name
Test status
Simulation time 85199865 ps
CPU time 1.28 seconds
Started Feb 28 04:22:15 PM PST 24
Finished Feb 28 04:22:17 PM PST 24
Peak memory 197360 kb
Host smart-4de30de2-0893-4939-926c-f60dddbcd304
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184840922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4184840922
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.101274714
Short name T906
Test name
Test status
Simulation time 70658381 ps
CPU time 0.9 seconds
Started Feb 28 04:22:36 PM PST 24
Finished Feb 28 04:22:37 PM PST 24
Peak memory 195764 kb
Host smart-825d7f1a-0858-4074-a459-e33543ae9e6a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=101274714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.101274714
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.425179892
Short name T882
Test name
Test status
Simulation time 44302526 ps
CPU time 1.1 seconds
Started Feb 28 04:22:32 PM PST 24
Finished Feb 28 04:22:34 PM PST 24
Peak memory 196296 kb
Host smart-50d7ab2a-2307-40e1-96d6-7f35044fb417
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425179892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.425179892
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.764887563
Short name T877
Test name
Test status
Simulation time 246768775 ps
CPU time 1.24 seconds
Started Feb 28 04:22:18 PM PST 24
Finished Feb 28 04:22:24 PM PST 24
Peak memory 196824 kb
Host smart-6352d7a8-8684-4719-8357-9bb6732e039c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=764887563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.764887563
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3924574577
Short name T897
Test name
Test status
Simulation time 59110205 ps
CPU time 1.28 seconds
Started Feb 28 04:22:28 PM PST 24
Finished Feb 28 04:22:29 PM PST 24
Peak memory 196944 kb
Host smart-8e2ee89c-0ab9-4128-b2a1-370c51854b18
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924574577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3924574577
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.126678952
Short name T851
Test name
Test status
Simulation time 28960838 ps
CPU time 0.81 seconds
Started Feb 28 04:22:25 PM PST 24
Finished Feb 28 04:22:27 PM PST 24
Peak memory 195848 kb
Host smart-0d9d9817-8c73-467e-82f9-dbb400518a36
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=126678952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.126678952
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1652187408
Short name T899
Test name
Test status
Simulation time 75072303 ps
CPU time 0.86 seconds
Started Feb 28 04:22:27 PM PST 24
Finished Feb 28 04:22:29 PM PST 24
Peak memory 196364 kb
Host smart-bf351f1f-40c1-49ca-8b68-4a28a496afd8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652187408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1652187408
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2825656983
Short name T937
Test name
Test status
Simulation time 85602694 ps
CPU time 0.91 seconds
Started Feb 28 04:22:35 PM PST 24
Finished Feb 28 04:22:36 PM PST 24
Peak memory 197776 kb
Host smart-90900444-8301-4157-b940-e05801c6d571
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2825656983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2825656983
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.387966181
Short name T850
Test name
Test status
Simulation time 64644887 ps
CPU time 1.18 seconds
Started Feb 28 04:22:26 PM PST 24
Finished Feb 28 04:22:28 PM PST 24
Peak memory 197024 kb
Host smart-68068c2e-b307-469f-984e-3e9f793df8bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387966181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.387966181
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1257138932
Short name T910
Test name
Test status
Simulation time 26571334 ps
CPU time 0.94 seconds
Started Feb 28 04:22:27 PM PST 24
Finished Feb 28 04:22:28 PM PST 24
Peak memory 197700 kb
Host smart-79bcd42a-b096-4b94-971a-f48fb1018acb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1257138932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1257138932
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.237464114
Short name T907
Test name
Test status
Simulation time 118211608 ps
CPU time 1.2 seconds
Started Feb 28 04:24:28 PM PST 24
Finished Feb 28 04:24:30 PM PST 24
Peak memory 197092 kb
Host smart-4f6cfc6d-5126-4088-b918-6d1222020fbc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237464114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.237464114
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3368973820
Short name T841
Test name
Test status
Simulation time 51462625 ps
CPU time 1.03 seconds
Started Feb 28 04:24:06 PM PST 24
Finished Feb 28 04:24:08 PM PST 24
Peak memory 195692 kb
Host smart-94badc4c-7c42-49d1-9549-bc1459ae4d7d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3368973820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3368973820
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3376805383
Short name T863
Test name
Test status
Simulation time 304375681 ps
CPU time 1.41 seconds
Started Feb 28 04:22:36 PM PST 24
Finished Feb 28 04:22:37 PM PST 24
Peak memory 197256 kb
Host smart-1ff0402b-64ec-4d2f-92bb-c276487ddaf9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376805383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3376805383
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1023444502
Short name T939
Test name
Test status
Simulation time 105215171 ps
CPU time 1.14 seconds
Started Feb 28 04:22:37 PM PST 24
Finished Feb 28 04:22:38 PM PST 24
Peak memory 196248 kb
Host smart-12d70d4d-a055-4bf0-b46f-89a7f7292a1e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1023444502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1023444502
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.824861158
Short name T844
Test name
Test status
Simulation time 68967676 ps
CPU time 1.26 seconds
Started Feb 28 04:22:35 PM PST 24
Finished Feb 28 04:22:36 PM PST 24
Peak memory 198320 kb
Host smart-3f9b627f-5695-4d53-b570-8a63ad92d5d0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824861158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.824861158
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1861214054
Short name T917
Test name
Test status
Simulation time 22965163 ps
CPU time 0.73 seconds
Started Feb 28 04:22:23 PM PST 24
Finished Feb 28 04:22:23 PM PST 24
Peak memory 195700 kb
Host smart-2129ff32-46ea-4c50-b7e0-2e3805a01068
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1861214054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1861214054
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.689080531
Short name T842
Test name
Test status
Simulation time 160726595 ps
CPU time 1.38 seconds
Started Feb 28 04:24:32 PM PST 24
Finished Feb 28 04:24:34 PM PST 24
Peak memory 198232 kb
Host smart-001db4f9-0da9-4f15-97aa-52c7751823d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689080531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.689080531
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.166837541
Short name T916
Test name
Test status
Simulation time 547233311 ps
CPU time 1.26 seconds
Started Feb 28 04:22:13 PM PST 24
Finished Feb 28 04:22:15 PM PST 24
Peak memory 196936 kb
Host smart-945cd737-253a-4f1c-98bf-400f1d55d458
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=166837541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.166837541
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2732281549
Short name T878
Test name
Test status
Simulation time 120677310 ps
CPU time 1.09 seconds
Started Feb 28 04:22:33 PM PST 24
Finished Feb 28 04:22:35 PM PST 24
Peak memory 196232 kb
Host smart-fc131137-3fa3-4104-96db-f57307b0463a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732281549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2732281549
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.952310896
Short name T927
Test name
Test status
Simulation time 54919228 ps
CPU time 1.1 seconds
Started Feb 28 04:22:26 PM PST 24
Finished Feb 28 04:22:27 PM PST 24
Peak memory 198392 kb
Host smart-b96908e9-3d4e-4623-a1c1-b31bd9ecede5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=952310896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.952310896
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3482829743
Short name T885
Test name
Test status
Simulation time 67801644 ps
CPU time 0.97 seconds
Started Feb 28 04:22:32 PM PST 24
Finished Feb 28 04:22:33 PM PST 24
Peak memory 196056 kb
Host smart-57dd1533-7e3b-4585-aa5a-999eaf503cdc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482829743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3482829743
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1513900019
Short name T903
Test name
Test status
Simulation time 70674083 ps
CPU time 1 seconds
Started Feb 28 04:22:25 PM PST 24
Finished Feb 28 04:22:26 PM PST 24
Peak memory 197012 kb
Host smart-a595d6ca-4305-49bc-8bbd-e4a7cd8e5442
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1513900019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1513900019
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.884727024
Short name T896
Test name
Test status
Simulation time 80538736 ps
CPU time 1.19 seconds
Started Feb 28 04:22:33 PM PST 24
Finished Feb 28 04:22:35 PM PST 24
Peak memory 197144 kb
Host smart-4e06b5d8-9d9d-4095-8205-3ae0d1b53483
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884727024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.884727024
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2603151619
Short name T929
Test name
Test status
Simulation time 35273660 ps
CPU time 1.12 seconds
Started Feb 28 04:22:41 PM PST 24
Finished Feb 28 04:22:43 PM PST 24
Peak memory 198284 kb
Host smart-387ffd20-355d-4a7b-a253-3c17be5ef914
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2603151619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2603151619
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1470939893
Short name T881
Test name
Test status
Simulation time 145953023 ps
CPU time 0.87 seconds
Started Feb 28 04:22:33 PM PST 24
Finished Feb 28 04:22:34 PM PST 24
Peak memory 195600 kb
Host smart-a21e14e4-0740-446b-bf0a-bc674de8d05d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470939893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1470939893
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2098370908
Short name T889
Test name
Test status
Simulation time 563891558 ps
CPU time 1.13 seconds
Started Feb 28 04:22:27 PM PST 24
Finished Feb 28 04:22:28 PM PST 24
Peak memory 196864 kb
Host smart-eec3c3ca-8aae-45c7-b19f-a03e8edd451d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2098370908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2098370908
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.730080665
Short name T876
Test name
Test status
Simulation time 133354319 ps
CPU time 1.28 seconds
Started Feb 28 04:22:34 PM PST 24
Finished Feb 28 04:22:35 PM PST 24
Peak memory 197336 kb
Host smart-3ff57d90-cb2e-4089-b50c-41085fd62d5e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730080665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.730080665
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2750532112
Short name T918
Test name
Test status
Simulation time 151960745 ps
CPU time 0.9 seconds
Started Feb 28 04:24:31 PM PST 24
Finished Feb 28 04:24:33 PM PST 24
Peak memory 196764 kb
Host smart-e7cf4a3c-3c53-4778-96d8-54bf39c29915
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2750532112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2750532112
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3648635703
Short name T845
Test name
Test status
Simulation time 65349828 ps
CPU time 1.21 seconds
Started Feb 28 04:22:21 PM PST 24
Finished Feb 28 04:22:23 PM PST 24
Peak memory 197124 kb
Host smart-08590b85-fd5c-4e0b-ade0-3e79856b6a13
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648635703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3648635703
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1275177737
Short name T848
Test name
Test status
Simulation time 163987180 ps
CPU time 1.11 seconds
Started Feb 28 04:22:13 PM PST 24
Finished Feb 28 04:22:14 PM PST 24
Peak memory 198392 kb
Host smart-9f69130d-8cb9-4bfb-8dc6-8417f9924c37
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1275177737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1275177737
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.461354178
Short name T886
Test name
Test status
Simulation time 265346664 ps
CPU time 1.4 seconds
Started Feb 28 04:22:29 PM PST 24
Finished Feb 28 04:22:31 PM PST 24
Peak memory 197320 kb
Host smart-48bf446d-41e9-4147-976f-625372214aa6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461354178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.461354178
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2439096645
Short name T871
Test name
Test status
Simulation time 45594070 ps
CPU time 1.22 seconds
Started Feb 28 04:22:22 PM PST 24
Finished Feb 28 04:22:23 PM PST 24
Peak memory 196372 kb
Host smart-9f5ac3a5-8799-4be1-8d94-3d4eb5c36ef3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2439096645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2439096645
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.292205452
Short name T935
Test name
Test status
Simulation time 75374976 ps
CPU time 1.18 seconds
Started Feb 28 04:22:19 PM PST 24
Finished Feb 28 04:22:21 PM PST 24
Peak memory 196836 kb
Host smart-d0b4aa26-c5fb-4549-b764-43aa87045bf7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292205452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.292205452
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2939391126
Short name T923
Test name
Test status
Simulation time 97483079 ps
CPU time 1.46 seconds
Started Feb 28 04:22:17 PM PST 24
Finished Feb 28 04:22:20 PM PST 24
Peak memory 197048 kb
Host smart-1aba7f4c-9b73-466c-b22e-8459c9d40afb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2939391126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2939391126
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1037503467
Short name T892
Test name
Test status
Simulation time 58134231 ps
CPU time 1 seconds
Started Feb 28 04:22:24 PM PST 24
Finished Feb 28 04:22:25 PM PST 24
Peak memory 196832 kb
Host smart-18ff837e-795c-40cb-a25b-81fa4ee273d7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037503467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1037503467
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3548652457
Short name T895
Test name
Test status
Simulation time 61056408 ps
CPU time 1.08 seconds
Started Feb 28 04:22:15 PM PST 24
Finished Feb 28 04:22:17 PM PST 24
Peak memory 196932 kb
Host smart-2e72dc27-f37c-42cc-9461-9ab516b6a0a5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3548652457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3548652457
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2274493399
Short name T894
Test name
Test status
Simulation time 49517149 ps
CPU time 1.37 seconds
Started Feb 28 04:22:35 PM PST 24
Finished Feb 28 04:22:36 PM PST 24
Peak memory 198320 kb
Host smart-abad2ac5-c50f-437f-9e0f-c6427dedc1db
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274493399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2274493399
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.662686933
Short name T867
Test name
Test status
Simulation time 71689372 ps
CPU time 1.15 seconds
Started Feb 28 04:22:15 PM PST 24
Finished Feb 28 04:22:17 PM PST 24
Peak memory 196076 kb
Host smart-8b2116a4-7200-423e-bff5-49ea68706a0a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=662686933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.662686933
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2740383494
Short name T914
Test name
Test status
Simulation time 221166271 ps
CPU time 1.4 seconds
Started Feb 28 04:24:28 PM PST 24
Finished Feb 28 04:24:30 PM PST 24
Peak memory 198228 kb
Host smart-6a9fc427-9cf8-48ab-80d5-0c917dcf30a2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740383494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2740383494
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2159897102
Short name T926
Test name
Test status
Simulation time 85196094 ps
CPU time 1.36 seconds
Started Feb 28 04:22:49 PM PST 24
Finished Feb 28 04:22:51 PM PST 24
Peak memory 196736 kb
Host smart-4b13bd20-722d-49a1-81a3-4368ecd75ca2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2159897102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2159897102
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.464411655
Short name T875
Test name
Test status
Simulation time 611255791 ps
CPU time 1.39 seconds
Started Feb 28 04:22:27 PM PST 24
Finished Feb 28 04:22:29 PM PST 24
Peak memory 198348 kb
Host smart-ed701e26-7396-4f10-aaf4-1cf9253b3f81
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464411655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.464411655
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3556232815
Short name T908
Test name
Test status
Simulation time 66669565 ps
CPU time 0.7 seconds
Started Feb 28 04:22:24 PM PST 24
Finished Feb 28 04:22:25 PM PST 24
Peak memory 195732 kb
Host smart-f81f0de3-56ad-47d9-b2a5-c59a7587d21d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3556232815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3556232815
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.109557325
Short name T866
Test name
Test status
Simulation time 61751570 ps
CPU time 1.1 seconds
Started Feb 28 04:24:34 PM PST 24
Finished Feb 28 04:24:35 PM PST 24
Peak memory 197136 kb
Host smart-28488c61-68ca-4d52-9fa2-00be8074b3cc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109557325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.109557325
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2708108089
Short name T913
Test name
Test status
Simulation time 177310779 ps
CPU time 1 seconds
Started Feb 28 04:22:22 PM PST 24
Finished Feb 28 04:22:23 PM PST 24
Peak memory 196972 kb
Host smart-ac131987-af5f-468f-8b51-349c31f283f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2708108089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2708108089
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2896311473
Short name T931
Test name
Test status
Simulation time 183057626 ps
CPU time 0.97 seconds
Started Feb 28 04:22:17 PM PST 24
Finished Feb 28 04:22:20 PM PST 24
Peak memory 196248 kb
Host smart-81b4ca8b-c7f1-44e7-a679-4f2311d930b6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896311473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2896311473
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.661110766
Short name T883
Test name
Test status
Simulation time 121624315 ps
CPU time 0.95 seconds
Started Feb 28 04:22:38 PM PST 24
Finished Feb 28 04:22:39 PM PST 24
Peak memory 196268 kb
Host smart-320694f2-2220-4511-b8c1-fbda5ec144cf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=661110766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.661110766
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.474824762
Short name T880
Test name
Test status
Simulation time 228424869 ps
CPU time 1.45 seconds
Started Feb 28 04:22:30 PM PST 24
Finished Feb 28 04:22:33 PM PST 24
Peak memory 197068 kb
Host smart-b3bb894e-53ec-4a71-a283-47c25a270cf8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474824762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.474824762
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2412648543
Short name T888
Test name
Test status
Simulation time 237358612 ps
CPU time 1.03 seconds
Started Feb 28 04:24:35 PM PST 24
Finished Feb 28 04:24:36 PM PST 24
Peak memory 196864 kb
Host smart-fbc7e7d2-5e3c-4695-965e-0b3a69506a0b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2412648543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2412648543
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2476091793
Short name T911
Test name
Test status
Simulation time 67736533 ps
CPU time 0.85 seconds
Started Feb 28 04:22:33 PM PST 24
Finished Feb 28 04:22:34 PM PST 24
Peak memory 196336 kb
Host smart-60dc770b-3036-4f8a-abc6-9427dfb529f1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476091793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2476091793
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3713606400
Short name T870
Test name
Test status
Simulation time 149821948 ps
CPU time 1.2 seconds
Started Feb 28 04:22:20 PM PST 24
Finished Feb 28 04:22:22 PM PST 24
Peak memory 197292 kb
Host smart-d02dcc8b-39b8-4fbc-80dd-19ae3f41f2f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3713606400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3713606400
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1189930973
Short name T912
Test name
Test status
Simulation time 200512377 ps
CPU time 1.07 seconds
Started Feb 28 04:22:26 PM PST 24
Finished Feb 28 04:22:28 PM PST 24
Peak memory 196932 kb
Host smart-9f14cc44-8ab2-4287-b834-9910537c56fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189930973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1189930973
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1225481286
Short name T865
Test name
Test status
Simulation time 271515568 ps
CPU time 0.73 seconds
Started Feb 28 04:22:36 PM PST 24
Finished Feb 28 04:22:37 PM PST 24
Peak memory 195392 kb
Host smart-13178058-1413-48a6-aacf-3286e5a3bda0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1225481286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1225481286
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2060027062
Short name T849
Test name
Test status
Simulation time 260047639 ps
CPU time 1.27 seconds
Started Feb 28 04:22:29 PM PST 24
Finished Feb 28 04:22:31 PM PST 24
Peak memory 197632 kb
Host smart-94373906-260f-45fb-84ce-a587ef9de5c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060027062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2060027062
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.84392068
Short name T930
Test name
Test status
Simulation time 87790353 ps
CPU time 1.28 seconds
Started Feb 28 04:22:34 PM PST 24
Finished Feb 28 04:22:35 PM PST 24
Peak memory 197164 kb
Host smart-9636ac94-5608-4ae8-b090-f5df40890e4d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=84392068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.84392068
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1031079019
Short name T902
Test name
Test status
Simulation time 1125676050 ps
CPU time 1.21 seconds
Started Feb 28 04:22:47 PM PST 24
Finished Feb 28 04:22:53 PM PST 24
Peak memory 196844 kb
Host smart-d13cf3a3-f3f9-4a33-ac7c-a986d60a11e1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031079019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1031079019
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3142443044
Short name T869
Test name
Test status
Simulation time 125482942 ps
CPU time 0.89 seconds
Started Feb 28 04:22:31 PM PST 24
Finished Feb 28 04:22:32 PM PST 24
Peak memory 195752 kb
Host smart-8e56d1cc-49ca-4ff3-b90d-9f53bbba8445
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3142443044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3142443044
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.12237768
Short name T852
Test name
Test status
Simulation time 50713681 ps
CPU time 1.06 seconds
Started Feb 28 04:22:27 PM PST 24
Finished Feb 28 04:22:28 PM PST 24
Peak memory 197160 kb
Host smart-5c5cf782-71b8-46bc-9e4e-7cd3da0f36a6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12237768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.12237768
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3049407620
Short name T933
Test name
Test status
Simulation time 50665749 ps
CPU time 1.37 seconds
Started Feb 28 04:22:22 PM PST 24
Finished Feb 28 04:22:23 PM PST 24
Peak memory 198336 kb
Host smart-50af8cca-91b8-4269-ac06-6ff5a914e692
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3049407620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3049407620
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.220594287
Short name T887
Test name
Test status
Simulation time 87862898 ps
CPU time 1.3 seconds
Started Feb 28 04:22:37 PM PST 24
Finished Feb 28 04:22:38 PM PST 24
Peak memory 197020 kb
Host smart-84434619-6d0b-4d8f-b1f5-34a5cce58ba1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220594287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.220594287
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3098450464
Short name T857
Test name
Test status
Simulation time 150420738 ps
CPU time 1.15 seconds
Started Feb 28 04:22:39 PM PST 24
Finished Feb 28 04:22:40 PM PST 24
Peak memory 196844 kb
Host smart-ec04c249-042f-4dc6-a690-27e1ecea9269
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3098450464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3098450464
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4061380186
Short name T934
Test name
Test status
Simulation time 100857834 ps
CPU time 0.76 seconds
Started Feb 28 04:22:28 PM PST 24
Finished Feb 28 04:22:29 PM PST 24
Peak memory 195424 kb
Host smart-162ef275-1f63-4ec2-8269-b07649454709
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061380186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4061380186
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1243463799
Short name T854
Test name
Test status
Simulation time 307585063 ps
CPU time 1.12 seconds
Started Feb 28 04:24:34 PM PST 24
Finished Feb 28 04:24:35 PM PST 24
Peak memory 195708 kb
Host smart-2cf2881b-2053-4226-aefc-e6e7a7488538
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1243463799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1243463799
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.891136774
Short name T862
Test name
Test status
Simulation time 58429645 ps
CPU time 1.58 seconds
Started Feb 28 04:22:51 PM PST 24
Finished Feb 28 04:22:53 PM PST 24
Peak memory 197128 kb
Host smart-039ad43b-5349-45c6-ba3f-9120a4604a8e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891136774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.891136774
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1370729532
Short name T855
Test name
Test status
Simulation time 52826244 ps
CPU time 1.11 seconds
Started Feb 28 04:22:39 PM PST 24
Finished Feb 28 04:22:41 PM PST 24
Peak memory 196804 kb
Host smart-5c237bb6-3e2e-4646-8ef4-b79295fd7e56
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1370729532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1370729532
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3384501286
Short name T846
Test name
Test status
Simulation time 260721716 ps
CPU time 1.15 seconds
Started Feb 28 04:22:35 PM PST 24
Finished Feb 28 04:22:36 PM PST 24
Peak memory 196080 kb
Host smart-db63906a-3482-4c93-9209-796a111ece77
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384501286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3384501286
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.205615148
Short name T905
Test name
Test status
Simulation time 58566011 ps
CPU time 0.99 seconds
Started Feb 28 04:22:37 PM PST 24
Finished Feb 28 04:22:38 PM PST 24
Peak memory 197108 kb
Host smart-c2fe7ac9-6437-451d-8590-a29ffa838681
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=205615148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.205615148
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1863299698
Short name T874
Test name
Test status
Simulation time 73318851 ps
CPU time 1.21 seconds
Started Feb 28 04:24:28 PM PST 24
Finished Feb 28 04:24:29 PM PST 24
Peak memory 198256 kb
Host smart-b96d636a-56aa-40ad-a5ea-64fe1d1c98bc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863299698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1863299698
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.144882651
Short name T922
Test name
Test status
Simulation time 287294466 ps
CPU time 1.47 seconds
Started Feb 28 04:22:26 PM PST 24
Finished Feb 28 04:22:28 PM PST 24
Peak memory 197168 kb
Host smart-918ba6ca-6420-4462-a31a-eb8a7f9c1b9c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=144882651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.144882651
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.743038087
Short name T891
Test name
Test status
Simulation time 242276904 ps
CPU time 1.11 seconds
Started Feb 28 04:23:29 PM PST 24
Finished Feb 28 04:23:31 PM PST 24
Peak memory 197016 kb
Host smart-d99379b5-356f-431e-a86a-15e420850743
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743038087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.743038087
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3439825605
Short name T872
Test name
Test status
Simulation time 56713169 ps
CPU time 1.46 seconds
Started Feb 28 04:22:38 PM PST 24
Finished Feb 28 04:22:39 PM PST 24
Peak memory 197020 kb
Host smart-fa6aeb09-278b-4399-8fd4-8577c6563c68
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3439825605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3439825605
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3936560364
Short name T847
Test name
Test status
Simulation time 269815885 ps
CPU time 1.27 seconds
Started Feb 28 04:22:31 PM PST 24
Finished Feb 28 04:22:33 PM PST 24
Peak memory 197420 kb
Host smart-f7169854-9064-4a4c-ab8c-f46a829a0734
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936560364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3936560364
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2387219000
Short name T853
Test name
Test status
Simulation time 126415923 ps
CPU time 1.18 seconds
Started Feb 28 04:24:33 PM PST 24
Finished Feb 28 04:24:35 PM PST 24
Peak memory 196852 kb
Host smart-8a2c77e5-48ce-4689-ac4f-5c45943803a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2387219000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2387219000
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.270074128
Short name T924
Test name
Test status
Simulation time 274966311 ps
CPU time 1.21 seconds
Started Feb 28 04:22:39 PM PST 24
Finished Feb 28 04:22:40 PM PST 24
Peak memory 197112 kb
Host smart-2ac9110c-93f7-47c0-b653-6180b2ff0578
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270074128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.270074128
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3535861711
Short name T920
Test name
Test status
Simulation time 70999611 ps
CPU time 1.16 seconds
Started Feb 28 04:22:25 PM PST 24
Finished Feb 28 04:22:27 PM PST 24
Peak memory 196136 kb
Host smart-8c9f3b5e-4886-4463-a498-2013842a58ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3535861711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3535861711
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1815969108
Short name T909
Test name
Test status
Simulation time 85057175 ps
CPU time 1.27 seconds
Started Feb 28 04:22:35 PM PST 24
Finished Feb 28 04:22:37 PM PST 24
Peak memory 197312 kb
Host smart-03286158-38f1-41c9-9ac5-94968541e4d0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815969108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1815969108
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.335085367
Short name T859
Test name
Test status
Simulation time 38459431 ps
CPU time 1.07 seconds
Started Feb 28 04:22:28 PM PST 24
Finished Feb 28 04:22:30 PM PST 24
Peak memory 196288 kb
Host smart-c6a728ee-160a-4153-b99e-4316e021b18b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=335085367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.335085367
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3861069495
Short name T893
Test name
Test status
Simulation time 59761886 ps
CPU time 0.81 seconds
Started Feb 28 04:22:37 PM PST 24
Finished Feb 28 04:22:38 PM PST 24
Peak memory 195840 kb
Host smart-0d742c32-536d-4fa1-bdc3-7faa0fe84107
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861069495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3861069495
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3502328255
Short name T879
Test name
Test status
Simulation time 186437519 ps
CPU time 1.44 seconds
Started Feb 28 04:22:39 PM PST 24
Finished Feb 28 04:22:41 PM PST 24
Peak memory 196032 kb
Host smart-7f15ec49-4eae-41d5-a354-d068fe4a706e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3502328255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3502328255
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.384822261
Short name T938
Test name
Test status
Simulation time 286143572 ps
CPU time 1.28 seconds
Started Feb 28 04:22:30 PM PST 24
Finished Feb 28 04:22:33 PM PST 24
Peak memory 197324 kb
Host smart-fb415861-b4c4-4630-806d-f5e2bb9b41ad
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384822261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.384822261
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.341367860
Short name T856
Test name
Test status
Simulation time 64558532 ps
CPU time 1.24 seconds
Started Feb 28 04:22:28 PM PST 24
Finished Feb 28 04:22:29 PM PST 24
Peak memory 198348 kb
Host smart-898b9bb4-8b60-451a-b30a-433bd11eb702
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=341367860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.341367860
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2153258430
Short name T904
Test name
Test status
Simulation time 35261865 ps
CPU time 1.01 seconds
Started Feb 28 04:22:38 PM PST 24
Finished Feb 28 04:22:40 PM PST 24
Peak memory 197984 kb
Host smart-bf151be6-332e-4ea1-99cc-18721d5def0f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153258430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2153258430
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3370608085
Short name T868
Test name
Test status
Simulation time 90104643 ps
CPU time 0.81 seconds
Started Feb 28 04:22:25 PM PST 24
Finished Feb 28 04:22:26 PM PST 24
Peak memory 196528 kb
Host smart-3609cc77-0d9e-45e3-961e-7aa5cd3b97fe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3370608085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3370608085
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3507622790
Short name T898
Test name
Test status
Simulation time 277435593 ps
CPU time 1.12 seconds
Started Feb 28 04:22:01 PM PST 24
Finished Feb 28 04:22:03 PM PST 24
Peak memory 196216 kb
Host smart-1d4965fc-468d-4803-8ae5-9eda0ca89b58
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507622790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3507622790
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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