Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[1]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[2]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[3]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[4]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[5]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[6]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[7]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[8]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[9]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[10]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[11]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[12]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[13]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[14]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[15]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[16]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[17]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[18]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[19]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[20]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[21]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[22]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[23]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[24]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[25]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[26]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[27]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[28]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[29]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[30]	5175662	1			T22	22451		T23	18081		T24	1
all_pins[31]	5175662	1			T22	22451		T23	18081		T24	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	102862042	1			T22	444239		T23	360780		T24	32
values[0x1]	62759142	1			T22	274193		T23	217812		T25	2554
transitions[0x0=>0x1]	37616111	1			T22	162097		T23	130706		T25	1596
transitions[0x1=>0x0]	37615967	1			T22	162097		T23	130705		T25	1596

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3213529	1			T22	13894		T23	11577		T24	1
all_pins[0]	values[0x1]	1962133	1			T22	8557		T23	6504		T25	54
all_pins[0]	transitions[0x0=>0x1]	1213294	1			T22	5136		T23	4083		T25	30
all_pins[0]	transitions[0x1=>0x0]	1215934	1			T22	5668		T23	4528		T25	48
all_pins[1]	values[0x0]	3210950	1			T22	13575		T23	11595		T24	1
all_pins[1]	values[0x1]	1964712	1			T22	8876		T23	6486		T25	106
all_pins[1]	transitions[0x0=>0x1]	1174333	1			T22	5332		T23	3988		T25	85
all_pins[1]	transitions[0x1=>0x0]	1171754	1			T22	5013		T23	4006		T25	33
all_pins[2]	values[0x0]	3213621	1			T22	14085		T23	11374		T24	1
all_pins[2]	values[0x1]	1962041	1			T22	8366		T23	6707		T25	72
all_pins[2]	transitions[0x0=>0x1]	1172476	1			T22	4620		T23	4116		T25	41
all_pins[2]	transitions[0x1=>0x0]	1175147	1			T22	5130		T23	3895		T25	75
all_pins[3]	values[0x0]	3218040	1			T22	13932		T23	11014		T24	1
all_pins[3]	values[0x1]	1957622	1			T22	8519		T23	7067		T25	100
all_pins[3]	transitions[0x0=>0x1]	1171751	1			T22	4998		T23	4416		T25	64
all_pins[3]	transitions[0x1=>0x0]	1176170	1			T22	4845		T23	4056		T25	36
all_pins[4]	values[0x0]	3219388	1			T22	13843		T23	11391		T24	1
all_pins[4]	values[0x1]	1956274	1			T22	8608		T23	6690		T25	53
all_pins[4]	transitions[0x0=>0x1]	1173898	1			T22	4985		T23	3873		T25	39
all_pins[4]	transitions[0x1=>0x0]	1175246	1			T22	4896		T23	4250		T25	86
all_pins[5]	values[0x0]	3217049	1			T22	13833		T23	11695		T24	1
all_pins[5]	values[0x1]	1958613	1			T22	8618		T23	6386		T25	81
all_pins[5]	transitions[0x0=>0x1]	1175797	1			T22	4998		T23	3681		T25	62
all_pins[5]	transitions[0x1=>0x0]	1173458	1			T22	4988		T23	3985		T25	34
all_pins[6]	values[0x0]	3209100	1			T22	14293		T23	11262		T24	1
all_pins[6]	values[0x1]	1966562	1			T22	8158		T23	6819		T25	100
all_pins[6]	transitions[0x0=>0x1]	1180559	1			T22	4754		T23	4336		T25	69
all_pins[6]	transitions[0x1=>0x0]	1172610	1			T22	5214		T23	3903		T25	50
all_pins[7]	values[0x0]	3216373	1			T22	14208		T23	11131		T24	1
all_pins[7]	values[0x1]	1959289	1			T22	8243		T23	6950		T25	70
all_pins[7]	transitions[0x0=>0x1]	1169701	1			T22	4942		T23	4070		T25	27
all_pins[7]	transitions[0x1=>0x0]	1176974	1			T22	4857		T23	3939		T25	57
all_pins[8]	values[0x0]	3216626	1			T22	13726		T23	11178		T24	1
all_pins[8]	values[0x1]	1959036	1			T22	8725		T23	6903		T25	78
all_pins[8]	transitions[0x0=>0x1]	1173613	1			T22	5463		T23	4053		T25	54
all_pins[8]	transitions[0x1=>0x0]	1173866	1			T22	4981		T23	4100		T25	46
all_pins[9]	values[0x0]	3216327	1			T22	13827		T23	11248		T24	1
all_pins[9]	values[0x1]	1959335	1			T22	8624		T23	6833		T25	77
all_pins[9]	transitions[0x0=>0x1]	1172720	1			T22	4938		T23	4002		T25	56
all_pins[9]	transitions[0x1=>0x0]	1172421	1			T22	5039		T23	4072		T25	57
all_pins[10]	values[0x0]	3212605	1			T22	13631		T23	11201		T24	1
all_pins[10]	values[0x1]	1963057	1			T22	8820		T23	6880		T25	89
all_pins[10]	transitions[0x0=>0x1]	1176411	1			T22	5280		T23	4093		T25	55
all_pins[10]	transitions[0x1=>0x0]	1172689	1			T22	5084		T23	4046		T25	43
all_pins[11]	values[0x0]	3214700	1			T22	13938		T23	10781		T24	1
all_pins[11]	values[0x1]	1960962	1			T22	8513		T23	7300		T25	78
all_pins[11]	transitions[0x0=>0x1]	1172986	1			T22	4980		T23	4429		T25	25
all_pins[11]	transitions[0x1=>0x0]	1175081	1			T22	5287		T23	4009		T25	36
all_pins[12]	values[0x0]	3214952	1			T22	13957		T23	11036		T24	1
all_pins[12]	values[0x1]	1960710	1			T22	8494		T23	7045		T25	85
all_pins[12]	transitions[0x0=>0x1]	1173708	1			T22	5137		T23	3993		T25	51
all_pins[12]	transitions[0x1=>0x0]	1173960	1			T22	5156		T23	4248		T25	44
all_pins[13]	values[0x0]	3216054	1			T22	13720		T23	11539		T24	1
all_pins[13]	values[0x1]	1959608	1			T22	8731		T23	6542		T25	63
all_pins[13]	transitions[0x0=>0x1]	1173551	1			T22	5070		T23	3765		T25	36
all_pins[13]	transitions[0x1=>0x0]	1174653	1			T22	4833		T23	4268		T25	58
all_pins[14]	values[0x0]	3218214	1			T22	13990		T23	11219		T24	1
all_pins[14]	values[0x1]	1957448	1			T22	8461		T23	6862		T25	87
all_pins[14]	transitions[0x0=>0x1]	1172199	1			T22	4909		T23	4119		T25	58
all_pins[14]	transitions[0x1=>0x0]	1174359	1			T22	5179		T23	3799		T25	34
all_pins[15]	values[0x0]	3213617	1			T22	13583		T23	11167		T24	1
all_pins[15]	values[0x1]	1962045	1			T22	8868		T23	6914		T25	78
all_pins[15]	transitions[0x0=>0x1]	1176147	1			T22	5364		T23	4142		T25	64
all_pins[15]	transitions[0x1=>0x0]	1171550	1			T22	4957		T23	4090		T25	73
all_pins[16]	values[0x0]	3212177	1			T22	13560		T23	11429		T24	1
all_pins[16]	values[0x1]	1963485	1			T22	8891		T23	6652		T25	84
all_pins[16]	transitions[0x0=>0x1]	1174751	1			T22	5325		T23	3941		T25	47
all_pins[16]	transitions[0x1=>0x0]	1173311	1			T22	5302		T23	4203		T25	41
all_pins[17]	values[0x0]	3213894	1			T22	14106		T23	10910		T24	1
all_pins[17]	values[0x1]	1961768	1			T22	8345		T23	7171		T25	65
all_pins[17]	transitions[0x0=>0x1]	1174135	1			T22	4747		T23	4250		T25	32
all_pins[17]	transitions[0x1=>0x0]	1175852	1			T22	5293		T23	3731		T25	51
all_pins[18]	values[0x0]	3218915	1			T22	13502		T23	11323		T24	1
all_pins[18]	values[0x1]	1956747	1			T22	8949		T23	6758		T25	87
all_pins[18]	transitions[0x0=>0x1]	1172596	1			T22	5432		T23	4045		T25	60
all_pins[18]	transitions[0x1=>0x0]	1177617	1			T22	4828		T23	4458		T25	38
all_pins[19]	values[0x0]	3210367	1			T22	13911		T23	11549		T24	1
all_pins[19]	values[0x1]	1965295	1			T22	8540		T23	6532		T25	93
all_pins[19]	transitions[0x0=>0x1]	1178027	1			T22	4903		T23	3928		T25	60
all_pins[19]	transitions[0x1=>0x0]	1169479	1			T22	5312		T23	4154		T25	54
all_pins[20]	values[0x0]	3210800	1			T22	13795		T23	11060		T24	1
all_pins[20]	values[0x1]	1964862	1			T22	8656		T23	7021		T25	49
all_pins[20]	transitions[0x0=>0x1]	1175996	1			T22	5182		T23	4349		T25	15
all_pins[20]	transitions[0x1=>0x0]	1176429	1			T22	5066		T23	3860		T25	59
all_pins[21]	values[0x0]	3219700	1			T22	13944		T23	10980		T24	1
all_pins[21]	values[0x1]	1955962	1			T22	8507		T23	7101		T25	84
all_pins[21]	transitions[0x0=>0x1]	1171929	1			T22	4850		T23	4155		T25	55
all_pins[21]	transitions[0x1=>0x0]	1180829	1			T22	4999		T23	4075		T25	20
all_pins[22]	values[0x0]	3216287	1			T22	14149		T23	11085		T24	1
all_pins[22]	values[0x1]	1959375	1			T22	8302		T23	6996		T25	65
all_pins[22]	transitions[0x0=>0x1]	1174369	1			T22	5140		T23	3930		T25	41
all_pins[22]	transitions[0x1=>0x0]	1170956	1			T22	5345		T23	4035		T25	60
all_pins[23]	values[0x0]	3210516	1			T22	14331		T23	11538		T24	1
all_pins[23]	values[0x1]	1965146	1			T22	8120		T23	6543		T25	108
all_pins[23]	transitions[0x0=>0x1]	1175853	1			T22	4920		T23	3880		T25	84
all_pins[23]	transitions[0x1=>0x0]	1170082	1			T22	5102		T23	4333		T25	41
all_pins[24]	values[0x0]	3216388	1			T22	13863		T23	11665		T24	1
all_pins[24]	values[0x1]	1959274	1			T22	8588		T23	6416		T25	99
all_pins[24]	transitions[0x0=>0x1]	1171064	1			T22	5135		T23	4046		T25	56
all_pins[24]	transitions[0x1=>0x0]	1176936	1			T22	4667		T23	4173		T25	65
all_pins[25]	values[0x0]	3218299	1			T22	13984		T23	11073		T24	1
all_pins[25]	values[0x1]	1957363	1			T22	8467		T23	7008		T25	105
all_pins[25]	transitions[0x0=>0x1]	1173501	1			T22	4935		T23	4339		T25	49
all_pins[25]	transitions[0x1=>0x0]	1175412	1			T22	5056		T23	3747		T25	43
all_pins[26]	values[0x0]	3211193	1			T22	13917		T23	11292		T24	1
all_pins[26]	values[0x1]	1964469	1			T22	8534		T23	6789		T25	66
all_pins[26]	transitions[0x0=>0x1]	1177736	1			T22	5090		T23	4035		T25	33
all_pins[26]	transitions[0x1=>0x0]	1170630	1			T22	5023		T23	4254		T25	72
all_pins[27]	values[0x0]	3215751	1			T22	13793		T23	11330		T24	1
all_pins[27]	values[0x1]	1959911	1			T22	8658		T23	6751		T25	72
all_pins[27]	transitions[0x0=>0x1]	1170904	1			T22	4850		T23	4191		T25	49
all_pins[27]	transitions[0x1=>0x0]	1175462	1			T22	4726		T23	4229		T25	43
all_pins[28]	values[0x0]	3207425	1			T22	13971		T23	11325		T24	1
all_pins[28]	values[0x1]	1968237	1			T22	8480		T23	6756		T25	84
all_pins[28]	transitions[0x0=>0x1]	1178865	1			T22	5002		T23	4092		T25	54
all_pins[28]	transitions[0x1=>0x0]	1170539	1			T22	5180		T23	4087		T25	42
all_pins[29]	values[0x0]	3216927	1			T22	14113		T23	11363		T24	1
all_pins[29]	values[0x1]	1958735	1			T22	8338		T23	6718		T25	75
all_pins[29]	transitions[0x0=>0x1]	1169742	1			T22	4965		T23	4120		T25	53
all_pins[29]	transitions[0x1=>0x0]	1179244	1			T22	5107		T23	4158		T25	62
all_pins[30]	values[0x0]	3211513	1			T22	13903		T23	11319		T24	1
all_pins[30]	values[0x1]	1964149	1			T22	8548		T23	6762		T25	75
all_pins[30]	transitions[0x0=>0x1]	1179791	1			T22	5253		T23	4140		T25	43
all_pins[30]	transitions[0x1=>0x0]	1174377	1			T22	5043		T23	4096		T25	43
all_pins[31]	values[0x0]	3210745	1			T22	13362		T23	11131		T24	1
all_pins[31]	values[0x1]	1964917	1			T22	9089		T23	6950		T25	72
all_pins[31]	transitions[0x0=>0x1]	1173708	1			T22	5462		T23	4106		T25	49
all_pins[31]	transitions[0x1=>0x0]	1172940	1			T22	4921		T23	3918		T25	52