Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[1]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[2]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[3]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[4]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[5]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[6]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[7]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[8]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[9]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[10]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[11]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[12]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[13]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[14]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[15]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[16]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[17]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[18]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[19]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[20]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[21]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[22]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[23]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[24]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[25]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[26]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[27]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[28]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[29]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[30]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[31]	16403422	1			T22	71224		T23	50146		T24	522

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

312416934

1

T22

146526

T23

571983

T24

13026

auto[1]

212492570

1

T22

813906

T23

103268

T24

3678

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

420647162

1

T22

181711

T23

126334

T24

12321

auto[1]

104262342

1

T22

462049

T23

341330

T24

4383

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

389835813

1

T22

168237

T23

117909

T24

8406

auto[1]

135073691

1

T22

596797

T23

425573

T24

8298

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	6066885	1			T22	28160		T23	12006		T24	262
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4474189	1			T22	17430		T23	19092		T24	35
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1644998	1			T22	7465		T23	5531		T24	59
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2059776	1			T22	10304		T23	527		T24	108
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	535622	1			T22	691		T23	7612		T24	8
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1621952	1			T22	7174		T23	5378		T24	50
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	6074500	1			T22	28287		T23	11977		T24	144
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4473168	1			T22	17514		T23	19678		T24	28
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1640073	1			T22	7266		T23	5530		T24	86
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2058712	1			T22	10288		T23	407		T24	136
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	533639	1			T22	690		T23	7402		T24	25
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1623330	1			T22	7179		T23	5152		T24	103
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	6068930	1			T22	27517		T23	12017		T24	231
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4471719	1			T22	17434		T23	19561		T24	24
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1643406	1			T22	7502		T23	5080		T24	80
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2062445	1			T22	10605		T23	450		T24	143
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	534746	1			T22	737		T23	7716		T24	15
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1622176	1			T22	7429		T23	5322		T24	29
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	6055590	1			T22	27153		T23	12050		T24	169
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4489298	1			T22	17611		T23	19207		T24	26
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1639770	1			T22	7201		T23	5141		T24	88
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2059972	1			T22	10715		T23	556		T24	143
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	536274	1			T22	804		T23	7785		T24	27
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1622518	1			T22	7740		T23	5407		T24	69
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	6061450	1			T22	27649		T23	12143		T24	125
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4474924	1			T22	17496		T23	19348		T24	11
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1643419	1			T22	7163		T23	5613		T24	67
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2060572	1			T22	11228		T23	448		T24	230
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	539618	1			T22	763		T23	7182		T24	27
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1623439	1			T22	6925		T23	5412		T24	62
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	6055701	1			T22	27787		T23	11977		T24	177
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4483530	1			T22	17626		T23	19214		T24	28
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1637594	1			T22	7587		T23	5344		T24	102
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2070444	1			T22	10268		T23	516		T24	162
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	533022	1			T22	755		T23	7697		T24	16
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1623131	1			T22	7201		T23	5398		T24	37
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	6056948	1			T22	27878		T23	12050		T24	118
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4483527	1			T22	17272		T23	19467		T24	10
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1636669	1			T22	7112		T23	5171		T24	60
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2061583	1			T22	11002		T23	495		T24	182
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	538940	1			T22	762		T23	7700		T24	36
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1625755	1			T22	7198		T23	5263		T24	116
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	6076452	1			T22	27308		T23	12025		T24	184
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4477098	1			T22	17489		T23	19515		T24	31
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1636146	1			T22	7258		T23	5490		T24	87
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2054090	1			T22	10936		T23	435		T24	129
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	536986	1			T22	784		T23	7442		T24	19
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1622650	1			T22	7449		T23	5239		T24	72
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	6059358	1			T22	27857		T23	12017		T24	145
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4479719	1			T22	17600		T23	19794		T24	23
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1642350	1			T22	7325		T23	5386		T24	87
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2062940	1			T22	10655		T23	442		T24	188
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	533932	1			T22	718		T23	7346		T24	32
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1625123	1			T22	7069		T23	5161		T24	47
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	6057473	1			T22	28050		T23	12112		T24	165
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4482633	1			T22	17544		T23	19307		T24	15
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1637896	1			T22	7744		T23	5575		T24	68
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2066040	1			T22	10084		T23	491		T24	198
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	535599	1			T22	737		T23	7153		T24	29
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1623781	1			T22	7065		T23	5508		T24	47
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	6058813	1			T22	27838		T23	12030		T24	132
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4478195	1			T22	17562		T23	19241		T24	15
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1645759	1			T22	7001		T23	5371		T24	49
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2061919	1			T22	11093		T23	465		T24	179
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	531632	1			T22	683		T23	7613		T24	25
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1627104	1			T22	7047		T23	5426		T24	122
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	6060920	1			T22	27537		T23	12096		T24	198
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4475780	1			T22	17423		T23	19442		T24	27
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1635176	1			T22	7141		T23	5304		T24	80
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2067646	1			T22	11049		T23	427		T24	123
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	539033	1			T22	886		T23	7546		T24	18
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1624867	1			T22	7188		T23	5331		T24	76
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	6055781	1			T22	27906		T23	12066		T24	163
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4479635	1			T22	17458		T23	19306		T24	19
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1637924	1			T22	7382		T23	5219		T24	49
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2069865	1			T22	10551		T23	511		T24	183
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	536555	1			T22	688		T23	7632		T24	29
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1623662	1			T22	7239		T23	5412		T24	79
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	6065335	1			T22	27448		T23	11952		T24	112
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4484754	1			T22	17501		T23	19455		T24	11
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1638747	1			T22	7205		T23	5480		T24	56
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2056281	1			T22	11093		T23	472		T24	226
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	534553	1			T22	833		T23	7615		T24	23
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1623752	1			T22	7144		T23	5172		T24	94
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	6057322	1			T22	27758		T23	12073		T24	167
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4476267	1			T22	17580		T23	19289		T24	10
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1643216	1			T22	7319		T23	5344		T24	64
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2065946	1			T22	10719		T23	501		T24	204
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	535882	1			T22	719		T23	7354		T24	34
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1624789	1			T22	7129		T23	5585		T24	43
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	6053506	1			T22	27926		T23	12071		T24	210
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4493950	1			T22	17421		T23	19506		T24	30
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1640984	1			T22	7318		T23	5258		T24	68
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2059162	1			T22	10488		T23	490		T24	143
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	534409	1			T22	773		T23	7717		T24	14
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1621411	1			T22	7298		T23	5104		T24	57
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	6058771	1			T22	27811		T23	12068		T24	170
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4488394	1			T22	17639		T23	19506		T24	23
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1632996	1			T22	7091		T23	5664		T24	58
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2065533	1			T22	10719		T23	472		T24	170
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	539350	1			T22	730		T23	7242		T24	19
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1618378	1			T22	7234		T23	5194		T24	82
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	6074094	1			T22	28050		T23	11965		T24	102
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4477229	1			T22	17383		T23	19664		T24	12
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1633397	1			T22	7186		T23	5364		T24	74
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2065120	1			T22	10737		T23	480		T24	218
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	537631	1			T22	834		T23	7552		T24	37
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1615951	1			T22	7034		T23	5121		T24	79
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	6054080	1			T22	27901		T23	11982		T24	156
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4491822	1			T22	17308		T23	19498		T24	30
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1632277	1			T22	7112		T23	5291		T24	49
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2069879	1			T22	11195		T23	464		T24	202
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	535903	1			T22	800		T23	7489		T24	36
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1619461	1			T22	6908		T23	5422		T24	49
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	6064460	1			T22	27951		T23	12094		T24	163
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4490148	1			T22	17472		T23	19712		T24	29
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1632832	1			T22	7161		T23	5438		T24	67
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2063516	1			T22	10784		T23	441		T24	150
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	535639	1			T22	776		T23	7303		T24	30
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1616827	1			T22	7080		T23	5158		T24	83
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	6061990	1			T22	28209		T23	12128		T24	208
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4485641	1			T22	17541		T23	19555		T24	25
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1629635	1			T22	6782		T23	5522		T24	87
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2066142	1			T22	10706		T23	408		T24	129
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	538204	1			T22	749		T23	7244		T24	20
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1621810	1			T22	7237		T23	5289		T24	53
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	6049287	1			T22	27763		T23	12146		T24	211
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4493926	1			T22	17563		T23	19570		T24	26
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1630227	1			T22	7560		T23	5300		T24	40
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2076474	1			T22	10611		T23	521		T24	175
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	535602	1			T22	768		T23	7469		T24	21
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1617906	1			T22	6959		T23	5140		T24	49
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	6072400	1			T22	27623		T23	11999		T24	194
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4479814	1			T22	17575		T23	19472		T24	27
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1636844	1			T22	7319		T23	5278		T24	74
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2060453	1			T22	10672		T23	476		T24	132
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	536998	1			T22	707		T23	7638		T24	21
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1616913	1			T22	7328		T23	5283		T24	74
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	6057944	1			T22	27226		T23	12160		T24	183
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4486227	1			T22	17525		T23	19007		T24	28
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1638487	1			T22	7258		T23	5257		T24	104
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2068520	1			T22	10821		T23	494		T24	147
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	534662	1			T22	820		T23	7751		T24	22
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1617582	1			T22	7574		T23	5477		T24	38
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	6068737	1			T22	27921		T23	11899		T24	253
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4488281	1			T22	17661		T23	19958		T24	43
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1640671	1			T22	7590		T23	5196		T24	67
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2058197	1			T22	10394		T23	505		T24	106
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	534854	1			T22	778		T23	7569		T24	13
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1612682	1			T22	6880		T23	5019		T24	40
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	6070625	1			T22	28581		T23	12146		T24	114
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4472608	1			T22	17668		T23	19221		T24	14
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1632054	1			T22	7314		T23	5458		T24	50
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2066226	1			T22	9975		T23	518		T24	204
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	539706	1			T22	678		T23	7215		T24	28
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1622203	1			T22	7008		T23	5588		T24	112
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	6050042	1			T22	27879		T23	11996		T24	199
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4492526	1			T22	17609		T23	19326		T24	26
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1631252	1			T22	7302		T23	5278		T24	86
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2068774	1			T22	10755		T23	477		T24	135
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	537932	1			T22	762		T23	7680		T24	22
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1622896	1			T22	6917		T23	5389		T24	54
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	6069399	1			T22	27490		T23	11967		T24	189
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4479947	1			T22	17485		T23	19553		T24	18
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1638398	1			T22	7134		T23	5430		T24	57
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2058918	1			T22	10937		T23	474		T24	164
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	536969	1			T22	830		T23	7447		T24	25
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1619791	1			T22	7348		T23	5275		T24	69
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	6064869	1			T22	27624		T23	12009		T24	172
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4483978	1			T22	17392		T23	19532		T24	33
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1638713	1			T22	6929		T23	5369		T24	69
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2066362	1			T22	11115		T23	499		T24	162
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	535580	1			T22	806		T23	7592		T24	20
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1613920	1			T22	7358		T23	5145		T24	66
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	6048770	1			T22	27491		T23	11931		T24	165
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4500270	1			T22	17294		T23	19388		T24	18
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1636638	1			T22	7140		T23	5264		T24	62
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2061356	1			T22	11190		T23	525		T24	184
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	535859	1			T22	775		T23	7754		T24	26
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1620529	1			T22	7334		T23	5284		T24	67
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	6068791	1			T22	28612		T23	11974		T24	143
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4478136	1			T22	17483		T23	19796		T24	6
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1635213	1			T22	7165		T23	5193		T24	44
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2066623	1			T22	10238		T23	430		T24	199
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	536885	1			T22	706		T23	7496		T24	40
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1617774	1			T22	7020		T23	5257		T24	90
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	6059707	1			T22	27679		T23	12078		T24	142
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4497211	1			T22	17417		T23	19194		T24	27
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1628578	1			T22	7493		T23	5382		T24	74
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2066179	1			T22	10940		T23	441		T24	194
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	535807	1			T22	864		T23	7553		T24	22
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1615940	1			T22	6831		T23	5498		T24	63

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal