Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[1]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[2]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[3]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[4]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[5]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[6]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[7]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[8]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[9]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[10]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[11]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[12]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[13]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[14]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[15]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[16]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[17]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[18]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[19]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[20]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[21]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[22]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[23]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[24]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[25]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[26]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[27]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[28]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[29]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[30]	16403422	1			T22	71224		T23	50146		T24	522
bins_for_gpio_bits[31]	16403422	1			T22	71224		T23	50146		T24	522

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

312416934

1

T22

146526

T23

571983

T24

13026

auto[1]

212492570

1

T22

813906

T23

103268

T24

3678

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

312412040

1

T22

146513

T23

572085

T24

13017

auto[1]

212497464

1

T22

814037

T23

103258

T24

3687

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	9481895	1			T22	44579		T23	17036		T24	419
bins_for_gpio_bits[0]	auto[0]	auto[1]	289611	1			T22	1345		T23	1033		T24	9
bins_for_gpio_bits[0]	auto[1]	auto[0]	289764	1			T22	1350		T23	1028		T24	10
bins_for_gpio_bits[0]	auto[1]	auto[1]	6342152	1			T22	23950		T23	31049		T24	84
bins_for_gpio_bits[1]	auto[0]	auto[0]	9483690	1			T22	44519		T23	16876		T24	348
bins_for_gpio_bits[1]	auto[0]	auto[1]	289484	1			T22	1320		T23	1040		T24	17
bins_for_gpio_bits[1]	auto[1]	auto[0]	289595	1			T22	1322		T23	1038		T24	18
bins_for_gpio_bits[1]	auto[1]	auto[1]	6340653	1			T22	24063		T23	31192		T24	139
bins_for_gpio_bits[2]	auto[0]	auto[0]	9485114	1			T22	44291		T23	16544		T24	447
bins_for_gpio_bits[2]	auto[0]	auto[1]	289500	1			T22	1328		T23	1008		T24	7
bins_for_gpio_bits[2]	auto[1]	auto[0]	289667	1			T22	1333		T23	1003		T24	7
bins_for_gpio_bits[2]	auto[1]	auto[1]	6339141	1			T22	24272		T23	31591		T24	61
bins_for_gpio_bits[3]	auto[0]	auto[0]	9466340	1			T22	43698		T23	16772		T24	388
bins_for_gpio_bits[3]	auto[0]	auto[1]	288811	1			T22	1366		T23	979		T24	12
bins_for_gpio_bits[3]	auto[1]	auto[0]	288992	1			T22	1371		T23	975		T24	12
bins_for_gpio_bits[3]	auto[1]	auto[1]	6359279	1			T22	24789		T23	31420		T24	110
bins_for_gpio_bits[4]	auto[0]	auto[0]	9476111	1			T22	44728		T23	17184		T24	406
bins_for_gpio_bits[4]	auto[0]	auto[1]	289205	1			T22	1306		T23	1025		T24	16
bins_for_gpio_bits[4]	auto[1]	auto[0]	289330	1			T22	1312		T23	1020		T24	16
bins_for_gpio_bits[4]	auto[1]	auto[1]	6348776	1			T22	23878		T23	30917		T24	84
bins_for_gpio_bits[5]	auto[0]	auto[0]	9474246	1			T22	44338		T23	16847		T24	431
bins_for_gpio_bits[5]	auto[0]	auto[1]	289305	1			T22	1299		T23	993		T24	10
bins_for_gpio_bits[5]	auto[1]	auto[0]	289493	1			T22	1304		T23	990		T24	10
bins_for_gpio_bits[5]	auto[1]	auto[1]	6350378	1			T22	24283		T23	31316		T24	71
bins_for_gpio_bits[6]	auto[0]	auto[0]	9465925	1			T22	44634		T23	16723		T24	344
bins_for_gpio_bits[6]	auto[0]	auto[1]	289109	1			T22	1356		T23	996		T24	15
bins_for_gpio_bits[6]	auto[1]	auto[0]	289275	1			T22	1358		T23	993		T24	16
bins_for_gpio_bits[6]	auto[1]	auto[1]	6359113	1			T22	23876		T23	31434		T24	147
bins_for_gpio_bits[7]	auto[0]	auto[0]	9477938	1			T22	44142		T23	16932		T24	385
bins_for_gpio_bits[7]	auto[0]	auto[1]	288612	1			T22	1353		T23	1022		T24	14
bins_for_gpio_bits[7]	auto[1]	auto[0]	288750	1			T22	1360		T23	1018		T24	15
bins_for_gpio_bits[7]	auto[1]	auto[1]	6348122	1			T22	24369		T23	31174		T24	108
bins_for_gpio_bits[8]	auto[0]	auto[0]	9474974	1			T22	44523		T23	16811		T24	410
bins_for_gpio_bits[8]	auto[0]	auto[1]	289562	1			T22	1314		T23	1037		T24	10
bins_for_gpio_bits[8]	auto[1]	auto[0]	289674	1			T22	1314		T23	1034		T24	10
bins_for_gpio_bits[8]	auto[1]	auto[1]	6349212	1			T22	24073		T23	31264		T24	92
bins_for_gpio_bits[9]	auto[0]	auto[0]	9471422	1			T22	44579		T23	17111		T24	421
bins_for_gpio_bits[9]	auto[0]	auto[1]	289818	1			T22	1293		T23	1071		T24	10
bins_for_gpio_bits[9]	auto[1]	auto[0]	289987	1			T22	1299		T23	1067		T24	10
bins_for_gpio_bits[9]	auto[1]	auto[1]	6352195	1			T22	24053		T23	30897		T24	81
bins_for_gpio_bits[10]	auto[0]	auto[0]	9476955	1			T22	44592		T23	16820		T24	344
bins_for_gpio_bits[10]	auto[0]	auto[1]	289412	1			T22	1338		T23	1048		T24	15
bins_for_gpio_bits[10]	auto[1]	auto[0]	289536	1			T22	1340		T23	1046		T24	16
bins_for_gpio_bits[10]	auto[1]	auto[1]	6347519	1			T22	23954		T23	31232		T24	147
bins_for_gpio_bits[11]	auto[0]	auto[0]	9474335	1			T22	44415		T23	16814		T24	389
bins_for_gpio_bits[11]	auto[0]	auto[1]	289260	1			T22	1311		T23	1019		T24	12
bins_for_gpio_bits[11]	auto[1]	auto[0]	289407	1			T22	1312		T23	1013		T24	12
bins_for_gpio_bits[11]	auto[1]	auto[1]	6350420	1			T22	24186		T23	31300		T24	109
bins_for_gpio_bits[12]	auto[0]	auto[0]	9473669	1			T22	44504		T23	16776		T24	382
bins_for_gpio_bits[12]	auto[0]	auto[1]	289722	1			T22	1330		T23	1021		T24	13
bins_for_gpio_bits[12]	auto[1]	auto[0]	289901	1			T22	1335		T23	1020		T24	13
bins_for_gpio_bits[12]	auto[1]	auto[1]	6350130	1			T22	24055		T23	31329		T24	114
bins_for_gpio_bits[13]	auto[0]	auto[0]	9471826	1			T22	44422		T23	16869		T24	381
bins_for_gpio_bits[13]	auto[0]	auto[1]	288372	1			T22	1320		T23	1038		T24	13
bins_for_gpio_bits[13]	auto[1]	auto[0]	288537	1			T22	1324		T23	1035		T24	13
bins_for_gpio_bits[13]	auto[1]	auto[1]	6354687	1			T22	24158		T23	31204		T24	115
bins_for_gpio_bits[14]	auto[0]	auto[0]	9476197	1			T22	44451		T23	16905		T24	424
bins_for_gpio_bits[14]	auto[0]	auto[1]	290124	1			T22	1341		T23	1017		T24	11
bins_for_gpio_bits[14]	auto[1]	auto[0]	290287	1			T22	1345		T23	1013		T24	11
bins_for_gpio_bits[14]	auto[1]	auto[1]	6346814	1			T22	24087		T23	31211		T24	76
bins_for_gpio_bits[15]	auto[0]	auto[0]	9463993	1			T22	44401		T23	16814		T24	411
bins_for_gpio_bits[15]	auto[0]	auto[1]	289527	1			T22	1325		T23	1008		T24	10
bins_for_gpio_bits[15]	auto[1]	auto[0]	289659	1			T22	1331		T23	1005		T24	10
bins_for_gpio_bits[15]	auto[1]	auto[1]	6360243	1			T22	24167		T23	31319		T24	91
bins_for_gpio_bits[16]	auto[0]	auto[0]	9467892	1			T22	44293		T23	17157		T24	385
bins_for_gpio_bits[16]	auto[0]	auto[1]	289273	1			T22	1322		T23	1049		T24	13
bins_for_gpio_bits[16]	auto[1]	auto[0]	289408	1			T22	1328		T23	1047		T24	13
bins_for_gpio_bits[16]	auto[1]	auto[1]	6356849	1			T22	24281		T23	30893		T24	111
bins_for_gpio_bits[17]	auto[0]	auto[0]	9483173	1			T22	44655		T23	16775		T24	381
bins_for_gpio_bits[17]	auto[0]	auto[1]	289257	1			T22	1310		T23	1037		T24	13
bins_for_gpio_bits[17]	auto[1]	auto[0]	289438	1			T22	1318		T23	1034		T24	13
bins_for_gpio_bits[17]	auto[1]	auto[1]	6341554	1			T22	23941		T23	31300		T24	115
bins_for_gpio_bits[18]	auto[0]	auto[0]	9466068	1			T22	44896		T23	16713		T24	398
bins_for_gpio_bits[18]	auto[0]	auto[1]	290020	1			T22	1306		T23	1026		T24	9
bins_for_gpio_bits[18]	auto[1]	auto[0]	290168	1			T22	1312		T23	1024		T24	9
bins_for_gpio_bits[18]	auto[1]	auto[1]	6357166	1			T22	23710		T23	31383		T24	106
bins_for_gpio_bits[19]	auto[0]	auto[0]	9471265	1			T22	44605		T23	16938		T24	366
bins_for_gpio_bits[19]	auto[0]	auto[1]	289391	1			T22	1287		T23	1040		T24	14
bins_for_gpio_bits[19]	auto[1]	auto[0]	289543	1			T22	1291		T23	1035		T24	14
bins_for_gpio_bits[19]	auto[1]	auto[1]	6353223	1			T22	24041		T23	31133		T24	128
bins_for_gpio_bits[20]	auto[0]	auto[0]	9467466	1			T22	44413		T23	17039		T24	414
bins_for_gpio_bits[20]	auto[0]	auto[1]	290188	1			T22	1282		T23	1021		T24	9
bins_for_gpio_bits[20]	auto[1]	auto[0]	290301	1			T22	1284		T23	1019		T24	10
bins_for_gpio_bits[20]	auto[1]	auto[1]	6355467	1			T22	24245		T23	31067		T24	89
bins_for_gpio_bits[21]	auto[0]	auto[0]	9466495	1			T22	44619		T23	16906		T24	414
bins_for_gpio_bits[21]	auto[0]	auto[1]	289370	1			T22	1313		T23	1064		T24	11
bins_for_gpio_bits[21]	auto[1]	auto[0]	289493	1			T22	1315		T23	1061		T24	12
bins_for_gpio_bits[21]	auto[1]	auto[1]	6358064	1			T22	23977		T23	31115		T24	85
bins_for_gpio_bits[22]	auto[0]	auto[0]	9480035	1			T22	44263		T23	16723		T24	388
bins_for_gpio_bits[22]	auto[0]	auto[1]	289502	1			T22	1346		T23	1031		T24	12
bins_for_gpio_bits[22]	auto[1]	auto[0]	289662	1			T22	1351		T23	1030		T24	12
bins_for_gpio_bits[22]	auto[1]	auto[1]	6344223	1			T22	24264		T23	31362		T24	110
bins_for_gpio_bits[23]	auto[0]	auto[0]	9475394	1			T22	43919		T23	16936		T24	427
bins_for_gpio_bits[23]	auto[0]	auto[1]	289394	1			T22	1382		T23	976		T24	7
bins_for_gpio_bits[23]	auto[1]	auto[0]	289557	1			T22	1386		T23	975		T24	7
bins_for_gpio_bits[23]	auto[1]	auto[1]	6349077	1			T22	24537		T23	31259		T24	81
bins_for_gpio_bits[24]	auto[0]	auto[0]	9478205	1			T22	44631		T23	16592		T24	417
bins_for_gpio_bits[24]	auto[0]	auto[1]	289236	1			T22	1267		T23	1011		T24	9
bins_for_gpio_bits[24]	auto[1]	auto[0]	289400	1			T22	1274		T23	1008		T24	9
bins_for_gpio_bits[24]	auto[1]	auto[1]	6346581	1			T22	24052		T23	31535		T24	87
bins_for_gpio_bits[25]	auto[0]	auto[0]	9479890	1			T22	44576		T23	17075		T24	350
bins_for_gpio_bits[25]	auto[0]	auto[1]	288830	1			T22	1294		T23	1050		T24	18
bins_for_gpio_bits[25]	auto[1]	auto[0]	289015	1			T22	1294		T23	1047		T24	18
bins_for_gpio_bits[25]	auto[1]	auto[1]	6345687	1			T22	24060		T23	30974		T24	136
bins_for_gpio_bits[26]	auto[0]	auto[0]	9460195	1			T22	44661		T23	16742		T24	410
bins_for_gpio_bits[26]	auto[0]	auto[1]	289691	1			T22	1270		T23	1013		T24	10
bins_for_gpio_bits[26]	auto[1]	auto[0]	289873	1			T22	1275		T23	1009		T24	10
bins_for_gpio_bits[26]	auto[1]	auto[1]	6363663	1			T22	24018		T23	31382		T24	92
bins_for_gpio_bits[27]	auto[0]	auto[0]	9477388	1			T22	44200		T23	16844		T24	397
bins_for_gpio_bits[27]	auto[0]	auto[1]	289149	1			T22	1359		T23	1032		T24	12
bins_for_gpio_bits[27]	auto[1]	auto[0]	289327	1			T22	1361		T23	1027		T24	13
bins_for_gpio_bits[27]	auto[1]	auto[1]	6347558	1			T22	24304		T23	31243		T24	100
bins_for_gpio_bits[28]	auto[0]	auto[0]	9480739	1			T22	44328		T23	16840		T24	392
bins_for_gpio_bits[28]	auto[0]	auto[1]	289044	1			T22	1336		T23	1040		T24	11
bins_for_gpio_bits[28]	auto[1]	auto[0]	289205	1			T22	1340		T23	1037		T24	11
bins_for_gpio_bits[28]	auto[1]	auto[1]	6344434	1			T22	24220		T23	31229		T24	108
bins_for_gpio_bits[29]	auto[0]	auto[0]	9457166	1			T22	44485		T23	16697		T24	402
bins_for_gpio_bits[29]	auto[0]	auto[1]	289475	1			T22	1330		T23	1024		T24	9
bins_for_gpio_bits[29]	auto[1]	auto[0]	289598	1			T22	1336		T23	1023		T24	9
bins_for_gpio_bits[29]	auto[1]	auto[1]	6367183	1			T22	24073		T23	31402		T24	102
bins_for_gpio_bits[30]	auto[0]	auto[0]	9481034	1			T22	44747		T23	16613		T24	368
bins_for_gpio_bits[30]	auto[0]	auto[1]	289429	1			T22	1264		T23	987		T24	18
bins_for_gpio_bits[30]	auto[1]	auto[0]	289593	1			T22	1268		T23	984		T24	18
bins_for_gpio_bits[30]	auto[1]	auto[1]	6343366	1			T22	23945		T23	31562		T24	118
bins_for_gpio_bits[31]	auto[0]	auto[0]	9465762	1			T22	44864		T23	16902		T24	397
bins_for_gpio_bits[31]	auto[0]	auto[1]	288560	1			T22	1247		T23	1003		T24	12
bins_for_gpio_bits[31]	auto[1]	auto[0]	288702	1			T22	1248		T23	999		T24	13
bins_for_gpio_bits[31]	auto[1]	auto[1]	6360398	1			T22	23865		T23	31242		T24	100