Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9467478 |
1 |
|
|
T22 |
38236 |
|
T23 |
29855 |
|
T24 |
275 |
| auto[1] |
7297015 |
1 |
|
|
T22 |
34535 |
|
T23 |
21937 |
|
T25 |
287 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15822628 |
1 |
|
|
T22 |
68222 |
|
T23 |
48768 |
|
T24 |
275 |
| auto[1] |
941865 |
1 |
|
|
T22 |
4549 |
|
T23 |
3024 |
|
T25 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9457842 |
1 |
|
|
T22 |
39646 |
|
T23 |
29562 |
|
T24 |
275 |
| auto[1] |
7306651 |
1 |
|
|
T22 |
33125 |
|
T23 |
22230 |
|
T25 |
253 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3195576 |
1 |
|
|
T22 |
13839 |
|
T23 |
9316 |
|
T25 |
128 |
| auto[1] |
auto[0] |
auto[1] |
473563 |
1 |
|
|
T22 |
2097 |
|
T23 |
1444 |
|
T25 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3169210 |
1 |
|
|
T22 |
14737 |
|
T23 |
9890 |
|
T25 |
118 |
| auto[1] |
auto[1] |
auto[1] |
468302 |
1 |
|
|
T22 |
2452 |
|
T23 |
1580 |
|
T25 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9417191 |
1 |
|
|
T22 |
39142 |
|
T23 |
30558 |
|
T24 |
275 |
| auto[1] |
7347302 |
1 |
|
|
T22 |
33629 |
|
T23 |
21234 |
|
T25 |
427 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15820308 |
1 |
|
|
T22 |
68220 |
|
T23 |
48736 |
|
T24 |
275 |
| auto[1] |
944185 |
1 |
|
|
T22 |
4551 |
|
T23 |
3056 |
|
T25 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9446345 |
1 |
|
|
T22 |
40068 |
|
T23 |
28498 |
|
T24 |
275 |
| auto[1] |
7318148 |
1 |
|
|
T22 |
32703 |
|
T23 |
23294 |
|
T25 |
499 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3166046 |
1 |
|
|
T22 |
13518 |
|
T23 |
10646 |
|
T25 |
209 |
| auto[1] |
auto[0] |
auto[1] |
468711 |
1 |
|
|
T22 |
2131 |
|
T23 |
1662 |
|
T25 |
6 |
| auto[1] |
auto[1] |
auto[0] |
3207917 |
1 |
|
|
T22 |
14634 |
|
T23 |
9592 |
|
T25 |
278 |
| auto[1] |
auto[1] |
auto[1] |
475474 |
1 |
|
|
T22 |
2420 |
|
T23 |
1394 |
|
T25 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9462909 |
1 |
|
|
T22 |
38746 |
|
T23 |
28336 |
|
T24 |
275 |
| auto[1] |
7301584 |
1 |
|
|
T22 |
34025 |
|
T23 |
23456 |
|
T25 |
363 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15820011 |
1 |
|
|
T22 |
67979 |
|
T23 |
48624 |
|
T24 |
275 |
| auto[1] |
944482 |
1 |
|
|
T22 |
4792 |
|
T23 |
3168 |
|
T25 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9443712 |
1 |
|
|
T22 |
38653 |
|
T23 |
27823 |
|
T24 |
275 |
| auto[1] |
7320781 |
1 |
|
|
T22 |
34118 |
|
T23 |
23969 |
|
T25 |
380 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3195070 |
1 |
|
|
T22 |
14595 |
|
T23 |
9669 |
|
T25 |
188 |
| auto[1] |
auto[0] |
auto[1] |
472758 |
1 |
|
|
T22 |
2370 |
|
T23 |
1429 |
|
T25 |
10 |
| auto[1] |
auto[1] |
auto[0] |
3181229 |
1 |
|
|
T22 |
14731 |
|
T23 |
11132 |
|
T25 |
177 |
| auto[1] |
auto[1] |
auto[1] |
471724 |
1 |
|
|
T22 |
2422 |
|
T23 |
1739 |
|
T25 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9456174 |
1 |
|
|
T22 |
40795 |
|
T23 |
28175 |
|
T24 |
275 |
| auto[1] |
7308319 |
1 |
|
|
T22 |
31976 |
|
T23 |
23617 |
|
T25 |
308 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15827119 |
1 |
|
|
T22 |
68334 |
|
T23 |
48864 |
|
T24 |
275 |
| auto[1] |
937374 |
1 |
|
|
T22 |
4437 |
|
T23 |
2928 |
|
T25 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9477626 |
1 |
|
|
T22 |
40951 |
|
T23 |
29953 |
|
T24 |
275 |
| auto[1] |
7286867 |
1 |
|
|
T22 |
31820 |
|
T23 |
21839 |
|
T25 |
345 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3180985 |
1 |
|
|
T22 |
14522 |
|
T23 |
8228 |
|
T25 |
183 |
| auto[1] |
auto[0] |
auto[1] |
469284 |
1 |
|
|
T22 |
2285 |
|
T23 |
1253 |
|
T25 |
9 |
| auto[1] |
auto[1] |
auto[0] |
3168508 |
1 |
|
|
T22 |
12861 |
|
T23 |
10683 |
|
T25 |
146 |
| auto[1] |
auto[1] |
auto[1] |
468090 |
1 |
|
|
T22 |
2152 |
|
T23 |
1675 |
|
T25 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9455089 |
1 |
|
|
T22 |
38327 |
|
T23 |
28828 |
|
T24 |
275 |
| auto[1] |
7309404 |
1 |
|
|
T22 |
34444 |
|
T23 |
22964 |
|
T25 |
313 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15822191 |
1 |
|
|
T22 |
68063 |
|
T23 |
48889 |
|
T24 |
275 |
| auto[1] |
942302 |
1 |
|
|
T22 |
4708 |
|
T23 |
2903 |
|
T25 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9468820 |
1 |
|
|
T22 |
39332 |
|
T23 |
30057 |
|
T24 |
275 |
| auto[1] |
7295673 |
1 |
|
|
T22 |
33439 |
|
T23 |
21735 |
|
T25 |
326 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3164825 |
1 |
|
|
T22 |
13313 |
|
T23 |
8823 |
|
T25 |
180 |
| auto[1] |
auto[0] |
auto[1] |
469216 |
1 |
|
|
T22 |
2168 |
|
T23 |
1338 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3188546 |
1 |
|
|
T22 |
15418 |
|
T23 |
10009 |
|
T25 |
143 |
| auto[1] |
auto[1] |
auto[1] |
473086 |
1 |
|
|
T22 |
2540 |
|
T23 |
1565 |
|
T25 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9465063 |
1 |
|
|
T22 |
39755 |
|
T23 |
30980 |
|
T24 |
275 |
| auto[1] |
7299430 |
1 |
|
|
T22 |
33016 |
|
T23 |
20812 |
|
T25 |
347 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15814604 |
1 |
|
|
T22 |
68261 |
|
T23 |
48756 |
|
T24 |
275 |
| auto[1] |
949889 |
1 |
|
|
T22 |
4510 |
|
T23 |
3036 |
|
T25 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9413854 |
1 |
|
|
T22 |
40228 |
|
T23 |
29929 |
|
T24 |
275 |
| auto[1] |
7350639 |
1 |
|
|
T22 |
32543 |
|
T23 |
21863 |
|
T25 |
304 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3207437 |
1 |
|
|
T22 |
13509 |
|
T23 |
10514 |
|
T25 |
170 |
| auto[1] |
auto[0] |
auto[1] |
476857 |
1 |
|
|
T22 |
2214 |
|
T23 |
1720 |
|
T25 |
9 |
| auto[1] |
auto[1] |
auto[0] |
3193313 |
1 |
|
|
T22 |
14524 |
|
T23 |
8313 |
|
T25 |
123 |
| auto[1] |
auto[1] |
auto[1] |
473032 |
1 |
|
|
T22 |
2296 |
|
T23 |
1316 |
|
T25 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9473765 |
1 |
|
|
T22 |
40462 |
|
T23 |
29969 |
|
T24 |
275 |
| auto[1] |
7290728 |
1 |
|
|
T22 |
32309 |
|
T23 |
21823 |
|
T25 |
345 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15816041 |
1 |
|
|
T22 |
68409 |
|
T23 |
48795 |
|
T24 |
275 |
| auto[1] |
948452 |
1 |
|
|
T22 |
4362 |
|
T23 |
2997 |
|
T25 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9416308 |
1 |
|
|
T22 |
40582 |
|
T23 |
29195 |
|
T24 |
275 |
| auto[1] |
7348185 |
1 |
|
|
T22 |
32189 |
|
T23 |
22597 |
|
T25 |
321 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3220203 |
1 |
|
|
T22 |
14456 |
|
T23 |
9824 |
|
T25 |
164 |
| auto[1] |
auto[0] |
auto[1] |
477763 |
1 |
|
|
T22 |
2339 |
|
T23 |
1502 |
|
T25 |
10 |
| auto[1] |
auto[1] |
auto[0] |
3179530 |
1 |
|
|
T22 |
13371 |
|
T23 |
9776 |
|
T25 |
142 |
| auto[1] |
auto[1] |
auto[1] |
470689 |
1 |
|
|
T22 |
2023 |
|
T23 |
1495 |
|
T25 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9420816 |
1 |
|
|
T22 |
39756 |
|
T23 |
28241 |
|
T24 |
275 |
| auto[1] |
7343677 |
1 |
|
|
T22 |
33015 |
|
T23 |
23551 |
|
T25 |
299 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15819357 |
1 |
|
|
T22 |
68232 |
|
T23 |
48928 |
|
T24 |
275 |
| auto[1] |
945136 |
1 |
|
|
T22 |
4539 |
|
T23 |
2864 |
|
T25 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9434315 |
1 |
|
|
T22 |
40203 |
|
T23 |
29723 |
|
T24 |
275 |
| auto[1] |
7330178 |
1 |
|
|
T22 |
32568 |
|
T23 |
22069 |
|
T25 |
313 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3181813 |
1 |
|
|
T22 |
14150 |
|
T23 |
9234 |
|
T25 |
176 |
| auto[1] |
auto[0] |
auto[1] |
470621 |
1 |
|
|
T22 |
2334 |
|
T23 |
1334 |
|
T25 |
7 |
| auto[1] |
auto[1] |
auto[0] |
3203229 |
1 |
|
|
T22 |
13879 |
|
T23 |
9971 |
|
T25 |
129 |
| auto[1] |
auto[1] |
auto[1] |
474515 |
1 |
|
|
T22 |
2205 |
|
T23 |
1530 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9413216 |
1 |
|
|
T22 |
39578 |
|
T23 |
29493 |
|
T24 |
275 |
| auto[1] |
7351277 |
1 |
|
|
T22 |
33193 |
|
T23 |
22299 |
|
T25 |
305 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15819942 |
1 |
|
|
T22 |
68128 |
|
T23 |
48674 |
|
T24 |
275 |
| auto[1] |
944551 |
1 |
|
|
T22 |
4643 |
|
T23 |
3118 |
|
T25 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9444790 |
1 |
|
|
T22 |
39827 |
|
T23 |
28475 |
|
T24 |
275 |
| auto[1] |
7319703 |
1 |
|
|
T22 |
32944 |
|
T23 |
23317 |
|
T25 |
424 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3169468 |
1 |
|
|
T22 |
14235 |
|
T23 |
10075 |
|
T25 |
252 |
| auto[1] |
auto[0] |
auto[1] |
468276 |
1 |
|
|
T22 |
2301 |
|
T23 |
1532 |
|
T25 |
12 |
| auto[1] |
auto[1] |
auto[0] |
3205684 |
1 |
|
|
T22 |
14066 |
|
T23 |
10124 |
|
T25 |
155 |
| auto[1] |
auto[1] |
auto[1] |
476275 |
1 |
|
|
T22 |
2342 |
|
T23 |
1586 |
|
T25 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9458057 |
1 |
|
|
T22 |
40320 |
|
T23 |
27800 |
|
T24 |
275 |
| auto[1] |
7306436 |
1 |
|
|
T22 |
32451 |
|
T23 |
23992 |
|
T25 |
277 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15820962 |
1 |
|
|
T22 |
68087 |
|
T23 |
48876 |
|
T24 |
275 |
| auto[1] |
943531 |
1 |
|
|
T22 |
4684 |
|
T23 |
2916 |
|
T25 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9454925 |
1 |
|
|
T22 |
39047 |
|
T23 |
29869 |
|
T24 |
275 |
| auto[1] |
7309568 |
1 |
|
|
T22 |
33724 |
|
T23 |
21923 |
|
T25 |
367 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3182787 |
1 |
|
|
T22 |
15508 |
|
T23 |
9093 |
|
T25 |
233 |
| auto[1] |
auto[0] |
auto[1] |
471506 |
1 |
|
|
T22 |
2590 |
|
T23 |
1376 |
|
T25 |
6 |
| auto[1] |
auto[1] |
auto[0] |
3183250 |
1 |
|
|
T22 |
13532 |
|
T23 |
9914 |
|
T25 |
122 |
| auto[1] |
auto[1] |
auto[1] |
472025 |
1 |
|
|
T22 |
2094 |
|
T23 |
1540 |
|
T25 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9500185 |
1 |
|
|
T22 |
38504 |
|
T23 |
28450 |
|
T24 |
275 |
| auto[1] |
7264308 |
1 |
|
|
T22 |
34267 |
|
T23 |
23342 |
|
T25 |
376 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15815163 |
1 |
|
|
T22 |
68191 |
|
T23 |
49011 |
|
T24 |
275 |
| auto[1] |
949330 |
1 |
|
|
T22 |
4580 |
|
T23 |
2781 |
|
T25 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9419948 |
1 |
|
|
T22 |
39822 |
|
T23 |
30163 |
|
T24 |
275 |
| auto[1] |
7344545 |
1 |
|
|
T22 |
32949 |
|
T23 |
21629 |
|
T25 |
229 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3224027 |
1 |
|
|
T22 |
14317 |
|
T23 |
9451 |
|
T25 |
100 |
| auto[1] |
auto[0] |
auto[1] |
479994 |
1 |
|
|
T22 |
2277 |
|
T23 |
1369 |
|
T25 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3171188 |
1 |
|
|
T22 |
14052 |
|
T23 |
9397 |
|
T25 |
121 |
| auto[1] |
auto[1] |
auto[1] |
469336 |
1 |
|
|
T22 |
2303 |
|
T23 |
1412 |
|
T25 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9430019 |
1 |
|
|
T22 |
38795 |
|
T23 |
30368 |
|
T24 |
275 |
| auto[1] |
7334474 |
1 |
|
|
T22 |
33976 |
|
T23 |
21424 |
|
T25 |
366 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15823169 |
1 |
|
|
T22 |
68073 |
|
T23 |
48678 |
|
T24 |
275 |
| auto[1] |
941324 |
1 |
|
|
T22 |
4698 |
|
T23 |
3114 |
|
T25 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9461961 |
1 |
|
|
T22 |
38686 |
|
T23 |
28534 |
|
T24 |
275 |
| auto[1] |
7302532 |
1 |
|
|
T22 |
34085 |
|
T23 |
23258 |
|
T25 |
275 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3168412 |
1 |
|
|
T22 |
13918 |
|
T23 |
10032 |
|
T25 |
114 |
| auto[1] |
auto[0] |
auto[1] |
468076 |
1 |
|
|
T22 |
2232 |
|
T23 |
1534 |
|
T25 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3192796 |
1 |
|
|
T22 |
15469 |
|
T23 |
10112 |
|
T25 |
152 |
| auto[1] |
auto[1] |
auto[1] |
473248 |
1 |
|
|
T22 |
2466 |
|
T23 |
1580 |
|
T25 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9473464 |
1 |
|
|
T22 |
40085 |
|
T23 |
29979 |
|
T24 |
275 |
| auto[1] |
7291029 |
1 |
|
|
T22 |
32686 |
|
T23 |
21813 |
|
T25 |
298 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15817801 |
1 |
|
|
T22 |
68045 |
|
T23 |
48977 |
|
T24 |
275 |
| auto[1] |
946692 |
1 |
|
|
T22 |
4726 |
|
T23 |
2815 |
|
T25 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9425566 |
1 |
|
|
T22 |
38925 |
|
T23 |
30440 |
|
T24 |
275 |
| auto[1] |
7338927 |
1 |
|
|
T22 |
33846 |
|
T23 |
21352 |
|
T25 |
359 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3197725 |
1 |
|
|
T22 |
14667 |
|
T23 |
9831 |
|
T25 |
162 |
| auto[1] |
auto[0] |
auto[1] |
474200 |
1 |
|
|
T22 |
2365 |
|
T23 |
1565 |
|
T25 |
6 |
| auto[1] |
auto[1] |
auto[0] |
3194510 |
1 |
|
|
T22 |
14453 |
|
T23 |
8706 |
|
T25 |
186 |
| auto[1] |
auto[1] |
auto[1] |
472492 |
1 |
|
|
T22 |
2361 |
|
T23 |
1250 |
|
T25 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9439519 |
1 |
|
|
T22 |
39804 |
|
T23 |
29258 |
|
T24 |
275 |
| auto[1] |
7324974 |
1 |
|
|
T22 |
32967 |
|
T23 |
22534 |
|
T25 |
258 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15823176 |
1 |
|
|
T22 |
68443 |
|
T23 |
48820 |
|
T24 |
275 |
| auto[1] |
941317 |
1 |
|
|
T22 |
4328 |
|
T23 |
2972 |
|
T25 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9454743 |
1 |
|
|
T22 |
40884 |
|
T23 |
29255 |
|
T24 |
275 |
| auto[1] |
7309750 |
1 |
|
|
T22 |
31887 |
|
T23 |
22537 |
|
T25 |
381 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3187927 |
1 |
|
|
T22 |
13751 |
|
T23 |
9833 |
|
T25 |
221 |
| auto[1] |
auto[0] |
auto[1] |
472851 |
1 |
|
|
T22 |
2189 |
|
T23 |
1477 |
|
T25 |
9 |
| auto[1] |
auto[1] |
auto[0] |
3180506 |
1 |
|
|
T22 |
13808 |
|
T23 |
9732 |
|
T25 |
147 |
| auto[1] |
auto[1] |
auto[1] |
468466 |
1 |
|
|
T22 |
2139 |
|
T23 |
1495 |
|
T25 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9435676 |
1 |
|
|
T22 |
39214 |
|
T23 |
29828 |
|
T24 |
275 |
| auto[1] |
7328817 |
1 |
|
|
T22 |
33557 |
|
T23 |
21964 |
|
T25 |
365 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15820638 |
1 |
|
|
T22 |
68021 |
|
T23 |
49057 |
|
T24 |
275 |
| auto[1] |
943855 |
1 |
|
|
T22 |
4750 |
|
T23 |
2735 |
|
T25 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9450683 |
1 |
|
|
T22 |
38342 |
|
T23 |
30639 |
|
T24 |
275 |
| auto[1] |
7313810 |
1 |
|
|
T22 |
34429 |
|
T23 |
21153 |
|
T25 |
271 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3174895 |
1 |
|
|
T22 |
14627 |
|
T23 |
9378 |
|
T25 |
127 |
| auto[1] |
auto[0] |
auto[1] |
470077 |
1 |
|
|
T22 |
2372 |
|
T23 |
1355 |
|
T25 |
7 |
| auto[1] |
auto[1] |
auto[0] |
3195060 |
1 |
|
|
T22 |
15052 |
|
T23 |
9040 |
|
T25 |
136 |
| auto[1] |
auto[1] |
auto[1] |
473778 |
1 |
|
|
T22 |
2378 |
|
T23 |
1380 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9462204 |
1 |
|
|
T22 |
41615 |
|
T23 |
29538 |
|
T24 |
275 |
| auto[1] |
7302289 |
1 |
|
|
T22 |
31156 |
|
T23 |
22254 |
|
T25 |
348 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15825697 |
1 |
|
|
T22 |
68334 |
|
T23 |
48900 |
|
T24 |
275 |
| auto[1] |
938796 |
1 |
|
|
T22 |
4437 |
|
T23 |
2892 |
|
T25 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9486495 |
1 |
|
|
T22 |
40464 |
|
T23 |
29314 |
|
T24 |
275 |
| auto[1] |
7277998 |
1 |
|
|
T22 |
32307 |
|
T23 |
22478 |
|
T25 |
342 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3177709 |
1 |
|
|
T22 |
14185 |
|
T23 |
10432 |
|
T25 |
149 |
| auto[1] |
auto[0] |
auto[1] |
471309 |
1 |
|
|
T22 |
2236 |
|
T23 |
1539 |
|
T25 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3161493 |
1 |
|
|
T22 |
13685 |
|
T23 |
9154 |
|
T25 |
185 |
| auto[1] |
auto[1] |
auto[1] |
467487 |
1 |
|
|
T22 |
2201 |
|
T23 |
1353 |
|
T25 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9464275 |
1 |
|
|
T22 |
41752 |
|
T23 |
30163 |
|
T24 |
275 |
| auto[1] |
7300218 |
1 |
|
|
T22 |
31019 |
|
T23 |
21629 |
|
T25 |
414 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15825372 |
1 |
|
|
T22 |
68491 |
|
T23 |
48885 |
|
T24 |
275 |
| auto[1] |
939121 |
1 |
|
|
T22 |
4280 |
|
T23 |
2907 |
|
T25 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9469631 |
1 |
|
|
T22 |
41847 |
|
T23 |
29449 |
|
T24 |
275 |
| auto[1] |
7294862 |
1 |
|
|
T22 |
30924 |
|
T23 |
22343 |
|
T25 |
298 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3187948 |
1 |
|
|
T22 |
13701 |
|
T23 |
9866 |
|
T25 |
129 |
| auto[1] |
auto[0] |
auto[1] |
470096 |
1 |
|
|
T22 |
2237 |
|
T23 |
1456 |
|
T25 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3167793 |
1 |
|
|
T22 |
12943 |
|
T23 |
9570 |
|
T25 |
157 |
| auto[1] |
auto[1] |
auto[1] |
469025 |
1 |
|
|
T22 |
2043 |
|
T23 |
1451 |
|
T25 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9455903 |
1 |
|
|
T22 |
38885 |
|
T23 |
30190 |
|
T24 |
275 |
| auto[1] |
7308590 |
1 |
|
|
T22 |
33886 |
|
T23 |
21602 |
|
T25 |
404 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15824513 |
1 |
|
|
T22 |
68086 |
|
T23 |
48871 |
|
T24 |
275 |
| auto[1] |
939980 |
1 |
|
|
T22 |
4685 |
|
T23 |
2921 |
|
T25 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9471854 |
1 |
|
|
T22 |
38553 |
|
T23 |
29906 |
|
T24 |
275 |
| auto[1] |
7292639 |
1 |
|
|
T22 |
34218 |
|
T23 |
21886 |
|
T25 |
478 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3164493 |
1 |
|
|
T22 |
13830 |
|
T23 |
9764 |
|
T25 |
183 |
| auto[1] |
auto[0] |
auto[1] |
466866 |
1 |
|
|
T22 |
2188 |
|
T23 |
1588 |
|
T25 |
9 |
| auto[1] |
auto[1] |
auto[0] |
3188166 |
1 |
|
|
T22 |
15703 |
|
T23 |
9201 |
|
T25 |
280 |
| auto[1] |
auto[1] |
auto[1] |
473114 |
1 |
|
|
T22 |
2497 |
|
T23 |
1333 |
|
T25 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9446349 |
1 |
|
|
T22 |
38557 |
|
T23 |
28734 |
|
T24 |
275 |
| auto[1] |
7318144 |
1 |
|
|
T22 |
34214 |
|
T23 |
23058 |
|
T25 |
366 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15815894 |
1 |
|
|
T22 |
68099 |
|
T23 |
48839 |
|
T24 |
275 |
| auto[1] |
948599 |
1 |
|
|
T22 |
4672 |
|
T23 |
2953 |
|
T25 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9420035 |
1 |
|
|
T22 |
38926 |
|
T23 |
29463 |
|
T24 |
275 |
| auto[1] |
7344458 |
1 |
|
|
T22 |
33845 |
|
T23 |
22329 |
|
T25 |
268 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3180774 |
1 |
|
|
T22 |
14217 |
|
T23 |
9028 |
|
T25 |
166 |
| auto[1] |
auto[0] |
auto[1] |
471820 |
1 |
|
|
T22 |
2287 |
|
T23 |
1318 |
|
T25 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3215085 |
1 |
|
|
T22 |
14956 |
|
T23 |
10348 |
|
T25 |
93 |
| auto[1] |
auto[1] |
auto[1] |
476779 |
1 |
|
|
T22 |
2385 |
|
T23 |
1635 |
|
T25 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9446673 |
1 |
|
|
T22 |
39813 |
|
T23 |
30459 |
|
T24 |
275 |
| auto[1] |
7317820 |
1 |
|
|
T22 |
32958 |
|
T23 |
21333 |
|
T25 |
292 |