Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15817068 |
1 |
|
|
T22 |
68029 |
|
T23 |
48985 |
|
T24 |
275 |
| auto[1] |
947425 |
1 |
|
|
T22 |
4742 |
|
T23 |
2807 |
|
T25 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9432605 |
1 |
|
|
T22 |
38148 |
|
T23 |
30309 |
|
T24 |
275 |
| auto[1] |
7331888 |
1 |
|
|
T22 |
34623 |
|
T23 |
21483 |
|
T25 |
369 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3201254 |
1 |
|
|
T22 |
15733 |
|
T23 |
9750 |
|
T25 |
223 |
| auto[1] |
auto[0] |
auto[1] |
476023 |
1 |
|
|
T22 |
2487 |
|
T23 |
1441 |
|
T25 |
8 |
| auto[1] |
auto[1] |
auto[0] |
3183209 |
1 |
|
|
T22 |
14148 |
|
T23 |
8926 |
|
T25 |
132 |
| auto[1] |
auto[1] |
auto[1] |
471402 |
1 |
|
|
T22 |
2255 |
|
T23 |
1366 |
|
T25 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |