Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 945
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T764 /workspace/coverage/cover_reg_top/16.gpio_intr_test.2047718924 Feb 29 12:43:49 PM PST 24 Feb 29 12:43:50 PM PST 24 102039350 ps
T102 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3364235392 Feb 29 12:43:26 PM PST 24 Feb 29 12:43:27 PM PST 24 114477955 ps
T765 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2304653866 Feb 29 12:43:25 PM PST 24 Feb 29 12:43:28 PM PST 24 42771789 ps
T766 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2024381812 Feb 29 12:43:12 PM PST 24 Feb 29 12:43:13 PM PST 24 407862887 ps
T767 /workspace/coverage/cover_reg_top/5.gpio_intr_test.181181651 Feb 29 12:43:15 PM PST 24 Feb 29 12:43:16 PM PST 24 69994400 ps
T768 /workspace/coverage/cover_reg_top/37.gpio_intr_test.1794216886 Feb 29 12:43:27 PM PST 24 Feb 29 12:43:28 PM PST 24 11128379 ps
T769 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3029213539 Feb 29 12:42:56 PM PST 24 Feb 29 12:42:58 PM PST 24 23041275 ps
T103 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2852901815 Feb 29 12:43:16 PM PST 24 Feb 29 12:43:18 PM PST 24 59738812 ps
T770 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1819141535 Feb 29 12:43:14 PM PST 24 Feb 29 12:43:16 PM PST 24 28879719 ps
T771 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3898420239 Feb 29 12:43:17 PM PST 24 Feb 29 12:43:18 PM PST 24 13119003 ps
T772 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1363180884 Feb 29 12:43:27 PM PST 24 Feb 29 12:43:28 PM PST 24 45391059 ps
T773 /workspace/coverage/cover_reg_top/9.gpio_intr_test.2810992643 Feb 29 12:43:29 PM PST 24 Feb 29 12:43:30 PM PST 24 39686180 ps
T774 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1672128601 Feb 29 12:42:49 PM PST 24 Feb 29 12:42:50 PM PST 24 84266609 ps
T775 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3113599742 Feb 29 12:43:17 PM PST 24 Feb 29 12:43:18 PM PST 24 23789372 ps
T776 /workspace/coverage/cover_reg_top/4.gpio_intr_test.2692066091 Feb 29 12:43:06 PM PST 24 Feb 29 12:43:06 PM PST 24 12988816 ps
T777 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3050569018 Feb 29 12:43:14 PM PST 24 Feb 29 12:43:16 PM PST 24 81644684 ps
T778 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3642680658 Feb 29 12:43:09 PM PST 24 Feb 29 12:43:10 PM PST 24 61313078 ps
T779 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2859605324 Feb 29 12:43:08 PM PST 24 Feb 29 12:43:09 PM PST 24 58591423 ps
T780 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.262271187 Feb 29 12:43:08 PM PST 24 Feb 29 12:43:09 PM PST 24 405252432 ps
T781 /workspace/coverage/cover_reg_top/3.gpio_intr_test.4121066992 Feb 29 12:43:13 PM PST 24 Feb 29 12:43:14 PM PST 24 19184696 ps
T782 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3339144487 Feb 29 12:43:18 PM PST 24 Feb 29 12:43:19 PM PST 24 31329054 ps
T39 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.454948130 Feb 29 12:43:35 PM PST 24 Feb 29 12:43:36 PM PST 24 541031403 ps
T783 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1040291774 Feb 29 12:43:17 PM PST 24 Feb 29 12:43:19 PM PST 24 111121613 ps
T43 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.811331470 Feb 29 12:43:18 PM PST 24 Feb 29 12:43:19 PM PST 24 94621130 ps
T784 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3529492025 Feb 29 12:43:29 PM PST 24 Feb 29 12:43:31 PM PST 24 36100286 ps
T785 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3902429196 Feb 29 12:43:18 PM PST 24 Feb 29 12:43:18 PM PST 24 45693403 ps
T786 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.274132035 Feb 29 12:43:16 PM PST 24 Feb 29 12:43:18 PM PST 24 477667883 ps
T787 /workspace/coverage/cover_reg_top/31.gpio_intr_test.4158187225 Feb 29 12:43:39 PM PST 24 Feb 29 12:43:40 PM PST 24 30781869 ps
T788 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1076329376 Feb 29 12:43:33 PM PST 24 Feb 29 12:43:34 PM PST 24 13571211 ps
T789 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.905095513 Feb 29 12:43:19 PM PST 24 Feb 29 12:43:20 PM PST 24 72420840 ps
T790 /workspace/coverage/cover_reg_top/46.gpio_intr_test.3041756915 Feb 29 12:43:37 PM PST 24 Feb 29 12:43:38 PM PST 24 13243412 ps
T791 /workspace/coverage/cover_reg_top/32.gpio_intr_test.3125684764 Feb 29 12:43:44 PM PST 24 Feb 29 12:43:44 PM PST 24 187872374 ps
T792 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2697816396 Feb 29 12:43:43 PM PST 24 Feb 29 12:43:44 PM PST 24 215325459 ps
T793 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3429600336 Feb 29 12:43:15 PM PST 24 Feb 29 12:43:18 PM PST 24 171005941 ps
T87 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.302464159 Feb 29 12:43:08 PM PST 24 Feb 29 12:43:09 PM PST 24 110790782 ps
T794 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1962122196 Feb 29 12:43:21 PM PST 24 Feb 29 12:43:23 PM PST 24 36996217 ps
T88 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3037947778 Feb 29 12:43:12 PM PST 24 Feb 29 12:43:14 PM PST 24 27591666 ps
T795 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2502001967 Feb 29 12:43:28 PM PST 24 Feb 29 12:43:30 PM PST 24 20660765 ps
T796 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3417533563 Feb 29 12:43:53 PM PST 24 Feb 29 12:43:54 PM PST 24 45592754 ps
T797 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.438575649 Feb 29 12:43:10 PM PST 24 Feb 29 12:43:11 PM PST 24 12292478 ps
T798 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3757316946 Feb 29 12:43:19 PM PST 24 Feb 29 12:43:21 PM PST 24 55643607 ps
T799 /workspace/coverage/cover_reg_top/35.gpio_intr_test.667865365 Feb 29 12:43:28 PM PST 24 Feb 29 12:43:29 PM PST 24 13925177 ps
T89 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1175449642 Feb 29 12:43:28 PM PST 24 Feb 29 12:43:28 PM PST 24 37332609 ps
T800 /workspace/coverage/cover_reg_top/40.gpio_intr_test.1229926466 Feb 29 12:43:34 PM PST 24 Feb 29 12:43:35 PM PST 24 20468560 ps
T801 /workspace/coverage/cover_reg_top/12.gpio_intr_test.453217402 Feb 29 12:43:31 PM PST 24 Feb 29 12:43:32 PM PST 24 44303032 ps
T802 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3287396425 Feb 29 12:43:08 PM PST 24 Feb 29 12:43:09 PM PST 24 18939456 ps
T803 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.458286358 Feb 29 12:43:09 PM PST 24 Feb 29 12:43:10 PM PST 24 13277060 ps
T804 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.4026753182 Feb 29 12:43:24 PM PST 24 Feb 29 12:43:24 PM PST 24 28262650 ps
T805 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2229151940 Feb 29 12:43:08 PM PST 24 Feb 29 12:43:09 PM PST 24 18915924 ps
T806 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2332530864 Feb 29 12:43:07 PM PST 24 Feb 29 12:43:07 PM PST 24 21205084 ps
T807 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2849133122 Feb 29 12:43:33 PM PST 24 Feb 29 12:43:34 PM PST 24 533804053 ps
T808 /workspace/coverage/cover_reg_top/13.gpio_intr_test.3477043769 Feb 29 12:43:27 PM PST 24 Feb 29 12:43:28 PM PST 24 33948890 ps
T809 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2447369712 Feb 29 12:43:22 PM PST 24 Feb 29 12:43:22 PM PST 24 14545375 ps
T810 /workspace/coverage/cover_reg_top/33.gpio_intr_test.986742337 Feb 29 12:43:30 PM PST 24 Feb 29 12:43:31 PM PST 24 18211832 ps
T811 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1129536 Feb 29 12:43:19 PM PST 24 Feb 29 12:43:21 PM PST 24 13233783 ps
T812 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.636849697 Feb 29 12:43:30 PM PST 24 Feb 29 12:43:31 PM PST 24 139635901 ps
T90 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.527080856 Feb 29 12:43:21 PM PST 24 Feb 29 12:43:22 PM PST 24 24916980 ps
T813 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1312197863 Feb 29 12:43:26 PM PST 24 Feb 29 12:43:27 PM PST 24 374188226 ps
T814 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1692561935 Feb 29 12:43:36 PM PST 24 Feb 29 12:43:37 PM PST 24 43360064 ps
T815 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1113793490 Feb 29 12:43:22 PM PST 24 Feb 29 12:43:24 PM PST 24 133831198 ps
T816 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2331302891 Feb 29 12:43:22 PM PST 24 Feb 29 12:43:23 PM PST 24 31708806 ps
T817 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1285255559 Feb 29 12:42:51 PM PST 24 Feb 29 12:42:52 PM PST 24 33273743 ps
T818 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2460403811 Feb 29 12:43:15 PM PST 24 Feb 29 12:43:16 PM PST 24 23742094 ps
T819 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1369496176 Feb 29 12:43:09 PM PST 24 Feb 29 12:43:10 PM PST 24 20209401 ps
T820 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2536247551 Feb 29 12:43:16 PM PST 24 Feb 29 12:43:18 PM PST 24 15753423 ps
T821 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2065754166 Feb 29 12:43:23 PM PST 24 Feb 29 12:43:25 PM PST 24 84255060 ps
T94 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1974281309 Feb 29 12:43:00 PM PST 24 Feb 29 12:43:05 PM PST 24 375993429 ps
T822 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3518350353 Feb 29 12:43:28 PM PST 24 Feb 29 12:43:30 PM PST 24 71599539 ps
T823 /workspace/coverage/cover_reg_top/38.gpio_intr_test.3005927253 Feb 29 12:43:37 PM PST 24 Feb 29 12:43:43 PM PST 24 14859556 ps
T40 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3821832936 Feb 29 12:43:19 PM PST 24 Feb 29 12:43:21 PM PST 24 135922151 ps
T824 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.220730142 Feb 29 12:43:15 PM PST 24 Feb 29 12:43:17 PM PST 24 69945937 ps
T825 /workspace/coverage/cover_reg_top/34.gpio_intr_test.849710752 Feb 29 12:43:41 PM PST 24 Feb 29 12:43:42 PM PST 24 13257056 ps
T826 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1034674564 Feb 29 12:43:13 PM PST 24 Feb 29 12:43:15 PM PST 24 119677810 ps
T827 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3380002516 Feb 29 12:43:07 PM PST 24 Feb 29 12:43:08 PM PST 24 390603167 ps
T828 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.156846035 Feb 29 12:43:23 PM PST 24 Feb 29 12:43:24 PM PST 24 78166859 ps
T829 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1103341757 Feb 29 12:43:27 PM PST 24 Feb 29 12:43:27 PM PST 24 45313053 ps
T830 /workspace/coverage/cover_reg_top/30.gpio_intr_test.2823322499 Feb 29 12:43:37 PM PST 24 Feb 29 12:43:38 PM PST 24 76730023 ps
T831 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2454510535 Feb 29 12:43:10 PM PST 24 Feb 29 12:43:11 PM PST 24 14852359 ps
T832 /workspace/coverage/cover_reg_top/6.gpio_intr_test.446557561 Feb 29 12:43:11 PM PST 24 Feb 29 12:43:11 PM PST 24 11730754 ps
T833 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1675415515 Feb 29 12:43:34 PM PST 24 Feb 29 12:43:35 PM PST 24 62016341 ps
T834 /workspace/coverage/cover_reg_top/47.gpio_intr_test.1580489048 Feb 29 12:43:22 PM PST 24 Feb 29 12:43:22 PM PST 24 13705386 ps
T835 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.525164517 Feb 29 12:43:17 PM PST 24 Feb 29 12:43:19 PM PST 24 35864608 ps
T836 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.479578460 Feb 29 12:43:17 PM PST 24 Feb 29 12:43:21 PM PST 24 243130773 ps
T91 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3612293236 Feb 29 12:43:11 PM PST 24 Feb 29 12:43:12 PM PST 24 138940163 ps
T837 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1393947742 Feb 29 12:43:29 PM PST 24 Feb 29 12:43:30 PM PST 24 20788987 ps
T838 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.210512066 Feb 29 12:43:21 PM PST 24 Feb 29 12:43:23 PM PST 24 418025473 ps
T839 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1686873956 Feb 29 12:43:18 PM PST 24 Feb 29 12:43:19 PM PST 24 202662791 ps
T840 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4269922688 Feb 29 12:43:11 PM PST 24 Feb 29 12:43:13 PM PST 24 61326277 ps
T92 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.4163017014 Feb 29 12:43:29 PM PST 24 Feb 29 12:43:35 PM PST 24 32649170 ps
T95 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2239030244 Feb 29 12:43:27 PM PST 24 Feb 29 12:43:28 PM PST 24 30524718 ps
T841 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.207864857 Feb 29 12:43:06 PM PST 24 Feb 29 12:43:07 PM PST 24 44943373 ps
T842 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1173405639 Feb 29 12:43:25 PM PST 24 Feb 29 12:43:26 PM PST 24 1999033257 ps
T843 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2116277462 Feb 29 12:43:42 PM PST 24 Feb 29 12:43:44 PM PST 24 328011320 ps
T844 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2274029882 Feb 29 12:43:12 PM PST 24 Feb 29 12:43:14 PM PST 24 77426875 ps
T845 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.4098241010 Feb 29 12:43:14 PM PST 24 Feb 29 12:43:15 PM PST 24 60769840 ps
T846 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.498409254 Feb 29 12:42:29 PM PST 24 Feb 29 12:42:31 PM PST 24 221622980 ps
T847 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3285598668 Feb 29 12:42:26 PM PST 24 Feb 29 12:42:28 PM PST 24 216528781 ps
T848 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.80704864 Feb 29 12:42:57 PM PST 24 Feb 29 12:42:58 PM PST 24 112203994 ps
T849 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1457615694 Feb 29 12:42:36 PM PST 24 Feb 29 12:42:38 PM PST 24 974631402 ps
T850 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.891026714 Feb 29 12:42:29 PM PST 24 Feb 29 12:42:31 PM PST 24 50526320 ps
T851 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3398310547 Feb 29 12:42:31 PM PST 24 Feb 29 12:42:32 PM PST 24 30080891 ps
T852 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2129417987 Feb 29 12:42:26 PM PST 24 Feb 29 12:42:29 PM PST 24 29547587 ps
T853 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3377401756 Feb 29 12:42:39 PM PST 24 Feb 29 12:42:40 PM PST 24 590553398 ps
T854 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2621840996 Feb 29 12:42:41 PM PST 24 Feb 29 12:42:42 PM PST 24 103780248 ps
T855 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.558224940 Feb 29 12:42:36 PM PST 24 Feb 29 12:42:38 PM PST 24 355486038 ps
T856 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1694305383 Feb 29 12:42:38 PM PST 24 Feb 29 12:42:39 PM PST 24 144106350 ps
T857 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3844998941 Feb 29 12:42:30 PM PST 24 Feb 29 12:42:31 PM PST 24 56595583 ps
T858 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.741382550 Feb 29 12:42:34 PM PST 24 Feb 29 12:42:35 PM PST 24 621720523 ps
T859 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1336345981 Feb 29 12:42:36 PM PST 24 Feb 29 12:42:37 PM PST 24 143151546 ps
T860 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1636307549 Feb 29 12:42:59 PM PST 24 Feb 29 12:43:02 PM PST 24 103213895 ps
T861 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.178441142 Feb 29 12:42:50 PM PST 24 Feb 29 12:42:51 PM PST 24 225151978 ps
T862 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2133833186 Feb 29 12:42:39 PM PST 24 Feb 29 12:42:41 PM PST 24 86010616 ps
T863 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3227222336 Feb 29 12:42:35 PM PST 24 Feb 29 12:42:36 PM PST 24 94181495 ps
T864 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1011468225 Feb 29 12:42:37 PM PST 24 Feb 29 12:42:38 PM PST 24 427978579 ps
T865 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1408170272 Feb 29 12:42:25 PM PST 24 Feb 29 12:42:26 PM PST 24 37261315 ps
T866 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2469812588 Feb 29 12:42:31 PM PST 24 Feb 29 12:42:34 PM PST 24 304773885 ps
T867 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.539078879 Feb 29 12:42:36 PM PST 24 Feb 29 12:42:38 PM PST 24 106716312 ps
T868 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3680482774 Feb 29 12:42:31 PM PST 24 Feb 29 12:42:33 PM PST 24 134988325 ps
T869 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.326423522 Feb 29 12:42:35 PM PST 24 Feb 29 12:42:36 PM PST 24 266881905 ps
T870 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1483478239 Feb 29 12:42:32 PM PST 24 Feb 29 12:42:34 PM PST 24 45889227 ps
T871 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.542112473 Feb 29 12:42:40 PM PST 24 Feb 29 12:42:41 PM PST 24 126453404 ps
T872 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2520087355 Feb 29 12:42:47 PM PST 24 Feb 29 12:42:49 PM PST 24 104828568 ps
T873 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2409344333 Feb 29 12:42:34 PM PST 24 Feb 29 12:42:37 PM PST 24 39318422 ps
T874 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.49001750 Feb 29 12:42:32 PM PST 24 Feb 29 12:42:33 PM PST 24 125887789 ps
T875 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2834150223 Feb 29 12:42:32 PM PST 24 Feb 29 12:42:34 PM PST 24 72833133 ps
T876 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2661484267 Feb 29 12:42:37 PM PST 24 Feb 29 12:42:38 PM PST 24 232583271 ps
T877 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1206217431 Feb 29 12:42:35 PM PST 24 Feb 29 12:42:37 PM PST 24 139829312 ps
T878 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1752175639 Feb 29 12:42:36 PM PST 24 Feb 29 12:42:38 PM PST 24 127559502 ps
T879 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.782805997 Feb 29 12:42:40 PM PST 24 Feb 29 12:42:41 PM PST 24 193665483 ps
T880 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1927690117 Feb 29 12:42:28 PM PST 24 Feb 29 12:42:30 PM PST 24 31054931 ps
T881 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3410086608 Feb 29 12:42:30 PM PST 24 Feb 29 12:42:32 PM PST 24 38256848 ps
T882 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1905665768 Feb 29 12:42:27 PM PST 24 Feb 29 12:42:29 PM PST 24 87545533 ps
T883 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3707970749 Feb 29 12:42:28 PM PST 24 Feb 29 12:42:30 PM PST 24 68950203 ps
T884 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.747718527 Feb 29 12:42:40 PM PST 24 Feb 29 12:42:41 PM PST 24 356631274 ps
T885 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3065353324 Feb 29 12:42:45 PM PST 24 Feb 29 12:42:47 PM PST 24 54365698 ps
T886 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1422157328 Feb 29 12:42:27 PM PST 24 Feb 29 12:42:29 PM PST 24 401764743 ps
T887 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3712390013 Feb 29 12:42:24 PM PST 24 Feb 29 12:42:25 PM PST 24 190817402 ps
T888 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1122994040 Feb 29 12:42:31 PM PST 24 Feb 29 12:42:33 PM PST 24 206328520 ps
T889 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3207425451 Feb 29 12:42:23 PM PST 24 Feb 29 12:42:24 PM PST 24 34097998 ps
T890 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3648758372 Feb 29 12:42:33 PM PST 24 Feb 29 12:42:35 PM PST 24 138361633 ps
T891 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3775534592 Feb 29 12:42:43 PM PST 24 Feb 29 12:42:45 PM PST 24 234366701 ps
T892 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.345088226 Feb 29 12:42:48 PM PST 24 Feb 29 12:42:50 PM PST 24 173533083 ps
T893 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3903028062 Feb 29 12:42:49 PM PST 24 Feb 29 12:42:50 PM PST 24 29882296 ps
T894 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2343539784 Feb 29 12:42:32 PM PST 24 Feb 29 12:42:34 PM PST 24 223239417 ps
T895 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.856415604 Feb 29 12:42:26 PM PST 24 Feb 29 12:42:28 PM PST 24 91542339 ps
T896 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1876320185 Feb 29 12:42:27 PM PST 24 Feb 29 12:42:29 PM PST 24 104409347 ps
T897 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1481974752 Feb 29 12:42:30 PM PST 24 Feb 29 12:42:31 PM PST 24 64013350 ps
T898 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.422781728 Feb 29 12:42:31 PM PST 24 Feb 29 12:42:33 PM PST 24 519496752 ps
T899 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1171462164 Feb 29 12:42:47 PM PST 24 Feb 29 12:42:49 PM PST 24 42814696 ps
T900 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2809193028 Feb 29 12:42:39 PM PST 24 Feb 29 12:42:41 PM PST 24 139412933 ps
T901 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.446678716 Feb 29 12:42:32 PM PST 24 Feb 29 12:42:33 PM PST 24 40601438 ps
T902 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.650429459 Feb 29 12:42:34 PM PST 24 Feb 29 12:42:35 PM PST 24 77360948 ps
T903 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2307833960 Feb 29 12:42:27 PM PST 24 Feb 29 12:42:28 PM PST 24 24061187 ps
T904 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.345462791 Feb 29 12:42:29 PM PST 24 Feb 29 12:42:31 PM PST 24 139419086 ps
T905 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1716779273 Feb 29 12:42:35 PM PST 24 Feb 29 12:42:41 PM PST 24 149887794 ps
T906 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1632326477 Feb 29 12:42:37 PM PST 24 Feb 29 12:42:39 PM PST 24 45888845 ps
T907 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1389320236 Feb 29 12:42:39 PM PST 24 Feb 29 12:42:46 PM PST 24 112751292 ps
T908 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2993926410 Feb 29 12:42:24 PM PST 24 Feb 29 12:42:25 PM PST 24 81222325 ps
T909 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2304995460 Feb 29 12:42:39 PM PST 24 Feb 29 12:42:41 PM PST 24 170730826 ps
T910 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1653207257 Feb 29 12:42:34 PM PST 24 Feb 29 12:42:36 PM PST 24 76408888 ps
T911 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.772211062 Feb 29 12:42:37 PM PST 24 Feb 29 12:42:38 PM PST 24 110277819 ps
T912 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2799546445 Feb 29 12:42:29 PM PST 24 Feb 29 12:42:31 PM PST 24 83576394 ps
T913 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3222515530 Feb 29 12:42:45 PM PST 24 Feb 29 12:42:46 PM PST 24 165789619 ps
T914 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1138346893 Feb 29 12:42:35 PM PST 24 Feb 29 12:42:37 PM PST 24 71125171 ps
T915 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1159309933 Feb 29 12:42:36 PM PST 24 Feb 29 12:42:38 PM PST 24 104196461 ps
T916 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1555354295 Feb 29 12:42:27 PM PST 24 Feb 29 12:42:29 PM PST 24 60133624 ps
T917 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.749400301 Feb 29 12:42:28 PM PST 24 Feb 29 12:42:31 PM PST 24 509691270 ps
T918 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3798722778 Feb 29 12:42:28 PM PST 24 Feb 29 12:42:35 PM PST 24 52465109 ps
T919 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.392436309 Feb 29 12:42:28 PM PST 24 Feb 29 12:42:30 PM PST 24 32654928 ps
T920 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4293882513 Feb 29 12:42:30 PM PST 24 Feb 29 12:42:32 PM PST 24 29491893 ps
T921 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1208268511 Feb 29 12:42:35 PM PST 24 Feb 29 12:42:37 PM PST 24 129863543 ps
T922 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1976883686 Feb 29 12:42:26 PM PST 24 Feb 29 12:42:28 PM PST 24 79728622 ps
T923 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1271519146 Feb 29 12:42:34 PM PST 24 Feb 29 12:42:36 PM PST 24 82660106 ps
T924 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2834271101 Feb 29 12:42:25 PM PST 24 Feb 29 12:42:25 PM PST 24 27350377 ps
T925 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.650135407 Feb 29 12:42:30 PM PST 24 Feb 29 12:42:31 PM PST 24 29166005 ps
T926 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.129554382 Feb 29 12:42:43 PM PST 24 Feb 29 12:42:44 PM PST 24 40881256 ps
T927 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1166113369 Feb 29 12:42:30 PM PST 24 Feb 29 12:42:31 PM PST 24 29384830 ps
T928 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3359022855 Feb 29 12:42:28 PM PST 24 Feb 29 12:42:31 PM PST 24 235325144 ps
T929 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.647962729 Feb 29 12:42:37 PM PST 24 Feb 29 12:42:39 PM PST 24 85978853 ps
T930 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2023093802 Feb 29 12:42:31 PM PST 24 Feb 29 12:42:33 PM PST 24 36019682 ps
T931 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.218046561 Feb 29 12:42:39 PM PST 24 Feb 29 12:42:41 PM PST 24 116695341 ps
T932 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3936012672 Feb 29 12:42:36 PM PST 24 Feb 29 12:42:37 PM PST 24 50450210 ps
T933 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1857778992 Feb 29 12:42:27 PM PST 24 Feb 29 12:42:30 PM PST 24 798655462 ps
T934 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3608946869 Feb 29 12:42:36 PM PST 24 Feb 29 12:42:37 PM PST 24 50678642 ps
T935 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2032213077 Feb 29 12:42:32 PM PST 24 Feb 29 12:42:34 PM PST 24 78118900 ps
T936 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1488589980 Feb 29 12:42:42 PM PST 24 Feb 29 12:42:44 PM PST 24 251116789 ps
T937 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2848753213 Feb 29 12:42:30 PM PST 24 Feb 29 12:42:31 PM PST 24 181580200 ps
T938 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3728531139 Feb 29 12:42:34 PM PST 24 Feb 29 12:42:36 PM PST 24 107541589 ps
T939 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3511541782 Feb 29 12:42:45 PM PST 24 Feb 29 12:42:46 PM PST 24 157252761 ps
T940 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1683061823 Feb 29 12:42:35 PM PST 24 Feb 29 12:42:37 PM PST 24 89347197 ps
T941 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4030729954 Feb 29 12:42:37 PM PST 24 Feb 29 12:42:39 PM PST 24 145260307 ps
T942 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3501490728 Feb 29 12:42:43 PM PST 24 Feb 29 12:42:45 PM PST 24 257476516 ps
T943 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2132339659 Feb 29 12:42:39 PM PST 24 Feb 29 12:42:41 PM PST 24 51502792 ps
T944 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.955320693 Feb 29 12:42:46 PM PST 24 Feb 29 12:42:48 PM PST 24 84683219 ps
T945 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2918211312 Feb 29 12:42:26 PM PST 24 Feb 29 12:42:28 PM PST 24 191254625 ps

Test location /workspace/coverage/default/5.gpio_stress_all.858115739
Short name T22
Test name
Test status
Simulation time 7989505445 ps
CPU time 113.51 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:55:09 PM PST 24
Peak memory 198232 kb
Host smart-3f949a1f-ef90-4378-a4be-14294b67252b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858115739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.858115739
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2546377272
Short name T19
Test name
Test status
Simulation time 65625762 ps
CPU time 1.42 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:19 PM PST 24
Peak memory 196696 kb
Host smart-1c9e3e8b-f977-46f2-b23a-44fe9d88a536
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546377272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2546377272
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2652542558
Short name T26
Test name
Test status
Simulation time 46746150874 ps
CPU time 667.39 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 01:05:16 PM PST 24
Peak memory 198372 kb
Host smart-bd34033d-b733-413f-affd-0b13b056ffd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2652542558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2652542558
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.3485924868
Short name T108
Test name
Test status
Simulation time 181211525 ps
CPU time 1.32 seconds
Started Feb 29 12:53:52 PM PST 24
Finished Feb 29 12:53:53 PM PST 24
Peak memory 198064 kb
Host smart-7f79d2e1-5aa7-4fee-a07b-dc5f11209ac2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485924868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.3485924868
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3631558708
Short name T34
Test name
Test status
Simulation time 74855302 ps
CPU time 0.79 seconds
Started Feb 29 12:52:50 PM PST 24
Finished Feb 29 12:52:51 PM PST 24
Peak memory 213776 kb
Host smart-3a875dc4-2640-4f7b-bf58-7af5f1de6a0c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631558708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3631558708
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1071665311
Short name T79
Test name
Test status
Simulation time 12973755 ps
CPU time 0.63 seconds
Started Feb 29 12:43:46 PM PST 24
Finished Feb 29 12:43:47 PM PST 24
Peak memory 195008 kb
Host smart-f8b9bb91-77bb-41ca-805e-3e258e5b77ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071665311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1071665311
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2353930188
Short name T2
Test name
Test status
Simulation time 8909424939 ps
CPU time 95.97 seconds
Started Feb 29 12:52:58 PM PST 24
Finished Feb 29 12:54:35 PM PST 24
Peak memory 198212 kb
Host smart-afbfaaf1-2030-4270-9d02-5a13b2d237cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353930188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2353930188
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1673364621
Short name T37
Test name
Test status
Simulation time 909924921 ps
CPU time 1.46 seconds
Started Feb 29 12:43:27 PM PST 24
Finished Feb 29 12:43:28 PM PST 24
Peak memory 198460 kb
Host smart-99fd6d19-c764-4fa2-9d1b-932c5681fcd9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673364621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1673364621
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1996033017
Short name T122
Test name
Test status
Simulation time 18136712 ps
CPU time 0.57 seconds
Started Feb 29 12:52:42 PM PST 24
Finished Feb 29 12:52:43 PM PST 24
Peak memory 193908 kb
Host smart-97c469de-11cf-4f3e-b8de-ffc82419832c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996033017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1996033017
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1974281309
Short name T94
Test name
Test status
Simulation time 375993429 ps
CPU time 3.71 seconds
Started Feb 29 12:43:00 PM PST 24
Finished Feb 29 12:43:05 PM PST 24
Peak memory 197188 kb
Host smart-b67c02f9-a768-4aa0-a4d6-9de1c56ac857
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974281309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1974281309
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3716664532
Short name T100
Test name
Test status
Simulation time 24066981 ps
CPU time 0.65 seconds
Started Feb 29 12:43:04 PM PST 24
Finished Feb 29 12:43:05 PM PST 24
Peak memory 195296 kb
Host smart-652b6d1d-030b-456b-b490-de0ad6c45785
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716664532 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3716664532
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.274132035
Short name T786
Test name
Test status
Simulation time 477667883 ps
CPU time 1.44 seconds
Started Feb 29 12:43:16 PM PST 24
Finished Feb 29 12:43:18 PM PST 24
Peak memory 198480 kb
Host smart-d4f795a8-30a1-4d5e-bf61-1a408169c5d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274132035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.274132035
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3037947778
Short name T88
Test name
Test status
Simulation time 27591666 ps
CPU time 0.75 seconds
Started Feb 29 12:43:12 PM PST 24
Finished Feb 29 12:43:14 PM PST 24
Peak memory 195984 kb
Host smart-42581ebd-2114-46b7-9462-f15ecfe1109e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037947778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3037947778
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1285255559
Short name T817
Test name
Test status
Simulation time 33273743 ps
CPU time 0.6 seconds
Started Feb 29 12:42:51 PM PST 24
Finished Feb 29 12:42:52 PM PST 24
Peak memory 195864 kb
Host smart-3a77e7e8-91d6-496c-a9ed-e2c1ea47bf2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285255559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1285255559
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1780499592
Short name T738
Test name
Test status
Simulation time 62298803 ps
CPU time 1.58 seconds
Started Feb 29 12:43:04 PM PST 24
Finished Feb 29 12:43:06 PM PST 24
Peak memory 198468 kb
Host smart-510c3e50-8bf8-4800-a02d-38e5308d1f10
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780499592 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1780499592
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3435483751
Short name T78
Test name
Test status
Simulation time 34279448 ps
CPU time 0.59 seconds
Started Feb 29 12:43:03 PM PST 24
Finished Feb 29 12:43:05 PM PST 24
Peak memory 195720 kb
Host smart-b432a246-f1f0-46b0-bc27-64d5864b6ad1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435483751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3435483751
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2454510535
Short name T831
Test name
Test status
Simulation time 14852359 ps
CPU time 0.58 seconds
Started Feb 29 12:43:10 PM PST 24
Finished Feb 29 12:43:11 PM PST 24
Peak memory 194068 kb
Host smart-c79f5786-1d5a-4536-ace1-87ae7226af29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454510535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2454510535
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.4098241010
Short name T845
Test name
Test status
Simulation time 60769840 ps
CPU time 0.87 seconds
Started Feb 29 12:43:14 PM PST 24
Finished Feb 29 12:43:15 PM PST 24
Peak memory 196872 kb
Host smart-0a889a14-8f72-4a30-aa73-21c8add628b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098241010 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.4098241010
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1259266016
Short name T742
Test name
Test status
Simulation time 127663937 ps
CPU time 2.62 seconds
Started Feb 29 12:42:52 PM PST 24
Finished Feb 29 12:42:54 PM PST 24
Peak memory 198408 kb
Host smart-64a936ed-be9b-4aa3-a5d2-c5e2d97e74e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259266016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1259266016
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1672128601
Short name T774
Test name
Test status
Simulation time 84266609 ps
CPU time 0.87 seconds
Started Feb 29 12:42:49 PM PST 24
Finished Feb 29 12:42:50 PM PST 24
Peak memory 197548 kb
Host smart-d4459612-32cc-44a5-9644-4976b1d998ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672128601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1672128601
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3380294535
Short name T104
Test name
Test status
Simulation time 213044769 ps
CPU time 0.85 seconds
Started Feb 29 12:43:02 PM PST 24
Finished Feb 29 12:43:03 PM PST 24
Peak memory 196580 kb
Host smart-f9b93a85-16e4-40c6-a3e7-a27e4e1b1ad0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380294535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3380294535
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.479578460
Short name T836
Test name
Test status
Simulation time 243130773 ps
CPU time 2.97 seconds
Started Feb 29 12:43:17 PM PST 24
Finished Feb 29 12:43:21 PM PST 24
Peak memory 197224 kb
Host smart-d811b5e8-723d-4217-8bd5-81e83b4a54e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479578460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.479578460
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3898420239
Short name T771
Test name
Test status
Simulation time 13119003 ps
CPU time 0.61 seconds
Started Feb 29 12:43:17 PM PST 24
Finished Feb 29 12:43:18 PM PST 24
Peak memory 194948 kb
Host smart-558d76d7-1117-4c69-805a-fa122cdaaf22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898420239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3898420239
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3029213539
Short name T769
Test name
Test status
Simulation time 23041275 ps
CPU time 0.76 seconds
Started Feb 29 12:42:56 PM PST 24
Finished Feb 29 12:42:58 PM PST 24
Peak memory 197916 kb
Host smart-b0e445be-131d-404c-8df0-8f5a309df870
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029213539 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3029213539
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.566159833
Short name T739
Test name
Test status
Simulation time 14241126 ps
CPU time 0.6 seconds
Started Feb 29 12:42:55 PM PST 24
Finished Feb 29 12:42:55 PM PST 24
Peak memory 195052 kb
Host smart-ed612aec-47d7-4f59-9620-58b645cddaa7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566159833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.566159833
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2460403811
Short name T818
Test name
Test status
Simulation time 23742094 ps
CPU time 0.6 seconds
Started Feb 29 12:43:15 PM PST 24
Finished Feb 29 12:43:16 PM PST 24
Peak memory 194644 kb
Host smart-9dab4734-bba1-4b6f-91f1-ddecb6364c04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460403811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2460403811
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.88943873
Short name T754
Test name
Test status
Simulation time 54338295 ps
CPU time 1.13 seconds
Started Feb 29 12:42:54 PM PST 24
Finished Feb 29 12:42:55 PM PST 24
Peak memory 198404 kb
Host smart-6a6e64b4-05ad-4199-9e91-bc036883e979
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88943873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.88943873
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3380002516
Short name T827
Test name
Test status
Simulation time 390603167 ps
CPU time 0.9 seconds
Started Feb 29 12:43:07 PM PST 24
Finished Feb 29 12:43:08 PM PST 24
Peak memory 197564 kb
Host smart-b7b9d430-33b3-47c7-9f7e-6dac47b451a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380002516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3380002516
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.4035170689
Short name T722
Test name
Test status
Simulation time 142488907 ps
CPU time 0.95 seconds
Started Feb 29 12:43:55 PM PST 24
Finished Feb 29 12:43:56 PM PST 24
Peak memory 198284 kb
Host smart-0fae9bee-4eb7-4005-bba4-6c65d7700411
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035170689 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.4035170689
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1517023874
Short name T759
Test name
Test status
Simulation time 35388086 ps
CPU time 0.58 seconds
Started Feb 29 12:43:37 PM PST 24
Finished Feb 29 12:43:37 PM PST 24
Peak memory 194872 kb
Host smart-18e2707b-7548-4192-bfbd-f8aa0177c4be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517023874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1517023874
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.213668681
Short name T734
Test name
Test status
Simulation time 32371861 ps
CPU time 0.58 seconds
Started Feb 29 12:43:27 PM PST 24
Finished Feb 29 12:43:27 PM PST 24
Peak memory 194112 kb
Host smart-198e35ab-c19e-458b-92cc-d272ff6299e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213668681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.213668681
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3205396488
Short name T98
Test name
Test status
Simulation time 114142595 ps
CPU time 0.83 seconds
Started Feb 29 12:43:31 PM PST 24
Finished Feb 29 12:43:32 PM PST 24
Peak memory 196648 kb
Host smart-7b8a99ac-f635-4032-b39b-46a99ab0cdbd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205396488 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3205396488
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2116277462
Short name T843
Test name
Test status
Simulation time 328011320 ps
CPU time 1.7 seconds
Started Feb 29 12:43:42 PM PST 24
Finished Feb 29 12:43:44 PM PST 24
Peak memory 198340 kb
Host smart-6326a18d-1436-4805-96f4-de7071cb864e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116277462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2116277462
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.156846035
Short name T828
Test name
Test status
Simulation time 78166859 ps
CPU time 0.9 seconds
Started Feb 29 12:43:23 PM PST 24
Finished Feb 29 12:43:24 PM PST 24
Peak memory 198132 kb
Host smart-99ed5634-e2b6-4aae-9b2a-6620412cc77e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156846035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.156846035
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2314516678
Short name T763
Test name
Test status
Simulation time 133545637 ps
CPU time 0.96 seconds
Started Feb 29 12:43:21 PM PST 24
Finished Feb 29 12:43:22 PM PST 24
Peak memory 198268 kb
Host smart-a1d442aa-a1bf-4f97-974f-abdb6cb6c873
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314516678 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2314516678
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.4142268136
Short name T85
Test name
Test status
Simulation time 24050129 ps
CPU time 0.58 seconds
Started Feb 29 12:43:15 PM PST 24
Finished Feb 29 12:43:16 PM PST 24
Peak memory 193624 kb
Host smart-56e75960-eb73-49d8-98b9-857fe110ec24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142268136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.4142268136
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1042116935
Short name T726
Test name
Test status
Simulation time 40911493 ps
CPU time 0.65 seconds
Started Feb 29 12:43:20 PM PST 24
Finished Feb 29 12:43:21 PM PST 24
Peak memory 194180 kb
Host smart-a9d6bd5d-7a3b-4cbd-9ed2-f820679e53c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042116935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1042116935
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1312197863
Short name T813
Test name
Test status
Simulation time 374188226 ps
CPU time 0.85 seconds
Started Feb 29 12:43:26 PM PST 24
Finished Feb 29 12:43:27 PM PST 24
Peak memory 196600 kb
Host smart-ccb6474c-afd4-4a03-8eec-61f8dc3b6f0b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312197863 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1312197863
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2502001967
Short name T795
Test name
Test status
Simulation time 20660765 ps
CPU time 1.05 seconds
Started Feb 29 12:43:28 PM PST 24
Finished Feb 29 12:43:30 PM PST 24
Peak memory 198200 kb
Host smart-b8e4748d-d23f-4db3-9e7e-cb66ce51c561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502001967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2502001967
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2065754166
Short name T821
Test name
Test status
Simulation time 84255060 ps
CPU time 1.16 seconds
Started Feb 29 12:43:23 PM PST 24
Finished Feb 29 12:43:25 PM PST 24
Peak memory 198012 kb
Host smart-63d3699b-02f8-4b2b-b246-fe7a1abd45ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065754166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2065754166
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3158688647
Short name T729
Test name
Test status
Simulation time 21249497 ps
CPU time 0.7 seconds
Started Feb 29 12:43:20 PM PST 24
Finished Feb 29 12:43:21 PM PST 24
Peak memory 198012 kb
Host smart-55380014-cf13-44a3-9e3c-7392b068935f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158688647 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3158688647
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3427283053
Short name T737
Test name
Test status
Simulation time 15096129 ps
CPU time 0.63 seconds
Started Feb 29 12:43:21 PM PST 24
Finished Feb 29 12:43:21 PM PST 24
Peak memory 194956 kb
Host smart-83ca47d0-0bcf-4ae0-9549-d8ce6521d35e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427283053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3427283053
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.453217402
Short name T801
Test name
Test status
Simulation time 44303032 ps
CPU time 0.6 seconds
Started Feb 29 12:43:31 PM PST 24
Finished Feb 29 12:43:32 PM PST 24
Peak memory 194144 kb
Host smart-83b23a7f-5d94-4bc1-8c26-eb4fc9812ead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453217402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.453217402
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3757316946
Short name T798
Test name
Test status
Simulation time 55643607 ps
CPU time 0.79 seconds
Started Feb 29 12:43:19 PM PST 24
Finished Feb 29 12:43:21 PM PST 24
Peak memory 196804 kb
Host smart-5f33c85b-f8a0-4aaa-abe3-60a321b25a70
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757316946 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3757316946
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2643549669
Short name T724
Test name
Test status
Simulation time 80370205 ps
CPU time 2.14 seconds
Started Feb 29 12:43:25 PM PST 24
Finished Feb 29 12:43:27 PM PST 24
Peak memory 198644 kb
Host smart-8845ea10-bb36-45b1-a768-b101ec7ab48c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643549669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2643549669
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.905095513
Short name T789
Test name
Test status
Simulation time 72420840 ps
CPU time 0.89 seconds
Started Feb 29 12:43:19 PM PST 24
Finished Feb 29 12:43:20 PM PST 24
Peak memory 197484 kb
Host smart-0243f518-0cc6-4159-8327-498a23bb9100
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905095513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.905095513
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1686873956
Short name T839
Test name
Test status
Simulation time 202662791 ps
CPU time 0.7 seconds
Started Feb 29 12:43:18 PM PST 24
Finished Feb 29 12:43:19 PM PST 24
Peak memory 198176 kb
Host smart-81b4f5cc-5cb2-42ba-934a-a9e71e9f80db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686873956 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1686873956
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1393947742
Short name T837
Test name
Test status
Simulation time 20788987 ps
CPU time 0.57 seconds
Started Feb 29 12:43:29 PM PST 24
Finished Feb 29 12:43:30 PM PST 24
Peak memory 195564 kb
Host smart-3335629c-ab97-451c-895f-3bab2bfb1921
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393947742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1393947742
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3477043769
Short name T808
Test name
Test status
Simulation time 33948890 ps
CPU time 0.62 seconds
Started Feb 29 12:43:27 PM PST 24
Finished Feb 29 12:43:28 PM PST 24
Peak memory 194088 kb
Host smart-bb1ddbbc-10b8-4dde-9367-c5a82c32863b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477043769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3477043769
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3339144487
Short name T782
Test name
Test status
Simulation time 31329054 ps
CPU time 0.73 seconds
Started Feb 29 12:43:18 PM PST 24
Finished Feb 29 12:43:19 PM PST 24
Peak memory 197004 kb
Host smart-03bebe16-d48b-45aa-9a58-b6daf3f78c8a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339144487 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3339144487
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1962122196
Short name T794
Test name
Test status
Simulation time 36996217 ps
CPU time 2.07 seconds
Started Feb 29 12:43:21 PM PST 24
Finished Feb 29 12:43:23 PM PST 24
Peak memory 198356 kb
Host smart-50da3061-8bbb-4037-a49d-68f0d537354a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962122196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1962122196
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1187618192
Short name T29
Test name
Test status
Simulation time 148840378 ps
CPU time 0.85 seconds
Started Feb 29 12:43:33 PM PST 24
Finished Feb 29 12:43:35 PM PST 24
Peak memory 197680 kb
Host smart-042b1418-40d5-42ff-9ec5-57b6a787e92c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187618192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1187618192
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3923857633
Short name T748
Test name
Test status
Simulation time 36315514 ps
CPU time 1.56 seconds
Started Feb 29 12:43:49 PM PST 24
Finished Feb 29 12:43:51 PM PST 24
Peak memory 198512 kb
Host smart-f36d23eb-3b01-465d-a576-3345479fbfe0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923857633 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3923857633
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2536247551
Short name T820
Test name
Test status
Simulation time 15753423 ps
CPU time 0.58 seconds
Started Feb 29 12:43:16 PM PST 24
Finished Feb 29 12:43:18 PM PST 24
Peak memory 194936 kb
Host smart-313cb195-5e09-4985-baca-e93b05f4c7fd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536247551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2536247551
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2604951374
Short name T762
Test name
Test status
Simulation time 43048620 ps
CPU time 0.58 seconds
Started Feb 29 12:43:16 PM PST 24
Finished Feb 29 12:43:17 PM PST 24
Peak memory 194052 kb
Host smart-56957091-1327-42f9-89eb-cf6865901973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604951374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2604951374
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2852901815
Short name T103
Test name
Test status
Simulation time 59738812 ps
CPU time 0.71 seconds
Started Feb 29 12:43:16 PM PST 24
Finished Feb 29 12:43:18 PM PST 24
Peak memory 196272 kb
Host smart-f7524d52-17ea-4f85-a0f5-7b1f06c3fb0b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852901815 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2852901815
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3429600336
Short name T793
Test name
Test status
Simulation time 171005941 ps
CPU time 2.55 seconds
Started Feb 29 12:43:15 PM PST 24
Finished Feb 29 12:43:18 PM PST 24
Peak memory 198372 kb
Host smart-3f6bc7ab-8609-4879-acd5-8a16921ee152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429600336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3429600336
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1040291774
Short name T783
Test name
Test status
Simulation time 111121613 ps
CPU time 0.87 seconds
Started Feb 29 12:43:17 PM PST 24
Finished Feb 29 12:43:19 PM PST 24
Peak memory 198288 kb
Host smart-9f8a4774-51c9-435e-9d59-c0d44ad47a8c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040291774 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1040291774
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.4163017014
Short name T92
Test name
Test status
Simulation time 32649170 ps
CPU time 0.6 seconds
Started Feb 29 12:43:29 PM PST 24
Finished Feb 29 12:43:35 PM PST 24
Peak memory 195188 kb
Host smart-d4d5c027-8b6d-466a-98dd-9a053bc4aa88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163017014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.4163017014
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2447369712
Short name T809
Test name
Test status
Simulation time 14545375 ps
CPU time 0.57 seconds
Started Feb 29 12:43:22 PM PST 24
Finished Feb 29 12:43:22 PM PST 24
Peak memory 194680 kb
Host smart-07951ab9-8b1e-4d7c-9cb2-d9a9e9cd2018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447369712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2447369712
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3364235392
Short name T102
Test name
Test status
Simulation time 114477955 ps
CPU time 0.72 seconds
Started Feb 29 12:43:26 PM PST 24
Finished Feb 29 12:43:27 PM PST 24
Peak memory 196396 kb
Host smart-e20ac478-3744-44b1-8165-a022cb88574e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364235392 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3364235392
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2304653866
Short name T765
Test name
Test status
Simulation time 42771789 ps
CPU time 2.15 seconds
Started Feb 29 12:43:25 PM PST 24
Finished Feb 29 12:43:28 PM PST 24
Peak memory 198708 kb
Host smart-633d16ca-5f06-46da-9c83-3b15b3cd1fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304653866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2304653866
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.811331470
Short name T43
Test name
Test status
Simulation time 94621130 ps
CPU time 0.86 seconds
Started Feb 29 12:43:18 PM PST 24
Finished Feb 29 12:43:19 PM PST 24
Peak memory 197496 kb
Host smart-9a35c8bb-f8aa-4f2b-805f-3c40925f4a86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811331470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.811331470
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3518350353
Short name T822
Test name
Test status
Simulation time 71599539 ps
CPU time 1.81 seconds
Started Feb 29 12:43:28 PM PST 24
Finished Feb 29 12:43:30 PM PST 24
Peak memory 198444 kb
Host smart-ef83d66a-4482-4a01-931b-dae1f27aa0a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518350353 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3518350353
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1357510720
Short name T80
Test name
Test status
Simulation time 15565346 ps
CPU time 0.6 seconds
Started Feb 29 12:43:16 PM PST 24
Finished Feb 29 12:43:17 PM PST 24
Peak memory 193640 kb
Host smart-fbf0e67b-1166-405f-aa49-8ffc997dc828
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357510720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1357510720
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2047718924
Short name T764
Test name
Test status
Simulation time 102039350 ps
CPU time 0.62 seconds
Started Feb 29 12:43:49 PM PST 24
Finished Feb 29 12:43:50 PM PST 24
Peak memory 194056 kb
Host smart-925d1b34-5cc6-4b0e-8f58-2af9be8485b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047718924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2047718924
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1129536
Short name T811
Test name
Test status
Simulation time 13233783 ps
CPU time 0.62 seconds
Started Feb 29 12:43:19 PM PST 24
Finished Feb 29 12:43:21 PM PST 24
Peak memory 194888 kb
Host smart-6e7605d9-78a4-4301-83c9-4db34201b55c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129536 -assert nopostproc +UVM_TESTNAME=gpio_base_
test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.gpio_same_csr_outstanding.1129536
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1113793490
Short name T815
Test name
Test status
Simulation time 133831198 ps
CPU time 1.79 seconds
Started Feb 29 12:43:22 PM PST 24
Finished Feb 29 12:43:24 PM PST 24
Peak memory 198484 kb
Host smart-12a69f48-5e1d-4358-96de-10b8854d5a35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113793490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1113793490
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3821832936
Short name T40
Test name
Test status
Simulation time 135922151 ps
CPU time 1.37 seconds
Started Feb 29 12:43:19 PM PST 24
Finished Feb 29 12:43:21 PM PST 24
Peak memory 198456 kb
Host smart-924e4920-4377-4c17-bcc3-25b776f5d644
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821832936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3821832936
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2698919032
Short name T728
Test name
Test status
Simulation time 32759019 ps
CPU time 0.84 seconds
Started Feb 29 12:43:29 PM PST 24
Finished Feb 29 12:43:30 PM PST 24
Peak memory 198196 kb
Host smart-a6ce2c30-e072-419f-ae4e-5fefb4ca3fad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698919032 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2698919032
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3955413541
Short name T82
Test name
Test status
Simulation time 15128050 ps
CPU time 0.68 seconds
Started Feb 29 12:43:14 PM PST 24
Finished Feb 29 12:43:16 PM PST 24
Peak memory 195244 kb
Host smart-8d3c6b62-7afc-41b8-8e4c-599e88818435
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955413541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3955413541
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2343380191
Short name T720
Test name
Test status
Simulation time 57984638 ps
CPU time 0.61 seconds
Started Feb 29 12:43:20 PM PST 24
Finished Feb 29 12:43:21 PM PST 24
Peak memory 194172 kb
Host smart-1981e1f4-7e36-4479-a43c-44da94bb4ede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343380191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2343380191
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3344852872
Short name T99
Test name
Test status
Simulation time 60519735 ps
CPU time 0.66 seconds
Started Feb 29 12:43:18 PM PST 24
Finished Feb 29 12:43:19 PM PST 24
Peak memory 195904 kb
Host smart-b1cf031a-efc3-4985-b3c5-4e2d2a78c5be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344852872 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3344852872
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1879199121
Short name T756
Test name
Test status
Simulation time 161355769 ps
CPU time 1.58 seconds
Started Feb 29 12:43:17 PM PST 24
Finished Feb 29 12:43:19 PM PST 24
Peak memory 198396 kb
Host smart-8b68ad32-db8a-4731-ae4c-4a56b5a309e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879199121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1879199121
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1173405639
Short name T842
Test name
Test status
Simulation time 1999033257 ps
CPU time 1.37 seconds
Started Feb 29 12:43:25 PM PST 24
Finished Feb 29 12:43:26 PM PST 24
Peak memory 198428 kb
Host smart-4e4c0dd8-3929-4e37-9642-1818f216fc01
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173405639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1173405639
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.912217996
Short name T750
Test name
Test status
Simulation time 73942793 ps
CPU time 0.71 seconds
Started Feb 29 12:43:22 PM PST 24
Finished Feb 29 12:43:23 PM PST 24
Peak memory 198168 kb
Host smart-f96fcc90-8462-40a9-8e82-870fce9bd3ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912217996 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.912217996
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1675415515
Short name T833
Test name
Test status
Simulation time 62016341 ps
CPU time 0.61 seconds
Started Feb 29 12:43:34 PM PST 24
Finished Feb 29 12:43:35 PM PST 24
Peak memory 194064 kb
Host smart-95d5f125-3569-4eb8-884d-093cd0ccba7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675415515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1675415515
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.4026753182
Short name T804
Test name
Test status
Simulation time 28262650 ps
CPU time 0.65 seconds
Started Feb 29 12:43:24 PM PST 24
Finished Feb 29 12:43:24 PM PST 24
Peak memory 195160 kb
Host smart-5536467e-ff9e-4e75-ac60-6131498f1ec4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026753182 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.4026753182
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.689796864
Short name T736
Test name
Test status
Simulation time 469517151 ps
CPU time 3.46 seconds
Started Feb 29 12:43:16 PM PST 24
Finished Feb 29 12:43:20 PM PST 24
Peak memory 198408 kb
Host smart-9b1d5809-9255-4422-962e-52e58c36ffe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689796864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.689796864
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2296528326
Short name T41
Test name
Test status
Simulation time 279702076 ps
CPU time 1.2 seconds
Started Feb 29 12:43:22 PM PST 24
Finished Feb 29 12:43:23 PM PST 24
Peak memory 198340 kb
Host smart-ecaa428a-4705-4d51-aba2-fcafdcd0150a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296528326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2296528326
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.360831982
Short name T755
Test name
Test status
Simulation time 76690455 ps
CPU time 0.99 seconds
Started Feb 29 12:43:27 PM PST 24
Finished Feb 29 12:43:28 PM PST 24
Peak memory 198136 kb
Host smart-468e7cd7-8f7a-4cda-b472-4a7283b30485
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360831982 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.360831982
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2239030244
Short name T95
Test name
Test status
Simulation time 30524718 ps
CPU time 0.61 seconds
Started Feb 29 12:43:27 PM PST 24
Finished Feb 29 12:43:28 PM PST 24
Peak memory 194928 kb
Host smart-fbd39914-fa61-4c71-83d7-34b86c8419f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239030244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2239030244
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1103341757
Short name T829
Test name
Test status
Simulation time 45313053 ps
CPU time 0.57 seconds
Started Feb 29 12:43:27 PM PST 24
Finished Feb 29 12:43:27 PM PST 24
Peak memory 194684 kb
Host smart-1477cd24-670d-4f2c-8898-f2b4686d76a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103341757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1103341757
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1553652531
Short name T96
Test name
Test status
Simulation time 20828105 ps
CPU time 0.62 seconds
Started Feb 29 12:43:17 PM PST 24
Finished Feb 29 12:43:18 PM PST 24
Peak memory 195132 kb
Host smart-a85d0fdc-bec1-4ff9-afdf-7ab38e8e072a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553652531 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1553652531
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.4037565438
Short name T740
Test name
Test status
Simulation time 182265188 ps
CPU time 3.18 seconds
Started Feb 29 12:43:30 PM PST 24
Finished Feb 29 12:43:33 PM PST 24
Peak memory 198532 kb
Host smart-c4353ad8-7211-4541-9c69-a62935f749e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037565438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.4037565438
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.454948130
Short name T39
Test name
Test status
Simulation time 541031403 ps
CPU time 0.85 seconds
Started Feb 29 12:43:35 PM PST 24
Finished Feb 29 12:43:36 PM PST 24
Peak memory 198432 kb
Host smart-338737fd-496f-48ed-9483-7ab83a7bd61e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454948130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.454948130
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2112463910
Short name T735
Test name
Test status
Simulation time 56676903 ps
CPU time 0.67 seconds
Started Feb 29 12:43:08 PM PST 24
Finished Feb 29 12:43:09 PM PST 24
Peak memory 194840 kb
Host smart-cfb65df9-76d7-4a2f-ba1f-f1678e5290c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112463910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2112463910
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.4283902291
Short name T81
Test name
Test status
Simulation time 315592979 ps
CPU time 2.97 seconds
Started Feb 29 12:43:29 PM PST 24
Finished Feb 29 12:43:32 PM PST 24
Peak memory 197536 kb
Host smart-c9544607-ddff-4c9c-b567-36675abe21bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283902291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.4283902291
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.783610535
Short name T86
Test name
Test status
Simulation time 14613871 ps
CPU time 0.6 seconds
Started Feb 29 12:43:09 PM PST 24
Finished Feb 29 12:43:10 PM PST 24
Peak memory 195008 kb
Host smart-62b5fff2-1b34-437e-8668-b42c0832a84f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783610535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.783610535
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1369496176
Short name T819
Test name
Test status
Simulation time 20209401 ps
CPU time 0.8 seconds
Started Feb 29 12:43:09 PM PST 24
Finished Feb 29 12:43:10 PM PST 24
Peak memory 198328 kb
Host smart-b9ad37d1-5c77-4c5d-9a37-f174a050e967
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369496176 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1369496176
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.458286358
Short name T803
Test name
Test status
Simulation time 13277060 ps
CPU time 0.61 seconds
Started Feb 29 12:43:09 PM PST 24
Finished Feb 29 12:43:10 PM PST 24
Peak memory 195664 kb
Host smart-7b514b37-6663-4cd5-9f1b-f490ba865661
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458286358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.458286358
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.409588533
Short name T758
Test name
Test status
Simulation time 17134925 ps
CPU time 0.64 seconds
Started Feb 29 12:43:22 PM PST 24
Finished Feb 29 12:43:23 PM PST 24
Peak memory 193984 kb
Host smart-5e3932ac-114e-425b-a183-fccb0b136e4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409588533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.409588533
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2292906230
Short name T97
Test name
Test status
Simulation time 17398169 ps
CPU time 0.68 seconds
Started Feb 29 12:43:16 PM PST 24
Finished Feb 29 12:43:17 PM PST 24
Peak memory 195096 kb
Host smart-2529ed15-cc3f-45ab-bc7d-4968ef50a384
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292906230 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2292906230
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.154795920
Short name T746
Test name
Test status
Simulation time 1643906486 ps
CPU time 1.71 seconds
Started Feb 29 12:43:07 PM PST 24
Finished Feb 29 12:43:09 PM PST 24
Peak memory 198456 kb
Host smart-2dc29871-d53a-48db-b131-4c66c9576846
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154795920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.154795920
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1982299936
Short name T719
Test name
Test status
Simulation time 36438099 ps
CPU time 0.55 seconds
Started Feb 29 12:43:21 PM PST 24
Finished Feb 29 12:43:22 PM PST 24
Peak memory 194596 kb
Host smart-d4750587-c3f5-490c-a8fc-2f4eeafd412b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982299936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1982299936
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2814846662
Short name T725
Test name
Test status
Simulation time 38776200 ps
CPU time 0.59 seconds
Started Feb 29 12:43:32 PM PST 24
Finished Feb 29 12:43:33 PM PST 24
Peak memory 194028 kb
Host smart-406f8198-756b-4eea-b5d1-bba99537eed8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814846662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2814846662
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.4011937397
Short name T744
Test name
Test status
Simulation time 13564878 ps
CPU time 0.63 seconds
Started Feb 29 12:43:25 PM PST 24
Finished Feb 29 12:43:26 PM PST 24
Peak memory 194356 kb
Host smart-d6fc6223-2ac8-4f36-ac75-3c1b517a14a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011937397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.4011937397
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1692561935
Short name T814
Test name
Test status
Simulation time 43360064 ps
CPU time 0.61 seconds
Started Feb 29 12:43:36 PM PST 24
Finished Feb 29 12:43:37 PM PST 24
Peak memory 194084 kb
Host smart-0f596fdb-46f0-4e0b-943c-db499440414f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692561935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1692561935
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1076329376
Short name T788
Test name
Test status
Simulation time 13571211 ps
CPU time 0.56 seconds
Started Feb 29 12:43:33 PM PST 24
Finished Feb 29 12:43:34 PM PST 24
Peak memory 193964 kb
Host smart-e9647aed-0bad-4f95-8b5d-d95aa62d1e78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076329376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1076329376
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3476568517
Short name T731
Test name
Test status
Simulation time 13234636 ps
CPU time 0.57 seconds
Started Feb 29 12:43:44 PM PST 24
Finished Feb 29 12:43:45 PM PST 24
Peak memory 194664 kb
Host smart-8df5740d-ae6d-4a4c-80bd-f4ee6e6f399d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476568517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3476568517
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2697816396
Short name T792
Test name
Test status
Simulation time 215325459 ps
CPU time 0.58 seconds
Started Feb 29 12:43:43 PM PST 24
Finished Feb 29 12:43:44 PM PST 24
Peak memory 194788 kb
Host smart-1020d5b0-2fb6-419a-a7c3-d0ca0cffdf85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697816396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2697816396
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1363180884
Short name T772
Test name
Test status
Simulation time 45391059 ps
CPU time 0.55 seconds
Started Feb 29 12:43:27 PM PST 24
Finished Feb 29 12:43:28 PM PST 24
Peak memory 194688 kb
Host smart-83f362d6-a076-4663-9798-d6efef8067ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363180884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1363180884
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3555271347
Short name T730
Test name
Test status
Simulation time 22143393 ps
CPU time 0.59 seconds
Started Feb 29 12:43:24 PM PST 24
Finished Feb 29 12:43:25 PM PST 24
Peak memory 194040 kb
Host smart-8bc08030-eaaa-4347-a49d-66797aa7b5f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555271347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3555271347
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3417533563
Short name T796
Test name
Test status
Simulation time 45592754 ps
CPU time 0.6 seconds
Started Feb 29 12:43:53 PM PST 24
Finished Feb 29 12:43:54 PM PST 24
Peak memory 194092 kb
Host smart-44b6a64a-a6f5-49e9-bbcd-69d4aed56abc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417533563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3417533563
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.527080856
Short name T90
Test name
Test status
Simulation time 24916980 ps
CPU time 0.65 seconds
Started Feb 29 12:43:21 PM PST 24
Finished Feb 29 12:43:22 PM PST 24
Peak memory 194856 kb
Host smart-11c8bca9-cb69-4869-9366-3b0cbe3cd286
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527080856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.527080856
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4269922688
Short name T840
Test name
Test status
Simulation time 61326277 ps
CPU time 2.09 seconds
Started Feb 29 12:43:11 PM PST 24
Finished Feb 29 12:43:13 PM PST 24
Peak memory 196976 kb
Host smart-ce72c5f2-e04c-4059-b777-23a22ba4bd0e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269922688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.4269922688
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.302464159
Short name T87
Test name
Test status
Simulation time 110790782 ps
CPU time 0.65 seconds
Started Feb 29 12:43:08 PM PST 24
Finished Feb 29 12:43:09 PM PST 24
Peak memory 195212 kb
Host smart-fe244e37-5933-47cd-a5ae-11fa674f4708
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302464159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.302464159
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3902429196
Short name T785
Test name
Test status
Simulation time 45693403 ps
CPU time 0.63 seconds
Started Feb 29 12:43:18 PM PST 24
Finished Feb 29 12:43:18 PM PST 24
Peak memory 196860 kb
Host smart-6df10e53-c4c6-412c-b029-c2ee8704bfe6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902429196 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3902429196
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2229151940
Short name T805
Test name
Test status
Simulation time 18915924 ps
CPU time 0.57 seconds
Started Feb 29 12:43:08 PM PST 24
Finished Feb 29 12:43:09 PM PST 24
Peak memory 193584 kb
Host smart-eab6f60a-c266-420d-b200-d6aa51f4c6aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229151940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2229151940
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.4121066992
Short name T781
Test name
Test status
Simulation time 19184696 ps
CPU time 0.64 seconds
Started Feb 29 12:43:13 PM PST 24
Finished Feb 29 12:43:14 PM PST 24
Peak memory 194068 kb
Host smart-2ea10344-a83b-41bf-900b-e3e9775f981b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121066992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.4121066992
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2375166674
Short name T101
Test name
Test status
Simulation time 19159645 ps
CPU time 0.75 seconds
Started Feb 29 12:43:15 PM PST 24
Finished Feb 29 12:43:16 PM PST 24
Peak memory 196564 kb
Host smart-050423ac-bab1-4ef6-98d7-3c14d5239583
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375166674 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2375166674
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.1034674564
Short name T826
Test name
Test status
Simulation time 119677810 ps
CPU time 1.44 seconds
Started Feb 29 12:43:13 PM PST 24
Finished Feb 29 12:43:15 PM PST 24
Peak memory 198492 kb
Host smart-41b1f595-5910-4abd-96d8-8aee41009c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034674564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.1034674564
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2024381812
Short name T766
Test name
Test status
Simulation time 407862887 ps
CPU time 1.35 seconds
Started Feb 29 12:43:12 PM PST 24
Finished Feb 29 12:43:13 PM PST 24
Peak memory 198380 kb
Host smart-0eace76f-7525-4aa7-8a28-266612c39cca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024381812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2024381812
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2823322499
Short name T830
Test name
Test status
Simulation time 76730023 ps
CPU time 0.56 seconds
Started Feb 29 12:43:37 PM PST 24
Finished Feb 29 12:43:38 PM PST 24
Peak memory 194680 kb
Host smart-b2099afe-1981-4017-a149-0f283ded8cb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823322499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2823322499
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.4158187225
Short name T787
Test name
Test status
Simulation time 30781869 ps
CPU time 0.55 seconds
Started Feb 29 12:43:39 PM PST 24
Finished Feb 29 12:43:40 PM PST 24
Peak memory 194040 kb
Host smart-032228d4-2032-401c-aea4-303c706a1824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158187225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.4158187225
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3125684764
Short name T791
Test name
Test status
Simulation time 187872374 ps
CPU time 0.61 seconds
Started Feb 29 12:43:44 PM PST 24
Finished Feb 29 12:43:44 PM PST 24
Peak memory 194684 kb
Host smart-1d15c20c-c0a3-47c6-8945-05bcfc32e497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125684764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3125684764
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.986742337
Short name T810
Test name
Test status
Simulation time 18211832 ps
CPU time 0.55 seconds
Started Feb 29 12:43:30 PM PST 24
Finished Feb 29 12:43:31 PM PST 24
Peak memory 194124 kb
Host smart-e53f77dd-1e88-45c4-ab8d-5e45950505c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986742337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.986742337
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.849710752
Short name T825
Test name
Test status
Simulation time 13257056 ps
CPU time 0.56 seconds
Started Feb 29 12:43:41 PM PST 24
Finished Feb 29 12:43:42 PM PST 24
Peak memory 194060 kb
Host smart-472ac5ba-9583-4468-939e-f35710522d23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849710752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.849710752
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.667865365
Short name T799
Test name
Test status
Simulation time 13925177 ps
CPU time 0.62 seconds
Started Feb 29 12:43:28 PM PST 24
Finished Feb 29 12:43:29 PM PST 24
Peak memory 194152 kb
Host smart-6b3ed94d-77fc-47bb-9138-5ff927c2e747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667865365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.667865365
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.825724148
Short name T751
Test name
Test status
Simulation time 15722667 ps
CPU time 0.64 seconds
Started Feb 29 12:43:28 PM PST 24
Finished Feb 29 12:43:29 PM PST 24
Peak memory 194032 kb
Host smart-1e6f624e-acd8-48cc-8877-53aecc475815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825724148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.825724148
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1794216886
Short name T768
Test name
Test status
Simulation time 11128379 ps
CPU time 0.54 seconds
Started Feb 29 12:43:27 PM PST 24
Finished Feb 29 12:43:28 PM PST 24
Peak memory 194628 kb
Host smart-5c8de96e-5aff-42d5-894e-4e36b2c06328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794216886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1794216886
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3005927253
Short name T823
Test name
Test status
Simulation time 14859556 ps
CPU time 0.61 seconds
Started Feb 29 12:43:37 PM PST 24
Finished Feb 29 12:43:43 PM PST 24
Peak memory 194120 kb
Host smart-585502bd-8a06-42db-8508-1c0d614cfc04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005927253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3005927253
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3244976233
Short name T753
Test name
Test status
Simulation time 15649375 ps
CPU time 0.63 seconds
Started Feb 29 12:43:27 PM PST 24
Finished Feb 29 12:43:28 PM PST 24
Peak memory 194668 kb
Host smart-48a29446-e58f-4b9c-aa85-4f555a9f3bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244976233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3244976233
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3612293236
Short name T91
Test name
Test status
Simulation time 138940163 ps
CPU time 0.84 seconds
Started Feb 29 12:43:11 PM PST 24
Finished Feb 29 12:43:12 PM PST 24
Peak memory 196444 kb
Host smart-87674b91-11a1-45e4-aa4d-9c46f93941b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612293236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3612293236
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1290479889
Short name T93
Test name
Test status
Simulation time 66152096 ps
CPU time 1.41 seconds
Started Feb 29 12:43:18 PM PST 24
Finished Feb 29 12:43:20 PM PST 24
Peak memory 197812 kb
Host smart-071a9d6f-2eb3-413f-89c7-b5ac32055043
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290479889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1290479889
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2859605324
Short name T779
Test name
Test status
Simulation time 58591423 ps
CPU time 0.66 seconds
Started Feb 29 12:43:08 PM PST 24
Finished Feb 29 12:43:09 PM PST 24
Peak memory 195292 kb
Host smart-c4a788a7-3064-49ea-a611-1e89c3a4b217
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859605324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2859605324
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.220730142
Short name T824
Test name
Test status
Simulation time 69945937 ps
CPU time 0.73 seconds
Started Feb 29 12:43:15 PM PST 24
Finished Feb 29 12:43:17 PM PST 24
Peak memory 198224 kb
Host smart-622e4bc0-fd21-4962-a88e-8c7d3dab30ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220730142 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.220730142
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.172478835
Short name T77
Test name
Test status
Simulation time 31059069 ps
CPU time 0.61 seconds
Started Feb 29 12:43:12 PM PST 24
Finished Feb 29 12:43:12 PM PST 24
Peak memory 193636 kb
Host smart-f2a5339b-304c-451d-8e57-67377059d9d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172478835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.172478835
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2692066091
Short name T776
Test name
Test status
Simulation time 12988816 ps
CPU time 0.59 seconds
Started Feb 29 12:43:06 PM PST 24
Finished Feb 29 12:43:06 PM PST 24
Peak memory 194096 kb
Host smart-fb056336-fe01-48c9-aa9f-f0392ebcb925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692066091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2692066091
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2331302891
Short name T816
Test name
Test status
Simulation time 31708806 ps
CPU time 0.73 seconds
Started Feb 29 12:43:22 PM PST 24
Finished Feb 29 12:43:23 PM PST 24
Peak memory 196352 kb
Host smart-32ef0fc2-b390-4502-9cf6-672a4276c144
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331302891 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2331302891
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1140802796
Short name T749
Test name
Test status
Simulation time 241097025 ps
CPU time 1.97 seconds
Started Feb 29 12:43:07 PM PST 24
Finished Feb 29 12:43:09 PM PST 24
Peak memory 198404 kb
Host smart-dbf88902-f2ef-41d5-8b3c-ab6a85ca57c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140802796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1140802796
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.262271187
Short name T780
Test name
Test status
Simulation time 405252432 ps
CPU time 0.87 seconds
Started Feb 29 12:43:08 PM PST 24
Finished Feb 29 12:43:09 PM PST 24
Peak memory 198220 kb
Host smart-820f5b6d-4a46-4fc3-8b1f-dd13eb7173b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262271187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.262271187
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1229926466
Short name T800
Test name
Test status
Simulation time 20468560 ps
CPU time 0.56 seconds
Started Feb 29 12:43:34 PM PST 24
Finished Feb 29 12:43:35 PM PST 24
Peak memory 193996 kb
Host smart-1f936a5f-0747-404c-b9da-44f2b06f636a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229926466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1229926466
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.487107548
Short name T760
Test name
Test status
Simulation time 72737080 ps
CPU time 0.6 seconds
Started Feb 29 12:43:19 PM PST 24
Finished Feb 29 12:43:21 PM PST 24
Peak memory 194160 kb
Host smart-05f94e16-2c57-458c-a8fa-3e6e5c902527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487107548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.487107548
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1098352131
Short name T723
Test name
Test status
Simulation time 109230424 ps
CPU time 0.63 seconds
Started Feb 29 12:43:23 PM PST 24
Finished Feb 29 12:43:23 PM PST 24
Peak memory 194016 kb
Host smart-5ad0b489-6aee-4261-857f-9cf1374b567d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098352131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1098352131
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3260269351
Short name T741
Test name
Test status
Simulation time 43953499 ps
CPU time 0.57 seconds
Started Feb 29 12:43:37 PM PST 24
Finished Feb 29 12:43:38 PM PST 24
Peak memory 194736 kb
Host smart-0fe6e384-f1ae-4c02-be6f-efc224823d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260269351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3260269351
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.518330877
Short name T727
Test name
Test status
Simulation time 39175735 ps
CPU time 0.57 seconds
Started Feb 29 12:43:28 PM PST 24
Finished Feb 29 12:43:29 PM PST 24
Peak memory 194076 kb
Host smart-8192947a-6787-447f-8b1c-dd4f2371f8fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518330877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.518330877
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3528871146
Short name T743
Test name
Test status
Simulation time 19749945 ps
CPU time 0.6 seconds
Started Feb 29 12:43:27 PM PST 24
Finished Feb 29 12:43:28 PM PST 24
Peak memory 194092 kb
Host smart-28784e89-f94e-47be-9541-3169980fdfdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528871146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3528871146
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3041756915
Short name T790
Test name
Test status
Simulation time 13243412 ps
CPU time 0.57 seconds
Started Feb 29 12:43:37 PM PST 24
Finished Feb 29 12:43:38 PM PST 24
Peak memory 194036 kb
Host smart-808bfb2a-64cd-4b8d-a193-2d98dbddcaa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041756915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3041756915
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1580489048
Short name T834
Test name
Test status
Simulation time 13705386 ps
CPU time 0.59 seconds
Started Feb 29 12:43:22 PM PST 24
Finished Feb 29 12:43:22 PM PST 24
Peak memory 194760 kb
Host smart-e9a7f642-c660-4b49-b44a-24c034b83dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580489048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1580489048
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.4156766074
Short name T747
Test name
Test status
Simulation time 46424968 ps
CPU time 0.6 seconds
Started Feb 29 12:43:51 PM PST 24
Finished Feb 29 12:43:52 PM PST 24
Peak memory 194768 kb
Host smart-b34762df-c14e-4d2a-bd5b-2d8d3549749a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156766074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.4156766074
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2591859880
Short name T721
Test name
Test status
Simulation time 16755490 ps
CPU time 0.57 seconds
Started Feb 29 12:43:48 PM PST 24
Finished Feb 29 12:43:49 PM PST 24
Peak memory 194092 kb
Host smart-7b578d7b-bc40-4b48-8dc6-4dfe64906d70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591859880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2591859880
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1819141535
Short name T770
Test name
Test status
Simulation time 28879719 ps
CPU time 0.88 seconds
Started Feb 29 12:43:14 PM PST 24
Finished Feb 29 12:43:16 PM PST 24
Peak memory 198304 kb
Host smart-26b9cb04-2b9f-410c-a407-ddff5e968b7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819141535 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1819141535
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.438575649
Short name T797
Test name
Test status
Simulation time 12292478 ps
CPU time 0.59 seconds
Started Feb 29 12:43:10 PM PST 24
Finished Feb 29 12:43:11 PM PST 24
Peak memory 195348 kb
Host smart-c4ceeddd-c5b0-4b52-aeb9-6568040598aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438575649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.438575649
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.181181651
Short name T767
Test name
Test status
Simulation time 69994400 ps
CPU time 0.62 seconds
Started Feb 29 12:43:15 PM PST 24
Finished Feb 29 12:43:16 PM PST 24
Peak memory 194160 kb
Host smart-8cfdd15b-8dc5-4280-b00b-a90f0ca0307e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181181651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.181181651
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1964297235
Short name T83
Test name
Test status
Simulation time 31160564 ps
CPU time 0.77 seconds
Started Feb 29 12:43:23 PM PST 24
Finished Feb 29 12:43:23 PM PST 24
Peak memory 196436 kb
Host smart-2e4654f5-ff96-4c05-97e2-7799d4230ba8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964297235 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1964297235
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.207864857
Short name T841
Test name
Test status
Simulation time 44943373 ps
CPU time 1.2 seconds
Started Feb 29 12:43:06 PM PST 24
Finished Feb 29 12:43:07 PM PST 24
Peak memory 198488 kb
Host smart-6d4bb560-23db-4efd-8abb-7db1f9674ec0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207864857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.207864857
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2274029882
Short name T844
Test name
Test status
Simulation time 77426875 ps
CPU time 1.11 seconds
Started Feb 29 12:43:12 PM PST 24
Finished Feb 29 12:43:14 PM PST 24
Peak memory 198008 kb
Host smart-cf5cb06e-248c-46d9-a43f-afbbf173d568
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274029882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2274029882
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4176485849
Short name T757
Test name
Test status
Simulation time 139620259 ps
CPU time 0.78 seconds
Started Feb 29 12:43:14 PM PST 24
Finished Feb 29 12:43:15 PM PST 24
Peak memory 198196 kb
Host smart-8bc9efe3-56ff-4930-8882-78a7dd01f215
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176485849 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.4176485849
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.978912988
Short name T752
Test name
Test status
Simulation time 39946025 ps
CPU time 0.6 seconds
Started Feb 29 12:43:16 PM PST 24
Finished Feb 29 12:43:17 PM PST 24
Peak memory 195064 kb
Host smart-8c12166f-9e01-4eb0-aa43-91f0b28d745b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978912988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.978912988
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.446557561
Short name T832
Test name
Test status
Simulation time 11730754 ps
CPU time 0.61 seconds
Started Feb 29 12:43:11 PM PST 24
Finished Feb 29 12:43:11 PM PST 24
Peak memory 194684 kb
Host smart-147dbbf1-9bb1-43a2-ac37-d92b78bca9f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446557561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.446557561
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3642680658
Short name T778
Test name
Test status
Simulation time 61313078 ps
CPU time 0.88 seconds
Started Feb 29 12:43:09 PM PST 24
Finished Feb 29 12:43:10 PM PST 24
Peak memory 196492 kb
Host smart-42dabb25-6697-481b-ae7e-26a63b125058
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642680658 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3642680658
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.210512066
Short name T838
Test name
Test status
Simulation time 418025473 ps
CPU time 2.49 seconds
Started Feb 29 12:43:21 PM PST 24
Finished Feb 29 12:43:23 PM PST 24
Peak memory 198452 kb
Host smart-e70a72b5-fb50-4922-ab88-e022ad7d544c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210512066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.210512066
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1985688322
Short name T42
Test name
Test status
Simulation time 168310207 ps
CPU time 1.13 seconds
Started Feb 29 12:43:31 PM PST 24
Finished Feb 29 12:43:33 PM PST 24
Peak memory 198484 kb
Host smart-ebe88a68-883c-43bf-b823-b87af5e6869c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985688322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1985688322
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3699728037
Short name T732
Test name
Test status
Simulation time 244627127 ps
CPU time 0.94 seconds
Started Feb 29 12:43:31 PM PST 24
Finished Feb 29 12:43:32 PM PST 24
Peak memory 198260 kb
Host smart-6245c9c0-ea1b-48cb-95bd-af1424c21049
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699728037 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3699728037
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2332530864
Short name T806
Test name
Test status
Simulation time 21205084 ps
CPU time 0.62 seconds
Started Feb 29 12:43:07 PM PST 24
Finished Feb 29 12:43:07 PM PST 24
Peak memory 195732 kb
Host smart-a12e71cf-1e88-452e-9176-11364105592e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332530864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2332530864
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3113599742
Short name T775
Test name
Test status
Simulation time 23789372 ps
CPU time 0.57 seconds
Started Feb 29 12:43:17 PM PST 24
Finished Feb 29 12:43:18 PM PST 24
Peak memory 193988 kb
Host smart-a04c1be0-c916-4516-ab62-bff3e753cef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113599742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3113599742
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3287396425
Short name T802
Test name
Test status
Simulation time 18939456 ps
CPU time 0.66 seconds
Started Feb 29 12:43:08 PM PST 24
Finished Feb 29 12:43:09 PM PST 24
Peak memory 194756 kb
Host smart-22797b06-d174-492d-8148-d1784f1439bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287396425 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3287396425
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.263568161
Short name T761
Test name
Test status
Simulation time 313033809 ps
CPU time 1.4 seconds
Started Feb 29 12:43:14 PM PST 24
Finished Feb 29 12:43:16 PM PST 24
Peak memory 198396 kb
Host smart-ef393f79-68ae-4af2-9075-42575f64ca55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263568161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.263568161
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3394275264
Short name T30
Test name
Test status
Simulation time 41807088 ps
CPU time 0.85 seconds
Started Feb 29 12:43:15 PM PST 24
Finished Feb 29 12:43:17 PM PST 24
Peak memory 197264 kb
Host smart-e6f83444-e0c6-497e-87d4-1372be38a24b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394275264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3394275264
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.525164517
Short name T835
Test name
Test status
Simulation time 35864608 ps
CPU time 0.91 seconds
Started Feb 29 12:43:17 PM PST 24
Finished Feb 29 12:43:19 PM PST 24
Peak memory 198240 kb
Host smart-e477d5b0-6abd-4975-934c-6228187a7e81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525164517 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.525164517
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3507486001
Short name T733
Test name
Test status
Simulation time 12892194 ps
CPU time 0.6 seconds
Started Feb 29 12:43:03 PM PST 24
Finished Feb 29 12:43:04 PM PST 24
Peak memory 193684 kb
Host smart-36a56099-3461-46dc-8ff9-9b68f0275d2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507486001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3507486001
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1866480162
Short name T745
Test name
Test status
Simulation time 39388799 ps
CPU time 0.58 seconds
Started Feb 29 12:43:18 PM PST 24
Finished Feb 29 12:43:19 PM PST 24
Peak memory 194692 kb
Host smart-ffaba8fa-25ac-463b-b4ad-696c702a7cfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866480162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1866480162
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3455940375
Short name T84
Test name
Test status
Simulation time 138643184 ps
CPU time 0.89 seconds
Started Feb 29 12:43:01 PM PST 24
Finished Feb 29 12:43:03 PM PST 24
Peak memory 196572 kb
Host smart-cbee99ee-6d96-4dfc-ac5d-d70c98e024a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455940375 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3455940375
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3050569018
Short name T777
Test name
Test status
Simulation time 81644684 ps
CPU time 1.06 seconds
Started Feb 29 12:43:14 PM PST 24
Finished Feb 29 12:43:16 PM PST 24
Peak memory 198168 kb
Host smart-36a14dc0-21e5-4559-ba93-47f7014aacd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050569018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3050569018
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2691200410
Short name T38
Test name
Test status
Simulation time 72411783 ps
CPU time 1.13 seconds
Started Feb 29 12:43:09 PM PST 24
Finished Feb 29 12:43:10 PM PST 24
Peak memory 198384 kb
Host smart-d626a710-8e7d-4a2c-9f4f-21bba3affed8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691200410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2691200410
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2849133122
Short name T807
Test name
Test status
Simulation time 533804053 ps
CPU time 0.95 seconds
Started Feb 29 12:43:33 PM PST 24
Finished Feb 29 12:43:34 PM PST 24
Peak memory 198288 kb
Host smart-50978369-4f3d-4bea-a6cd-6c45508683ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849133122 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2849133122
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1175449642
Short name T89
Test name
Test status
Simulation time 37332609 ps
CPU time 0.61 seconds
Started Feb 29 12:43:28 PM PST 24
Finished Feb 29 12:43:28 PM PST 24
Peak memory 195372 kb
Host smart-b0dc9842-3bd0-4d42-a71c-5e81f4675715
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175449642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1175449642
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2810992643
Short name T773
Test name
Test status
Simulation time 39686180 ps
CPU time 0.6 seconds
Started Feb 29 12:43:29 PM PST 24
Finished Feb 29 12:43:30 PM PST 24
Peak memory 194248 kb
Host smart-d8cb1e5c-09c4-4c66-91bf-ff78ca867346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810992643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2810992643
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.636849697
Short name T812
Test name
Test status
Simulation time 139635901 ps
CPU time 0.87 seconds
Started Feb 29 12:43:30 PM PST 24
Finished Feb 29 12:43:31 PM PST 24
Peak memory 197520 kb
Host smart-635d847a-ed14-444f-b8aa-a5673f9a9b8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636849697 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.636849697
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3529492025
Short name T784
Test name
Test status
Simulation time 36100286 ps
CPU time 1.67 seconds
Started Feb 29 12:43:29 PM PST 24
Finished Feb 29 12:43:31 PM PST 24
Peak memory 198488 kb
Host smart-8e7aa8d3-d5eb-4363-a77e-cdc12af46294
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529492025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3529492025
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3353525207
Short name T31
Test name
Test status
Simulation time 128271338 ps
CPU time 1.34 seconds
Started Feb 29 12:43:24 PM PST 24
Finished Feb 29 12:43:25 PM PST 24
Peak memory 198404 kb
Host smart-25752c61-d58a-46f3-bb7b-736884f458dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353525207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3353525207
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3023888121
Short name T431
Test name
Test status
Simulation time 23783389 ps
CPU time 0.77 seconds
Started Feb 29 12:52:43 PM PST 24
Finished Feb 29 12:52:45 PM PST 24
Peak memory 196096 kb
Host smart-bda147dd-e3af-4d1e-b11b-7c49865cba12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023888121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3023888121
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.973141683
Short name T534
Test name
Test status
Simulation time 80456855 ps
CPU time 4.16 seconds
Started Feb 29 12:52:57 PM PST 24
Finished Feb 29 12:53:02 PM PST 24
Peak memory 195768 kb
Host smart-773cd5fd-4bd2-42de-b686-9d118ae3794e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973141683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.973141683
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.684135728
Short name T554
Test name
Test status
Simulation time 162795330 ps
CPU time 1.07 seconds
Started Feb 29 12:52:55 PM PST 24
Finished Feb 29 12:52:58 PM PST 24
Peak memory 196808 kb
Host smart-1605df97-f035-4ed1-bd3f-93a4d493dbee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684135728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.684135728
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2800303975
Short name T409
Test name
Test status
Simulation time 307473430 ps
CPU time 1.3 seconds
Started Feb 29 12:52:52 PM PST 24
Finished Feb 29 12:52:54 PM PST 24
Peak memory 197980 kb
Host smart-ed020dbe-8b19-457f-9283-cb25e6673297
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800303975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2800303975
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3405757624
Short name T690
Test name
Test status
Simulation time 47919274 ps
CPU time 1.86 seconds
Started Feb 29 12:52:38 PM PST 24
Finished Feb 29 12:52:40 PM PST 24
Peak memory 198152 kb
Host smart-5a360bf3-a8cb-48fe-ab40-4ed7362c48b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405757624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3405757624
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.651461624
Short name T441
Test name
Test status
Simulation time 152428922 ps
CPU time 3.07 seconds
Started Feb 29 12:52:54 PM PST 24
Finished Feb 29 12:52:58 PM PST 24
Peak memory 198076 kb
Host smart-ea766daf-2a8e-40ac-9250-b8a905d7b099
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651461624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.651461624
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3518627220
Short name T320
Test name
Test status
Simulation time 166708868 ps
CPU time 1.06 seconds
Started Feb 29 12:52:43 PM PST 24
Finished Feb 29 12:52:44 PM PST 24
Peak memory 195868 kb
Host smart-0680dc24-e510-4811-9d52-a66d67e97e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518627220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3518627220
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1175981212
Short name T194
Test name
Test status
Simulation time 41224825 ps
CPU time 0.86 seconds
Started Feb 29 12:52:49 PM PST 24
Finished Feb 29 12:52:50 PM PST 24
Peak memory 196076 kb
Host smart-660b4f83-7a36-477b-87b3-29997a7b178b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175981212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1175981212
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3565719963
Short name T217
Test name
Test status
Simulation time 173720844 ps
CPU time 4.06 seconds
Started Feb 29 12:52:43 PM PST 24
Finished Feb 29 12:52:47 PM PST 24
Peak memory 197728 kb
Host smart-d434fa3e-cc9b-4212-94c6-f72d0da7fd25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565719963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3565719963
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1896914399
Short name T45
Test name
Test status
Simulation time 129224813 ps
CPU time 0.78 seconds
Started Feb 29 12:52:45 PM PST 24
Finished Feb 29 12:52:47 PM PST 24
Peak memory 213692 kb
Host smart-08f25f51-3508-465c-8b3e-151e08217a8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896914399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1896914399
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1472494834
Short name T237
Test name
Test status
Simulation time 481345803 ps
CPU time 1.4 seconds
Started Feb 29 12:53:07 PM PST 24
Finished Feb 29 12:53:08 PM PST 24
Peak memory 198056 kb
Host smart-c39b18ed-f877-442b-986c-c80fed7ef268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472494834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1472494834
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3393503326
Short name T241
Test name
Test status
Simulation time 62787337 ps
CPU time 1.04 seconds
Started Feb 29 12:52:58 PM PST 24
Finished Feb 29 12:52:59 PM PST 24
Peak memory 195648 kb
Host smart-55a37aaa-3ad4-47af-bad6-f73402ecb57a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393503326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3393503326
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.225060370
Short name T428
Test name
Test status
Simulation time 7961958166 ps
CPU time 112.64 seconds
Started Feb 29 12:52:45 PM PST 24
Finished Feb 29 12:54:39 PM PST 24
Peak memory 198112 kb
Host smart-130fe08d-7a48-4097-b5e4-deb079620327
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225060370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.225060370
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.189213496
Short name T12
Test name
Test status
Simulation time 17121570 ps
CPU time 0.58 seconds
Started Feb 29 12:52:49 PM PST 24
Finished Feb 29 12:52:50 PM PST 24
Peak memory 193868 kb
Host smart-c0cd326f-943b-4682-bb95-050b9a43691e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189213496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.189213496
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3611754006
Short name T462
Test name
Test status
Simulation time 215012819 ps
CPU time 0.84 seconds
Started Feb 29 12:52:48 PM PST 24
Finished Feb 29 12:52:49 PM PST 24
Peak memory 196404 kb
Host smart-f5a6e0b8-a7d8-44bb-ae26-57bc0cc38ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611754006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3611754006
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.78420673
Short name T346
Test name
Test status
Simulation time 983893670 ps
CPU time 7.99 seconds
Started Feb 29 12:52:57 PM PST 24
Finished Feb 29 12:53:05 PM PST 24
Peak memory 196784 kb
Host smart-7cb9c2c8-a213-452a-86a1-ca9602fc0d2f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78420673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress.78420673
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3955839859
Short name T667
Test name
Test status
Simulation time 144610211 ps
CPU time 0.98 seconds
Started Feb 29 12:52:50 PM PST 24
Finished Feb 29 12:52:52 PM PST 24
Peak memory 196476 kb
Host smart-25eb5dfb-8184-4b9f-b5b3-fa4727edeb46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955839859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3955839859
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3582890397
Short name T116
Test name
Test status
Simulation time 169988096 ps
CPU time 0.91 seconds
Started Feb 29 12:52:47 PM PST 24
Finished Feb 29 12:52:48 PM PST 24
Peak memory 195856 kb
Host smart-30bd4a16-c980-4eb4-b277-cbff82965825
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582890397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3582890397
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3785827838
Short name T485
Test name
Test status
Simulation time 334317613 ps
CPU time 3.41 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 12:53:14 PM PST 24
Peak memory 198200 kb
Host smart-aa9cff05-fd8a-43f5-91d5-b2a47d05d90c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785827838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3785827838
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2830939067
Short name T516
Test name
Test status
Simulation time 324617095 ps
CPU time 2.43 seconds
Started Feb 29 12:52:54 PM PST 24
Finished Feb 29 12:53:01 PM PST 24
Peak memory 197052 kb
Host smart-825b4f64-f76d-4b06-88af-d7d8292f1025
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830939067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2830939067
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3738425085
Short name T386
Test name
Test status
Simulation time 113640497 ps
CPU time 1.08 seconds
Started Feb 29 12:52:58 PM PST 24
Finished Feb 29 12:53:00 PM PST 24
Peak memory 196012 kb
Host smart-bfb69b1f-cf0f-4812-8aed-7fe570740208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738425085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3738425085
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.311314412
Short name T699
Test name
Test status
Simulation time 97445082 ps
CPU time 0.84 seconds
Started Feb 29 12:52:49 PM PST 24
Finished Feb 29 12:52:50 PM PST 24
Peak memory 196648 kb
Host smart-7e6a8fc4-9fe6-449e-afd1-36317141517c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311314412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.311314412
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3186302484
Short name T206
Test name
Test status
Simulation time 536527514 ps
CPU time 6.01 seconds
Started Feb 29 12:52:45 PM PST 24
Finished Feb 29 12:52:52 PM PST 24
Peak memory 198072 kb
Host smart-3aa6a86f-28c2-428f-992f-e5f7f6b65c68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186302484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3186302484
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.2823351057
Short name T114
Test name
Test status
Simulation time 45599943 ps
CPU time 1.22 seconds
Started Feb 29 12:52:51 PM PST 24
Finished Feb 29 12:52:53 PM PST 24
Peak memory 196588 kb
Host smart-cc6e41d6-517d-4ee8-8cec-598be9cc194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823351057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2823351057
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.4108705824
Short name T422
Test name
Test status
Simulation time 58728301 ps
CPU time 1.11 seconds
Started Feb 29 12:52:53 PM PST 24
Finished Feb 29 12:52:55 PM PST 24
Peak memory 195820 kb
Host smart-31c74506-e28e-4a48-ae65-693fa189a332
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108705824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.4108705824
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.145320633
Short name T458
Test name
Test status
Simulation time 20175768195 ps
CPU time 136.28 seconds
Started Feb 29 12:52:51 PM PST 24
Finished Feb 29 12:55:08 PM PST 24
Peak memory 198160 kb
Host smart-768776bd-5304-4dec-86ca-6131e54b799a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145320633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.145320633
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.767181325
Short name T676
Test name
Test status
Simulation time 42557664 ps
CPU time 0.56 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:53:16 PM PST 24
Peak memory 193884 kb
Host smart-61f14edb-204a-4214-a66a-baff4287e468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767181325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.767181325
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2413011897
Short name T260
Test name
Test status
Simulation time 42760150 ps
CPU time 0.81 seconds
Started Feb 29 12:52:59 PM PST 24
Finished Feb 29 12:53:00 PM PST 24
Peak memory 195228 kb
Host smart-f07f65f5-a03a-4ccc-92ee-246aafe8b4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413011897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2413011897
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.25816389
Short name T399
Test name
Test status
Simulation time 157794335 ps
CPU time 4.51 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:20 PM PST 24
Peak memory 195812 kb
Host smart-a395d22b-b49c-4378-920c-923ca7af38fe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25816389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stress
.25816389
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2195519483
Short name T494
Test name
Test status
Simulation time 96626541 ps
CPU time 1.13 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:20 PM PST 24
Peak memory 198132 kb
Host smart-34c98845-ac20-4033-8d5a-069bd81a2db1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195519483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2195519483
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3098069236
Short name T176
Test name
Test status
Simulation time 295225176 ps
CPU time 1.36 seconds
Started Feb 29 12:53:19 PM PST 24
Finished Feb 29 12:53:20 PM PST 24
Peak memory 197244 kb
Host smart-fe223705-b5e5-4e4f-89ee-9b4319ef3948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098069236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3098069236
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.958439480
Short name T352
Test name
Test status
Simulation time 130068042 ps
CPU time 0.98 seconds
Started Feb 29 12:53:14 PM PST 24
Finished Feb 29 12:53:15 PM PST 24
Peak memory 195984 kb
Host smart-1fbde998-1919-4ef1-aa80-1eaff03a23a3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958439480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.958439480
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1889430353
Short name T118
Test name
Test status
Simulation time 94558638 ps
CPU time 2.59 seconds
Started Feb 29 12:53:19 PM PST 24
Finished Feb 29 12:53:23 PM PST 24
Peak memory 198100 kb
Host smart-69cbf549-cf4e-4958-80d2-dd3b2ddd60f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889430353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1889430353
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2639551540
Short name T286
Test name
Test status
Simulation time 36569725 ps
CPU time 0.93 seconds
Started Feb 29 12:53:09 PM PST 24
Finished Feb 29 12:53:10 PM PST 24
Peak memory 195936 kb
Host smart-c490ab6e-1140-495e-b6cc-4c869de96786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639551540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2639551540
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2780142750
Short name T226
Test name
Test status
Simulation time 47187786 ps
CPU time 0.59 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 12:53:12 PM PST 24
Peak memory 194120 kb
Host smart-d4264939-3153-45e6-a63d-9e52223201a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780142750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2780142750
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2391876515
Short name T115
Test name
Test status
Simulation time 399809938 ps
CPU time 3.88 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 198036 kb
Host smart-ea336fc1-6442-4f62-a81c-e00764234583
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391876515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2391876515
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1988167842
Short name T540
Test name
Test status
Simulation time 99087123 ps
CPU time 0.94 seconds
Started Feb 29 12:53:13 PM PST 24
Finished Feb 29 12:53:14 PM PST 24
Peak memory 196628 kb
Host smart-94e90bc2-bbe5-48c9-af26-8808cdceaf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988167842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1988167842
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3046541973
Short name T445
Test name
Test status
Simulation time 270056973 ps
CPU time 1.18 seconds
Started Feb 29 12:53:08 PM PST 24
Finished Feb 29 12:53:10 PM PST 24
Peak memory 196648 kb
Host smart-915076f2-d6d3-469d-934c-275586cec2f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046541973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3046541973
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2364036640
Short name T315
Test name
Test status
Simulation time 5119663314 ps
CPU time 63.6 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:54:20 PM PST 24
Peak memory 198264 kb
Host smart-a7d4479f-e198-4949-83ea-c79927f0de28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364036640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2364036640
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.329786367
Short name T58
Test name
Test status
Simulation time 18442441121 ps
CPU time 591.35 seconds
Started Feb 29 12:53:19 PM PST 24
Finished Feb 29 01:03:11 PM PST 24
Peak memory 198316 kb
Host smart-8466069f-ce10-41cc-aca1-864935919bf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=329786367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.329786367
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1843351816
Short name T149
Test name
Test status
Simulation time 13071993 ps
CPU time 0.57 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:19 PM PST 24
Peak memory 194632 kb
Host smart-a362d4a5-6fda-4a9a-87f2-7e1c2f2c6161
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843351816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1843351816
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.902827308
Short name T157
Test name
Test status
Simulation time 40377697 ps
CPU time 0.73 seconds
Started Feb 29 12:53:05 PM PST 24
Finished Feb 29 12:53:06 PM PST 24
Peak memory 195992 kb
Host smart-a8fb2b2a-112a-480c-8496-a08de55083ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902827308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.902827308
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1249212551
Short name T372
Test name
Test status
Simulation time 182532323 ps
CPU time 9.27 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:30 PM PST 24
Peak memory 197032 kb
Host smart-bdb789f5-d359-4199-b4ac-8f16340765e1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249212551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1249212551
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2199803864
Short name T639
Test name
Test status
Simulation time 498900762 ps
CPU time 0.72 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:17 PM PST 24
Peak memory 194556 kb
Host smart-bdc6601b-253f-4641-8a40-b16e7f54541d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199803864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2199803864
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.623448947
Short name T418
Test name
Test status
Simulation time 101476377 ps
CPU time 1.37 seconds
Started Feb 29 12:53:13 PM PST 24
Finished Feb 29 12:53:15 PM PST 24
Peak memory 197148 kb
Host smart-02977354-bf8d-4f8f-876e-90dd995a0703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623448947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.623448947
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3665522914
Short name T183
Test name
Test status
Simulation time 517823098 ps
CPU time 1.17 seconds
Started Feb 29 12:53:19 PM PST 24
Finished Feb 29 12:53:21 PM PST 24
Peak memory 196876 kb
Host smart-94c9489d-1dba-4724-b57f-3c83732d499a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665522914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3665522914
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3632517850
Short name T64
Test name
Test status
Simulation time 111373287 ps
CPU time 2.35 seconds
Started Feb 29 12:53:13 PM PST 24
Finished Feb 29 12:53:16 PM PST 24
Peak memory 198144 kb
Host smart-a9e992e7-a599-49ab-ba3f-27eb615bebd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632517850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3632517850
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2716094957
Short name T168
Test name
Test status
Simulation time 176226208 ps
CPU time 1.14 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:19 PM PST 24
Peak memory 195948 kb
Host smart-885643dd-d605-4998-be51-37eaf7000a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716094957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2716094957
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.12798325
Short name T222
Test name
Test status
Simulation time 145981710 ps
CPU time 1.11 seconds
Started Feb 29 12:53:12 PM PST 24
Finished Feb 29 12:53:13 PM PST 24
Peak memory 196560 kb
Host smart-9201d885-c0a0-42a3-9c5a-f02f74238f18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12798325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup_
pulldown.12798325
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1610287475
Short name T298
Test name
Test status
Simulation time 53134258 ps
CPU time 2.25 seconds
Started Feb 29 12:53:14 PM PST 24
Finished Feb 29 12:53:16 PM PST 24
Peak memory 198052 kb
Host smart-3ea95c13-31a5-49b4-9803-aa9e27e78ea2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610287475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1610287475
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2475826180
Short name T133
Test name
Test status
Simulation time 38994348 ps
CPU time 0.82 seconds
Started Feb 29 12:53:17 PM PST 24
Finished Feb 29 12:53:18 PM PST 24
Peak memory 196084 kb
Host smart-6c1492cf-0f98-4e15-97d8-11e9f197812b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475826180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2475826180
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.610372422
Short name T521
Test name
Test status
Simulation time 54991207 ps
CPU time 1.19 seconds
Started Feb 29 12:53:14 PM PST 24
Finished Feb 29 12:53:15 PM PST 24
Peak memory 196448 kb
Host smart-089010e5-ef46-4836-83df-85107b077ddc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610372422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.610372422
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1159815157
Short name T606
Test name
Test status
Simulation time 8968088948 ps
CPU time 95.05 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:54:50 PM PST 24
Peak memory 198108 kb
Host smart-913522ee-d4d6-4110-ae02-047eda1515f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159815157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1159815157
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1570207419
Short name T50
Test name
Test status
Simulation time 168200938 ps
CPU time 0.58 seconds
Started Feb 29 12:53:17 PM PST 24
Finished Feb 29 12:53:18 PM PST 24
Peak memory 193968 kb
Host smart-f91ff664-a523-4fd6-990f-70909175c8a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570207419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1570207419
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.17160103
Short name T669
Test name
Test status
Simulation time 19782149 ps
CPU time 0.67 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:19 PM PST 24
Peak memory 194028 kb
Host smart-4743e02a-1286-4df4-812d-39c8bef2ede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17160103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.17160103
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2857722404
Short name T165
Test name
Test status
Simulation time 511008073 ps
CPU time 26.14 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:53:41 PM PST 24
Peak memory 197040 kb
Host smart-84ceffff-6126-4754-acc1-2c63b81bbc44
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857722404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2857722404
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1646782622
Short name T677
Test name
Test status
Simulation time 93683459 ps
CPU time 0.7 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:53:16 PM PST 24
Peak memory 195392 kb
Host smart-2286df78-1b1e-45fe-8e5d-edb6925c761f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646782622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1646782622
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1710232363
Short name T505
Test name
Test status
Simulation time 483587680 ps
CPU time 1.23 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:17 PM PST 24
Peak memory 196756 kb
Host smart-66bbdeb4-d8da-4444-8736-0e55d12e0706
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710232363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1710232363
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2411999088
Short name T665
Test name
Test status
Simulation time 1269796866 ps
CPU time 3.49 seconds
Started Feb 29 12:53:21 PM PST 24
Finished Feb 29 12:53:26 PM PST 24
Peak memory 198160 kb
Host smart-adffa98e-5b49-43b8-8e3f-d5907703c0a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411999088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2411999088
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1609815433
Short name T401
Test name
Test status
Simulation time 119175481 ps
CPU time 0.89 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 12:53:12 PM PST 24
Peak memory 196108 kb
Host smart-c531af8b-a568-409e-a335-45f8ac30d692
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609815433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1609815433
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3051829935
Short name T136
Test name
Test status
Simulation time 97112481 ps
CPU time 0.66 seconds
Started Feb 29 12:53:21 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 194284 kb
Host smart-f8adb3cd-df23-4657-b607-1e272533eb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051829935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3051829935
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.601972891
Short name T124
Test name
Test status
Simulation time 137163873 ps
CPU time 0.92 seconds
Started Feb 29 12:53:19 PM PST 24
Finished Feb 29 12:53:21 PM PST 24
Peak memory 196076 kb
Host smart-bf9d83f4-e949-42df-b8de-12aa3c01a74b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601972891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.601972891
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2357871981
Short name T582
Test name
Test status
Simulation time 30733131 ps
CPU time 1.38 seconds
Started Feb 29 12:53:14 PM PST 24
Finished Feb 29 12:53:16 PM PST 24
Peak memory 198012 kb
Host smart-c3b878fb-c864-4a1b-a83d-104618c92718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357871981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2357871981
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1023409747
Short name T283
Test name
Test status
Simulation time 52923098 ps
CPU time 1.06 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:17 PM PST 24
Peak memory 196480 kb
Host smart-e27ccd27-f949-4da3-8dba-8282250ba494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023409747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1023409747
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.232359047
Short name T621
Test name
Test status
Simulation time 85278448 ps
CPU time 1.48 seconds
Started Feb 29 12:53:10 PM PST 24
Finished Feb 29 12:53:12 PM PST 24
Peak memory 196912 kb
Host smart-cf40af29-baf1-48cf-9b96-edf660a87975
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232359047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.232359047
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3954197259
Short name T531
Test name
Test status
Simulation time 7442826625 ps
CPU time 103.51 seconds
Started Feb 29 12:53:19 PM PST 24
Finished Feb 29 12:55:03 PM PST 24
Peak memory 198172 kb
Host smart-6e790f81-157f-4fb1-b4be-20cc058ba215
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954197259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3954197259
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.4172629284
Short name T370
Test name
Test status
Simulation time 146680500791 ps
CPU time 2926.06 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 01:41:57 PM PST 24
Peak memory 198316 kb
Host smart-b838a2dc-efdf-4a84-a99a-8761f5726bb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4172629284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.4172629284
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3006666831
Short name T316
Test name
Test status
Simulation time 47890196 ps
CPU time 0.66 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 194116 kb
Host smart-111b6de5-908b-48b1-aee9-d1c0911305a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006666831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3006666831
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2074201102
Short name T545
Test name
Test status
Simulation time 189670722 ps
CPU time 0.94 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:17 PM PST 24
Peak memory 196500 kb
Host smart-9111895a-759e-4da6-816f-bf609a1f7b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074201102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2074201102
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.4199351340
Short name T119
Test name
Test status
Simulation time 6644626141 ps
CPU time 12.9 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:32 PM PST 24
Peak memory 196604 kb
Host smart-849970c2-bef5-4ced-a63c-e33c574d32df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199351340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.4199351340
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.300396880
Short name T21
Test name
Test status
Simulation time 132571015 ps
CPU time 0.98 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:17 PM PST 24
Peak memory 197744 kb
Host smart-e5468e28-5957-4928-9883-83708a91afe1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300396880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.300396880
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2065611559
Short name T411
Test name
Test status
Simulation time 410166809 ps
CPU time 1.42 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:18 PM PST 24
Peak memory 197084 kb
Host smart-151e5b61-0a6c-4f51-a392-a7e36955e3cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065611559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2065611559
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1301399788
Short name T388
Test name
Test status
Simulation time 98835147 ps
CPU time 1.93 seconds
Started Feb 29 12:53:28 PM PST 24
Finished Feb 29 12:53:30 PM PST 24
Peak memory 198136 kb
Host smart-5ff7d935-64b0-4b6f-af37-562a47c90af9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301399788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1301399788
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2256692194
Short name T410
Test name
Test status
Simulation time 128848846 ps
CPU time 1.62 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:18 PM PST 24
Peak memory 196128 kb
Host smart-3e9e7210-6dc4-416f-81ec-3ced8921b787
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256692194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2256692194
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2515756225
Short name T160
Test name
Test status
Simulation time 66561483 ps
CPU time 0.64 seconds
Started Feb 29 12:53:19 PM PST 24
Finished Feb 29 12:53:20 PM PST 24
Peak memory 194196 kb
Host smart-3c5f6018-ee90-440d-b482-9bcf8b178aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515756225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2515756225
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3469968400
Short name T207
Test name
Test status
Simulation time 39494075 ps
CPU time 0.7 seconds
Started Feb 29 12:53:17 PM PST 24
Finished Feb 29 12:53:18 PM PST 24
Peak memory 194324 kb
Host smart-625d860e-a84d-4fb4-8001-d0809bbd6cb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469968400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3469968400
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1657243732
Short name T580
Test name
Test status
Simulation time 68009800 ps
CPU time 3.08 seconds
Started Feb 29 12:53:13 PM PST 24
Finished Feb 29 12:53:16 PM PST 24
Peak memory 198016 kb
Host smart-686d8023-9113-4282-bbb3-f07f96c4879e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657243732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1657243732
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.932378108
Short name T430
Test name
Test status
Simulation time 71371749 ps
CPU time 1.14 seconds
Started Feb 29 12:53:25 PM PST 24
Finished Feb 29 12:53:27 PM PST 24
Peak memory 195816 kb
Host smart-c5edae43-73e0-4d81-9b52-5b9a7f29f9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932378108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.932378108
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1403751957
Short name T616
Test name
Test status
Simulation time 56116101 ps
CPU time 0.73 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 194936 kb
Host smart-803c74ff-ad17-4baa-b23d-d8ee800d509d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403751957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1403751957
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2575534974
Short name T44
Test name
Test status
Simulation time 2650517634 ps
CPU time 67.83 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 12:54:19 PM PST 24
Peak memory 198188 kb
Host smart-6581ef66-6a01-4fc9-86b4-c77e4934d38a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575534974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2575534974
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.2347803423
Short name T695
Test name
Test status
Simulation time 162998325121 ps
CPU time 1563.19 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 01:19:19 PM PST 24
Peak memory 198340 kb
Host smart-ac1e826e-f6d1-4c1f-adb9-9c402820a189
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2347803423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.2347803423
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1356739873
Short name T515
Test name
Test status
Simulation time 14873303 ps
CPU time 0.55 seconds
Started Feb 29 12:53:26 PM PST 24
Finished Feb 29 12:53:27 PM PST 24
Peak memory 194096 kb
Host smart-28a66119-fa19-4cdf-a6ba-b1128087eefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356739873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1356739873
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2433114582
Short name T493
Test name
Test status
Simulation time 146166696 ps
CPU time 0.9 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:21 PM PST 24
Peak memory 196252 kb
Host smart-531d44a4-9410-40bd-aba2-5eedd95472d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433114582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2433114582
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1489148898
Short name T342
Test name
Test status
Simulation time 1663523972 ps
CPU time 10.45 seconds
Started Feb 29 12:53:38 PM PST 24
Finished Feb 29 12:53:49 PM PST 24
Peak memory 198040 kb
Host smart-e7598f25-ea6a-4467-8d5c-6de4b7478903
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489148898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1489148898
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1272920792
Short name T501
Test name
Test status
Simulation time 61897610 ps
CPU time 0.8 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:20 PM PST 24
Peak memory 195808 kb
Host smart-0dc27919-4db6-488e-bc01-156993fc87a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272920792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1272920792
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.4040944920
Short name T254
Test name
Test status
Simulation time 150929468 ps
CPU time 1.12 seconds
Started Feb 29 12:53:23 PM PST 24
Finished Feb 29 12:53:25 PM PST 24
Peak memory 196024 kb
Host smart-da72185e-f92b-43cd-b211-9a0f93ca1a27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040944920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.4040944920
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2416969776
Short name T553
Test name
Test status
Simulation time 51493448 ps
CPU time 2.03 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:23 PM PST 24
Peak memory 198096 kb
Host smart-ce41656f-b24f-404d-b531-7d107209ce8f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416969776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2416969776
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2511783745
Short name T351
Test name
Test status
Simulation time 50543729 ps
CPU time 0.86 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 194448 kb
Host smart-bfaf7729-98da-41c8-bd77-ee2c19921c97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511783745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2511783745
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1329766973
Short name T584
Test name
Test status
Simulation time 30300286 ps
CPU time 1.09 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:18 PM PST 24
Peak memory 196908 kb
Host smart-8351a6cf-fc4e-4efb-bcf6-9de09c11dc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329766973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1329766973
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.142153431
Short name T48
Test name
Test status
Simulation time 210675959 ps
CPU time 1.17 seconds
Started Feb 29 12:53:14 PM PST 24
Finished Feb 29 12:53:16 PM PST 24
Peak memory 197196 kb
Host smart-057fd692-bcbd-4e1e-8f0c-0a6a47e3cc35
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142153431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.142153431
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3479988219
Short name T592
Test name
Test status
Simulation time 82695600 ps
CPU time 3.72 seconds
Started Feb 29 12:53:38 PM PST 24
Finished Feb 29 12:53:42 PM PST 24
Peak memory 198024 kb
Host smart-1a72434e-fd2a-4b5b-a112-f0ea985de6a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479988219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3479988219
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3174860306
Short name T692
Test name
Test status
Simulation time 37765354 ps
CPU time 1.15 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:19 PM PST 24
Peak memory 196208 kb
Host smart-b04b8d9d-de0b-4a1c-8466-eb06de8b5257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174860306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3174860306
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2329725608
Short name T132
Test name
Test status
Simulation time 29738655 ps
CPU time 0.97 seconds
Started Feb 29 12:53:17 PM PST 24
Finished Feb 29 12:53:18 PM PST 24
Peak memory 195588 kb
Host smart-14e4a1be-5f87-4acc-ade3-21f550178fe1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329725608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2329725608
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.16432224
Short name T644
Test name
Test status
Simulation time 6187580464 ps
CPU time 103.03 seconds
Started Feb 29 12:53:35 PM PST 24
Finished Feb 29 12:55:18 PM PST 24
Peak memory 198172 kb
Host smart-b1b10433-5e0b-48de-911c-b2812be34f68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16432224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gp
io_stress_all.16432224
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1347898103
Short name T36
Test name
Test status
Simulation time 45658337 ps
CPU time 0.55 seconds
Started Feb 29 12:53:27 PM PST 24
Finished Feb 29 12:53:28 PM PST 24
Peak memory 193844 kb
Host smart-f82f189b-9365-4ba3-9231-4f48b99e6969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347898103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1347898103
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3394619804
Short name T311
Test name
Test status
Simulation time 98433852 ps
CPU time 0.97 seconds
Started Feb 29 12:53:14 PM PST 24
Finished Feb 29 12:53:15 PM PST 24
Peak memory 196556 kb
Host smart-ca8db008-97e6-466e-b158-5dcf2c220b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394619804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3394619804
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2223255236
Short name T424
Test name
Test status
Simulation time 161487163 ps
CPU time 7.58 seconds
Started Feb 29 12:53:23 PM PST 24
Finished Feb 29 12:53:31 PM PST 24
Peak memory 197024 kb
Host smart-4cfa9abb-5553-417d-9dc6-89e3fded8f09
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223255236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2223255236
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1120060579
Short name T568
Test name
Test status
Simulation time 83276785 ps
CPU time 0.72 seconds
Started Feb 29 12:53:21 PM PST 24
Finished Feb 29 12:53:23 PM PST 24
Peak memory 194956 kb
Host smart-bd5f6b7e-f0c1-429b-8efa-425234707f13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120060579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1120060579
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3665063301
Short name T261
Test name
Test status
Simulation time 129155819 ps
CPU time 0.8 seconds
Started Feb 29 12:53:21 PM PST 24
Finished Feb 29 12:53:23 PM PST 24
Peak memory 195792 kb
Host smart-db759f8b-8cd9-4d8c-9bdf-32687a9629ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665063301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3665063301
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.49014530
Short name T652
Test name
Test status
Simulation time 68153509 ps
CPU time 2.09 seconds
Started Feb 29 12:53:22 PM PST 24
Finished Feb 29 12:53:25 PM PST 24
Peak memory 198280 kb
Host smart-b34f2742-d99f-4f7c-8e98-7f073ca87c23
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49014530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.gpio_intr_with_filter_rand_intr_event.49014530
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.4073465924
Short name T338
Test name
Test status
Simulation time 68055941 ps
CPU time 2.09 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:18 PM PST 24
Peak memory 195880 kb
Host smart-41fc6517-551d-4d5d-b69b-6a1b464d60de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073465924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.4073465924
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2818141453
Short name T52
Test name
Test status
Simulation time 297406879 ps
CPU time 1.43 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 197024 kb
Host smart-f17246a2-b54c-4491-903e-4fa62a19e93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818141453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2818141453
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2799682957
Short name T380
Test name
Test status
Simulation time 39485916 ps
CPU time 0.95 seconds
Started Feb 29 12:53:22 PM PST 24
Finished Feb 29 12:53:24 PM PST 24
Peak memory 196780 kb
Host smart-881ba619-e57b-4a5b-9c6b-e57f57f778d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799682957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2799682957
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2360606488
Short name T180
Test name
Test status
Simulation time 85362760 ps
CPU time 3.8 seconds
Started Feb 29 12:53:23 PM PST 24
Finished Feb 29 12:53:27 PM PST 24
Peak memory 198044 kb
Host smart-1622d176-90a9-4de6-95fc-b4ba7f9f5708
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360606488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2360606488
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3426388235
Short name T287
Test name
Test status
Simulation time 91361596 ps
CPU time 1.41 seconds
Started Feb 29 12:53:14 PM PST 24
Finished Feb 29 12:53:16 PM PST 24
Peak memory 198084 kb
Host smart-318f431c-044c-4cdd-be8e-816373e122b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426388235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3426388235
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1798899824
Short name T161
Test name
Test status
Simulation time 77120851 ps
CPU time 1.22 seconds
Started Feb 29 12:53:52 PM PST 24
Finished Feb 29 12:53:53 PM PST 24
Peak memory 195724 kb
Host smart-48b1bdbc-3dbb-4d06-8f06-d3fd8a23cf98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798899824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1798899824
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1428129433
Short name T618
Test name
Test status
Simulation time 53608339631 ps
CPU time 165.76 seconds
Started Feb 29 12:53:42 PM PST 24
Finished Feb 29 12:56:28 PM PST 24
Peak memory 198188 kb
Host smart-6358de80-fcdd-4810-a45d-a6588c6fe130
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428129433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1428129433
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.1445514977
Short name T662
Test name
Test status
Simulation time 146080117157 ps
CPU time 1663.26 seconds
Started Feb 29 12:53:17 PM PST 24
Finished Feb 29 01:21:01 PM PST 24
Peak memory 198232 kb
Host smart-98df8233-72f1-4ad2-a57f-b22bf365abec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1445514977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.1445514977
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3717377910
Short name T129
Test name
Test status
Simulation time 14687604 ps
CPU time 0.56 seconds
Started Feb 29 12:53:30 PM PST 24
Finished Feb 29 12:53:30 PM PST 24
Peak memory 194100 kb
Host smart-f402bb58-2b3e-44c5-9b44-e4107cdf9da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717377910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3717377910
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3175356165
Short name T198
Test name
Test status
Simulation time 94788402 ps
CPU time 0.94 seconds
Started Feb 29 12:53:25 PM PST 24
Finished Feb 29 12:53:27 PM PST 24
Peak memory 196560 kb
Host smart-a8456988-f5f6-44a8-a10b-c0d0da395582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175356165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3175356165
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.485757944
Short name T520
Test name
Test status
Simulation time 153941243 ps
CPU time 7.5 seconds
Started Feb 29 12:53:19 PM PST 24
Finished Feb 29 12:53:27 PM PST 24
Peak memory 196628 kb
Host smart-80639636-081b-4db7-b5fa-e368f8b4cf2e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485757944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.485757944
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.609692978
Short name T238
Test name
Test status
Simulation time 303309144 ps
CPU time 1.05 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 197944 kb
Host smart-0f8cbbca-cc59-4a00-be27-47a17d740cba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609692978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.609692978
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1973060296
Short name T664
Test name
Test status
Simulation time 53106058 ps
CPU time 0.75 seconds
Started Feb 29 12:53:30 PM PST 24
Finished Feb 29 12:53:31 PM PST 24
Peak memory 196088 kb
Host smart-852ed4d1-8c63-4dfb-884a-fa71e2c309d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973060296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1973060296
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2856054394
Short name T679
Test name
Test status
Simulation time 29065649 ps
CPU time 1.08 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:20 PM PST 24
Peak memory 196132 kb
Host smart-56dbb388-5683-4717-9930-936314491678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856054394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2856054394
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.925494676
Short name T643
Test name
Test status
Simulation time 43346874 ps
CPU time 0.91 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:17 PM PST 24
Peak memory 196780 kb
Host smart-6e1ad1a2-cc11-4754-9c8b-2a5cd79dd362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925494676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.925494676
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3933453268
Short name T181
Test name
Test status
Simulation time 142425194 ps
CPU time 1.32 seconds
Started Feb 29 12:53:49 PM PST 24
Finished Feb 29 12:53:51 PM PST 24
Peak memory 195928 kb
Host smart-b69951c6-36a8-4c7e-aad3-e3bf93a26e84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933453268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3933453268
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1650760050
Short name T455
Test name
Test status
Simulation time 318497686 ps
CPU time 3.66 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 198044 kb
Host smart-21b56e3f-e72e-4cfe-a40c-2210224c338e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650760050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1650760050
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2569213788
Short name T289
Test name
Test status
Simulation time 85079120 ps
CPU time 1.39 seconds
Started Feb 29 12:53:44 PM PST 24
Finished Feb 29 12:53:46 PM PST 24
Peak memory 196916 kb
Host smart-2b3bc959-d3a5-4555-a673-0d13ab4522f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569213788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2569213788
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.4158995064
Short name T562
Test name
Test status
Simulation time 37705911 ps
CPU time 1.06 seconds
Started Feb 29 12:53:41 PM PST 24
Finished Feb 29 12:53:43 PM PST 24
Peak memory 195804 kb
Host smart-f334f8f5-fd9d-44d3-aa63-82bdbc07df3d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158995064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.4158995064
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3033245077
Short name T533
Test name
Test status
Simulation time 15569919416 ps
CPU time 58.95 seconds
Started Feb 29 12:53:19 PM PST 24
Finished Feb 29 12:54:19 PM PST 24
Peak memory 198248 kb
Host smart-489774a5-651a-41fd-8c3a-6851d66abfd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033245077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3033245077
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.3898251309
Short name T59
Test name
Test status
Simulation time 653024341336 ps
CPU time 2858.64 seconds
Started Feb 29 12:53:26 PM PST 24
Finished Feb 29 01:41:05 PM PST 24
Peak memory 198312 kb
Host smart-12dedace-25d5-449f-b8ed-5e00184b50ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3898251309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.3898251309
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1364607190
Short name T443
Test name
Test status
Simulation time 26623177 ps
CPU time 0.57 seconds
Started Feb 29 12:53:22 PM PST 24
Finished Feb 29 12:53:23 PM PST 24
Peak memory 194044 kb
Host smart-e8520cb5-d49a-4f98-b615-73aa47da6fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364607190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1364607190
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2160809676
Short name T619
Test name
Test status
Simulation time 20470971 ps
CPU time 0.62 seconds
Started Feb 29 12:53:26 PM PST 24
Finished Feb 29 12:53:26 PM PST 24
Peak memory 194032 kb
Host smart-24e30b3b-cd61-426c-af33-f2066c8e4eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160809676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2160809676
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3861664092
Short name T523
Test name
Test status
Simulation time 1060931568 ps
CPU time 21.25 seconds
Started Feb 29 12:53:49 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 196872 kb
Host smart-93cd3b7d-f685-4c04-b46a-c23f98b115d6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861664092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3861664092
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3660415635
Short name T696
Test name
Test status
Simulation time 20953466 ps
CPU time 0.63 seconds
Started Feb 29 12:53:39 PM PST 24
Finished Feb 29 12:53:40 PM PST 24
Peak memory 195332 kb
Host smart-31f28b31-5ae5-4ee9-b379-6c918b68d383
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660415635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3660415635
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1967488707
Short name T714
Test name
Test status
Simulation time 513595514 ps
CPU time 1.35 seconds
Started Feb 29 12:53:22 PM PST 24
Finished Feb 29 12:53:24 PM PST 24
Peak memory 197204 kb
Host smart-9dcf9b69-0790-4d7f-bde9-6e1f8f3dd465
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967488707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1967488707
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1371267490
Short name T334
Test name
Test status
Simulation time 79332691 ps
CPU time 1.05 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 196752 kb
Host smart-b35553ba-e917-48aa-8b7d-262305130ba0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371267490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1371267490
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1421433403
Short name T253
Test name
Test status
Simulation time 429472959 ps
CPU time 2.28 seconds
Started Feb 29 12:53:46 PM PST 24
Finished Feb 29 12:53:49 PM PST 24
Peak memory 198148 kb
Host smart-188e91b1-8627-411a-9c95-32a938cb6bb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421433403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1421433403
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3021619503
Short name T313
Test name
Test status
Simulation time 186712727 ps
CPU time 1.07 seconds
Started Feb 29 12:53:21 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 196048 kb
Host smart-60c55aff-ea80-43f1-9029-c7e183ea66ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021619503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3021619503
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.517784703
Short name T549
Test name
Test status
Simulation time 57257466 ps
CPU time 1.17 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:20 PM PST 24
Peak memory 196744 kb
Host smart-2c1ca83b-f309-4c8f-a296-4b3bf11ee1e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517784703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.517784703
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1248333087
Short name T513
Test name
Test status
Simulation time 97942805 ps
CPU time 1.2 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:17 PM PST 24
Peak memory 198040 kb
Host smart-3457f9d2-9d4c-4d0a-8bbd-b356021a07fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248333087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1248333087
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.689813977
Short name T615
Test name
Test status
Simulation time 43530499 ps
CPU time 1.14 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:20 PM PST 24
Peak memory 196472 kb
Host smart-3d6edcd3-3b50-4c3c-b750-dfd115ea9168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689813977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.689813977
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1382694025
Short name T243
Test name
Test status
Simulation time 228018824 ps
CPU time 1.04 seconds
Started Feb 29 12:53:19 PM PST 24
Finished Feb 29 12:53:21 PM PST 24
Peak memory 196464 kb
Host smart-2ac49da7-8654-44b1-8f59-7488cdbd903e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382694025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1382694025
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2064229459
Short name T563
Test name
Test status
Simulation time 8701643381 ps
CPU time 123.73 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:55:20 PM PST 24
Peak memory 198168 kb
Host smart-dbf3958e-6fd8-4ba9-9d85-d968bd4aa8b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064229459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2064229459
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1994622087
Short name T512
Test name
Test status
Simulation time 287827516824 ps
CPU time 1496.09 seconds
Started Feb 29 12:53:27 PM PST 24
Finished Feb 29 01:18:23 PM PST 24
Peak memory 198520 kb
Host smart-b2daa3d6-6a3f-4193-9208-a38915b4d5ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1994622087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1994622087
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3303868763
Short name T588
Test name
Test status
Simulation time 14068808 ps
CPU time 0.58 seconds
Started Feb 29 12:53:22 PM PST 24
Finished Feb 29 12:53:23 PM PST 24
Peak memory 193880 kb
Host smart-e3ab3727-a46e-4e25-b2ab-ecb17c5fa4a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303868763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3303868763
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1544579463
Short name T13
Test name
Test status
Simulation time 30590860 ps
CPU time 0.65 seconds
Started Feb 29 12:53:42 PM PST 24
Finished Feb 29 12:53:42 PM PST 24
Peak memory 194672 kb
Host smart-5ac30bc7-03e2-4d86-91c9-906423dcb2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544579463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1544579463
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1980323637
Short name T273
Test name
Test status
Simulation time 469927049 ps
CPU time 24.94 seconds
Started Feb 29 12:53:39 PM PST 24
Finished Feb 29 12:54:04 PM PST 24
Peak memory 197020 kb
Host smart-319487da-78fe-4fc5-a017-5376294a565b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980323637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1980323637
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2263523890
Short name T472
Test name
Test status
Simulation time 52641903 ps
CPU time 0.79 seconds
Started Feb 29 12:53:34 PM PST 24
Finished Feb 29 12:53:34 PM PST 24
Peak memory 196028 kb
Host smart-d9b75c68-2321-475c-8c55-c2a0d05c7c38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263523890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2263523890
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.330399288
Short name T571
Test name
Test status
Simulation time 71567600 ps
CPU time 0.71 seconds
Started Feb 29 12:53:34 PM PST 24
Finished Feb 29 12:53:35 PM PST 24
Peak memory 194452 kb
Host smart-f6e3cc0e-8b37-4e34-8b16-697e496055bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330399288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.330399288
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2098668879
Short name T308
Test name
Test status
Simulation time 42253197 ps
CPU time 1.25 seconds
Started Feb 29 12:53:19 PM PST 24
Finished Feb 29 12:53:20 PM PST 24
Peak memory 196840 kb
Host smart-6dae0df3-7a37-4a99-ab38-409062241baa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098668879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2098668879
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2487504395
Short name T673
Test name
Test status
Simulation time 163876768 ps
CPU time 1.22 seconds
Started Feb 29 12:53:41 PM PST 24
Finished Feb 29 12:53:43 PM PST 24
Peak memory 196628 kb
Host smart-04cafcd9-43d0-4df0-ad85-d90fea57a441
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487504395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2487504395
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2984911854
Short name T378
Test name
Test status
Simulation time 54548972 ps
CPU time 0.69 seconds
Started Feb 29 12:53:46 PM PST 24
Finished Feb 29 12:53:47 PM PST 24
Peak memory 194512 kb
Host smart-d4db48e9-77a0-4fa0-b709-06c57efbe240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984911854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2984911854
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1616429145
Short name T109
Test name
Test status
Simulation time 61852632 ps
CPU time 0.86 seconds
Started Feb 29 12:53:41 PM PST 24
Finished Feb 29 12:53:42 PM PST 24
Peak memory 196464 kb
Host smart-1717ad7f-39c5-4581-a526-c588797d1a8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616429145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1616429145
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1047570846
Short name T573
Test name
Test status
Simulation time 63716779 ps
CPU time 1.37 seconds
Started Feb 29 12:53:51 PM PST 24
Finished Feb 29 12:53:53 PM PST 24
Peak memory 197968 kb
Host smart-445f2bda-ce53-49c7-b641-767d906cba22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047570846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1047570846
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.83275954
Short name T178
Test name
Test status
Simulation time 110389043 ps
CPU time 1.15 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 196520 kb
Host smart-fc7eebec-ac0a-4869-acf2-e916f436b5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83275954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.83275954
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2433182175
Short name T387
Test name
Test status
Simulation time 213959595 ps
CPU time 1.06 seconds
Started Feb 29 12:53:17 PM PST 24
Finished Feb 29 12:53:18 PM PST 24
Peak memory 195512 kb
Host smart-04c7197b-e9b3-4320-af21-f0809e9c4fe2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433182175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2433182175
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2079093259
Short name T71
Test name
Test status
Simulation time 2848110690 ps
CPU time 38.85 seconds
Started Feb 29 12:53:32 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 198200 kb
Host smart-3671db24-b4ff-4fc2-ad34-a503974941ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079093259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2079093259
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2475953059
Short name T337
Test name
Test status
Simulation time 10066167 ps
CPU time 0.56 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 193788 kb
Host smart-0b3dc9ba-bed9-4ffd-bf94-bbf65b0479cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475953059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2475953059
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.4226242319
Short name T179
Test name
Test status
Simulation time 50847045 ps
CPU time 0.99 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:17 PM PST 24
Peak memory 195776 kb
Host smart-5a91f1bd-34b1-4172-be26-70f54e561026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226242319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.4226242319
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.824596455
Short name T626
Test name
Test status
Simulation time 1688483423 ps
CPU time 22.65 seconds
Started Feb 29 12:53:46 PM PST 24
Finished Feb 29 12:54:09 PM PST 24
Peak memory 196964 kb
Host smart-fea24725-8318-49f8-880b-54a408a1e4fe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824596455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.824596455
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3997327349
Short name T184
Test name
Test status
Simulation time 125352588 ps
CPU time 0.73 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 195916 kb
Host smart-cbd1b34e-0a8a-4670-a6a7-c76c0b2374e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997327349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3997327349
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.3037641712
Short name T436
Test name
Test status
Simulation time 36086938 ps
CPU time 0.84 seconds
Started Feb 29 12:53:22 PM PST 24
Finished Feb 29 12:53:23 PM PST 24
Peak memory 196320 kb
Host smart-808af82c-95c5-43fe-83db-30c32b2cc306
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037641712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.3037641712
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.4189928272
Short name T671
Test name
Test status
Simulation time 307904943 ps
CPU time 2.85 seconds
Started Feb 29 12:53:30 PM PST 24
Finished Feb 29 12:53:33 PM PST 24
Peak memory 196528 kb
Host smart-17c7c761-e381-4308-9883-7ec4c4656f88
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189928272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.4189928272
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1396266501
Short name T489
Test name
Test status
Simulation time 77702796 ps
CPU time 1.85 seconds
Started Feb 29 12:53:33 PM PST 24
Finished Feb 29 12:53:34 PM PST 24
Peak memory 196272 kb
Host smart-10eb62b1-ffc1-4662-9512-9ccbdfee1a82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396266501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1396266501
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1211387840
Short name T484
Test name
Test status
Simulation time 239673992 ps
CPU time 1.25 seconds
Started Feb 29 12:53:48 PM PST 24
Finished Feb 29 12:53:50 PM PST 24
Peak memory 197132 kb
Host smart-3b0aa049-bcc5-4e9a-8a8c-0f757ef72d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211387840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1211387840
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1133053461
Short name T403
Test name
Test status
Simulation time 81215900 ps
CPU time 0.88 seconds
Started Feb 29 12:53:17 PM PST 24
Finished Feb 29 12:53:18 PM PST 24
Peak memory 196660 kb
Host smart-323698f7-c62a-4c78-92bc-3ec092b1dec3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133053461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1133053461
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2885738879
Short name T701
Test name
Test status
Simulation time 195215391 ps
CPU time 2.62 seconds
Started Feb 29 12:53:43 PM PST 24
Finished Feb 29 12:53:46 PM PST 24
Peak memory 198088 kb
Host smart-411b452a-15fa-4e95-9396-906d5b1f60bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885738879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2885738879
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.4000066465
Short name T402
Test name
Test status
Simulation time 90862780 ps
CPU time 1.36 seconds
Started Feb 29 12:53:17 PM PST 24
Finished Feb 29 12:53:19 PM PST 24
Peak memory 196688 kb
Host smart-a2a6c02a-40bc-472a-bad2-3dce432c3415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000066465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.4000066465
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2489720004
Short name T464
Test name
Test status
Simulation time 143727104 ps
CPU time 1.13 seconds
Started Feb 29 12:53:46 PM PST 24
Finished Feb 29 12:53:48 PM PST 24
Peak memory 195912 kb
Host smart-546a29a7-a59b-4b87-8bec-bb14ebaae91b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489720004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2489720004
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2889691646
Short name T341
Test name
Test status
Simulation time 37795854341 ps
CPU time 98.42 seconds
Started Feb 29 12:53:45 PM PST 24
Finished Feb 29 12:55:23 PM PST 24
Peak memory 198220 kb
Host smart-6bd58d8b-0289-4956-b05e-b6720807ffd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889691646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2889691646
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2712278296
Short name T508
Test name
Test status
Simulation time 12169869 ps
CPU time 0.57 seconds
Started Feb 29 12:52:53 PM PST 24
Finished Feb 29 12:52:54 PM PST 24
Peak memory 193920 kb
Host smart-90e6d941-8b0f-45fd-b5c4-94b548a7ba91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712278296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2712278296
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.4224264472
Short name T148
Test name
Test status
Simulation time 93988538 ps
CPU time 0.7 seconds
Started Feb 29 12:52:51 PM PST 24
Finished Feb 29 12:52:52 PM PST 24
Peak memory 195212 kb
Host smart-2b80c02c-4fec-41c3-ad41-0bffd4751f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224264472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.4224264472
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3667981513
Short name T214
Test name
Test status
Simulation time 2956181516 ps
CPU time 20.54 seconds
Started Feb 29 12:52:44 PM PST 24
Finished Feb 29 12:53:05 PM PST 24
Peak memory 197700 kb
Host smart-866e3951-482b-4bde-88a2-a04d319fd3d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667981513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3667981513
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3647889601
Short name T193
Test name
Test status
Simulation time 151974504 ps
CPU time 0.98 seconds
Started Feb 29 12:52:48 PM PST 24
Finished Feb 29 12:52:50 PM PST 24
Peak memory 196400 kb
Host smart-94b330d2-a35c-46ce-bc41-60642ca7997f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647889601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3647889601
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2097025888
Short name T139
Test name
Test status
Simulation time 445310506 ps
CPU time 1.53 seconds
Started Feb 29 12:52:43 PM PST 24
Finished Feb 29 12:52:46 PM PST 24
Peak memory 197256 kb
Host smart-dc75548c-e7bf-4a89-b907-1345327be8a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097025888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2097025888
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.4025488021
Short name T561
Test name
Test status
Simulation time 171506378 ps
CPU time 3.45 seconds
Started Feb 29 12:52:47 PM PST 24
Finished Feb 29 12:52:51 PM PST 24
Peak memory 198176 kb
Host smart-4e413de8-6bbf-44f6-b6ea-e719ca746e36
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025488021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.4025488021
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2250852658
Short name T716
Test name
Test status
Simulation time 277898401 ps
CPU time 2.96 seconds
Started Feb 29 12:53:03 PM PST 24
Finished Feb 29 12:53:06 PM PST 24
Peak memory 195928 kb
Host smart-53377e7d-b30f-4911-b7c3-5a8291b9a937
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250852658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2250852658
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.466317339
Short name T398
Test name
Test status
Simulation time 106277083 ps
CPU time 1.08 seconds
Started Feb 29 12:52:56 PM PST 24
Finished Feb 29 12:52:58 PM PST 24
Peak memory 195856 kb
Host smart-49451ea9-2180-450f-a7ae-c34367811ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466317339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.466317339
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2259263930
Short name T658
Test name
Test status
Simulation time 232374866 ps
CPU time 1.16 seconds
Started Feb 29 12:52:43 PM PST 24
Finished Feb 29 12:52:45 PM PST 24
Peak memory 196096 kb
Host smart-01406247-1803-4b3c-a8f0-5e55b72f2523
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259263930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2259263930
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2530114671
Short name T68
Test name
Test status
Simulation time 344831622 ps
CPU time 3.79 seconds
Started Feb 29 12:53:10 PM PST 24
Finished Feb 29 12:53:14 PM PST 24
Peak memory 198008 kb
Host smart-056f38a2-375b-4625-949f-61cbde1ec4dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530114671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2530114671
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.886038058
Short name T35
Test name
Test status
Simulation time 93677649 ps
CPU time 0.93 seconds
Started Feb 29 12:53:09 PM PST 24
Finished Feb 29 12:53:10 PM PST 24
Peak memory 213780 kb
Host smart-c3fa4a25-e0a6-463c-aa26-76136c3165b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886038058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.886038058
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.280128479
Short name T135
Test name
Test status
Simulation time 75028640 ps
CPU time 0.94 seconds
Started Feb 29 12:52:45 PM PST 24
Finished Feb 29 12:52:47 PM PST 24
Peak memory 196588 kb
Host smart-d4c3da2e-f91a-4895-b035-e8697f77ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280128479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.280128479
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1042736514
Short name T593
Test name
Test status
Simulation time 1596743417 ps
CPU time 1.33 seconds
Started Feb 29 12:52:48 PM PST 24
Finished Feb 29 12:52:49 PM PST 24
Peak memory 196544 kb
Host smart-e16de3c9-e2a0-4be5-9264-c6c30570ca61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042736514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1042736514
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.2275485485
Short name T56
Test name
Test status
Simulation time 73890118168 ps
CPU time 1665.77 seconds
Started Feb 29 12:52:45 PM PST 24
Finished Feb 29 01:20:32 PM PST 24
Peak memory 198356 kb
Host smart-7ef33a8a-418f-4ff0-8dcd-75a98981868a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2275485485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.2275485485
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.3406741627
Short name T16
Test name
Test status
Simulation time 13913521 ps
CPU time 0.56 seconds
Started Feb 29 12:53:21 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 193872 kb
Host smart-e623a19a-ee64-4492-b8f1-78ef196b8db1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406741627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.3406741627
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2648843986
Short name T391
Test name
Test status
Simulation time 23661730 ps
CPU time 0.74 seconds
Started Feb 29 12:53:47 PM PST 24
Finished Feb 29 12:53:48 PM PST 24
Peak memory 195132 kb
Host smart-fa2d0f72-51eb-40a4-897f-4f5373ff7f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648843986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2648843986
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1995182786
Short name T565
Test name
Test status
Simulation time 3815683851 ps
CPU time 26.67 seconds
Started Feb 29 12:53:36 PM PST 24
Finished Feb 29 12:54:03 PM PST 24
Peak memory 198156 kb
Host smart-23697fe7-6a62-4abf-a487-c3d8e33eae9f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995182786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1995182786
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3753394733
Short name T373
Test name
Test status
Simulation time 204424248 ps
CPU time 0.89 seconds
Started Feb 29 12:53:32 PM PST 24
Finished Feb 29 12:53:33 PM PST 24
Peak memory 195936 kb
Host smart-0e2ff37c-da14-4180-918f-d7013a573584
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753394733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3753394733
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1498299030
Short name T495
Test name
Test status
Simulation time 71379509 ps
CPU time 1.22 seconds
Started Feb 29 12:53:19 PM PST 24
Finished Feb 29 12:53:21 PM PST 24
Peak memory 195908 kb
Host smart-7879da1c-fc3b-445c-90cd-73ea861c08f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498299030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1498299030
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1786219945
Short name T73
Test name
Test status
Simulation time 94219577 ps
CPU time 3.48 seconds
Started Feb 29 12:53:31 PM PST 24
Finished Feb 29 12:53:35 PM PST 24
Peak memory 198080 kb
Host smart-e9bae23e-db39-49d5-a4fa-7fb9bf46592f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786219945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1786219945
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.288006124
Short name T242
Test name
Test status
Simulation time 29277668 ps
CPU time 0.91 seconds
Started Feb 29 12:53:27 PM PST 24
Finished Feb 29 12:53:28 PM PST 24
Peak memory 194476 kb
Host smart-3472fbff-4182-4d79-b0e2-fa5080f403d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288006124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
288006124
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.106770186
Short name T267
Test name
Test status
Simulation time 62541266 ps
CPU time 1.17 seconds
Started Feb 29 12:53:19 PM PST 24
Finished Feb 29 12:53:21 PM PST 24
Peak memory 197004 kb
Host smart-2191d56a-c1a5-4ef9-8c4a-289182d8e2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106770186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.106770186
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.913443051
Short name T456
Test name
Test status
Simulation time 29997352 ps
CPU time 1.09 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:20 PM PST 24
Peak memory 195832 kb
Host smart-b0966b9b-75cf-4fc2-8175-b1aa00a0709e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913443051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.913443051
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.934623265
Short name T130
Test name
Test status
Simulation time 1246876184 ps
CPU time 5.06 seconds
Started Feb 29 12:53:49 PM PST 24
Finished Feb 29 12:53:55 PM PST 24
Peak memory 198052 kb
Host smart-05d69577-aa5c-4d8f-a19d-718f47c0f9df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934623265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.934623265
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1721801705
Short name T607
Test name
Test status
Simulation time 58396458 ps
CPU time 1.07 seconds
Started Feb 29 12:53:28 PM PST 24
Finished Feb 29 12:53:29 PM PST 24
Peak memory 196312 kb
Host smart-baa7dfdc-f6f1-4506-b583-197be0b9c638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721801705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1721801705
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3289234285
Short name T432
Test name
Test status
Simulation time 54942595 ps
CPU time 0.91 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:20 PM PST 24
Peak memory 195444 kb
Host smart-0a6c6648-2754-46ef-a2d4-465908577e5a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289234285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3289234285
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.5785752
Short name T609
Test name
Test status
Simulation time 33350969016 ps
CPU time 84.67 seconds
Started Feb 29 12:53:21 PM PST 24
Finished Feb 29 12:54:47 PM PST 24
Peak memory 198160 kb
Host smart-7bdc79f8-5342-47f6-8967-88b1aef8ad41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5785752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TES
T_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpi
o_stress_all.5785752
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2563175381
Short name T708
Test name
Test status
Simulation time 614796822032 ps
CPU time 1776.31 seconds
Started Feb 29 12:53:28 PM PST 24
Finished Feb 29 01:23:04 PM PST 24
Peak memory 198332 kb
Host smart-75e3523a-440f-4285-83ea-15c33c675014
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2563175381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2563175381
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.418487566
Short name T290
Test name
Test status
Simulation time 14501617 ps
CPU time 0.55 seconds
Started Feb 29 12:53:46 PM PST 24
Finished Feb 29 12:53:47 PM PST 24
Peak memory 193880 kb
Host smart-bca435ba-140f-4c21-b142-1ea26ee64c2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418487566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.418487566
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1827702585
Short name T594
Test name
Test status
Simulation time 29494613 ps
CPU time 0.86 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 195972 kb
Host smart-f845e1a1-caac-437a-95ef-7600622a829c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827702585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1827702585
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.805635866
Short name T651
Test name
Test status
Simulation time 348358459 ps
CPU time 6.04 seconds
Started Feb 29 12:53:36 PM PST 24
Finished Feb 29 12:53:43 PM PST 24
Peak memory 196932 kb
Host smart-d8d47581-a61e-477e-8d87-81ad1c4f60a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805635866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.805635866
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2916511822
Short name T400
Test name
Test status
Simulation time 138579016 ps
CPU time 0.77 seconds
Started Feb 29 12:53:29 PM PST 24
Finished Feb 29 12:53:30 PM PST 24
Peak memory 194680 kb
Host smart-498a79ca-f911-4413-9f93-68113ef6db57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916511822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2916511822
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.232653853
Short name T551
Test name
Test status
Simulation time 125971968 ps
CPU time 1.02 seconds
Started Feb 29 12:53:31 PM PST 24
Finished Feb 29 12:53:32 PM PST 24
Peak memory 195992 kb
Host smart-a394eb89-8f8c-4f5d-b440-3cfc041aa5ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232653853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.232653853
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1514459941
Short name T144
Test name
Test status
Simulation time 24879580 ps
CPU time 1.12 seconds
Started Feb 29 12:53:42 PM PST 24
Finished Feb 29 12:53:44 PM PST 24
Peak memory 197468 kb
Host smart-e6553cae-5e1a-4c9f-9073-bf341b12d7f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514459941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1514459941
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2554722181
Short name T468
Test name
Test status
Simulation time 231722853 ps
CPU time 2.55 seconds
Started Feb 29 12:53:45 PM PST 24
Finished Feb 29 12:53:49 PM PST 24
Peak memory 197168 kb
Host smart-a8823cf0-d2f0-45ff-a2d0-6c48f25f34db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554722181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2554722181
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1470716989
Short name T393
Test name
Test status
Simulation time 125188564 ps
CPU time 0.84 seconds
Started Feb 29 12:53:21 PM PST 24
Finished Feb 29 12:53:23 PM PST 24
Peak memory 195980 kb
Host smart-205f4520-508b-436f-b42a-ecf8e83cedea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470716989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1470716989
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2460702958
Short name T146
Test name
Test status
Simulation time 16808136 ps
CPU time 0.66 seconds
Started Feb 29 12:53:22 PM PST 24
Finished Feb 29 12:53:23 PM PST 24
Peak memory 194936 kb
Host smart-a1a8868b-ed6f-41c1-821f-762f8301a6ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460702958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2460702958
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.4020961278
Short name T228
Test name
Test status
Simulation time 851323885 ps
CPU time 4.71 seconds
Started Feb 29 12:53:47 PM PST 24
Finished Feb 29 12:53:52 PM PST 24
Peak memory 197848 kb
Host smart-ac240555-55a0-4a31-b94d-1ca89ab60b52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020961278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.4020961278
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3936031207
Short name T18
Test name
Test status
Simulation time 516255178 ps
CPU time 1.46 seconds
Started Feb 29 12:53:46 PM PST 24
Finished Feb 29 12:53:48 PM PST 24
Peak memory 196800 kb
Host smart-9136054f-ac2e-4f75-86a4-b156bb540106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936031207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3936031207
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2261129687
Short name T218
Test name
Test status
Simulation time 116744428 ps
CPU time 1.01 seconds
Started Feb 29 12:53:45 PM PST 24
Finished Feb 29 12:53:47 PM PST 24
Peak memory 195696 kb
Host smart-919dc827-1610-4317-9566-f0145b0efafd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261129687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2261129687
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2519529167
Short name T564
Test name
Test status
Simulation time 4773470406 ps
CPU time 32.15 seconds
Started Feb 29 12:54:04 PM PST 24
Finished Feb 29 12:54:37 PM PST 24
Peak memory 198156 kb
Host smart-e8766deb-598e-41f0-94a2-df0d8a397263
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519529167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2519529167
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.172361848
Short name T182
Test name
Test status
Simulation time 65406706 ps
CPU time 0.6 seconds
Started Feb 29 12:53:22 PM PST 24
Finished Feb 29 12:53:23 PM PST 24
Peak memory 194824 kb
Host smart-2297f28b-744f-405e-8c14-207e64e812aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172361848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.172361848
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.607484028
Short name T357
Test name
Test status
Simulation time 105589901 ps
CPU time 0.73 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 195224 kb
Host smart-0a1b2185-1002-49cf-bf07-78f533a4fe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607484028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.607484028
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3152044927
Short name T466
Test name
Test status
Simulation time 476733123 ps
CPU time 15.79 seconds
Started Feb 29 12:53:22 PM PST 24
Finished Feb 29 12:53:39 PM PST 24
Peak memory 195604 kb
Host smart-a4e94426-9420-4914-9501-f3dae27bb91a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152044927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3152044927
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2962003683
Short name T518
Test name
Test status
Simulation time 574407588 ps
CPU time 1 seconds
Started Feb 29 12:53:36 PM PST 24
Finished Feb 29 12:53:38 PM PST 24
Peak memory 196740 kb
Host smart-52d0c1d8-c261-4c30-a41d-cd78aacd5c37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962003683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2962003683
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2373821359
Short name T216
Test name
Test status
Simulation time 31368226 ps
CPU time 0.91 seconds
Started Feb 29 12:53:41 PM PST 24
Finished Feb 29 12:53:42 PM PST 24
Peak memory 197220 kb
Host smart-565e6241-9e05-4bf0-9279-2ffa354e4f52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373821359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2373821359
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.304463069
Short name T425
Test name
Test status
Simulation time 39496037 ps
CPU time 1.48 seconds
Started Feb 29 12:53:29 PM PST 24
Finished Feb 29 12:53:30 PM PST 24
Peak memory 196484 kb
Host smart-22be533b-9bb9-4f5c-b4d4-c5f715377a9a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304463069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.304463069
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.726988186
Short name T376
Test name
Test status
Simulation time 158212400 ps
CPU time 3.08 seconds
Started Feb 29 12:53:45 PM PST 24
Finished Feb 29 12:53:49 PM PST 24
Peak memory 198068 kb
Host smart-e4b00911-cc4f-44b9-958f-e6e4c638ce0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726988186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger.
726988186
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2481940945
Short name T522
Test name
Test status
Simulation time 48351851 ps
CPU time 1.05 seconds
Started Feb 29 12:53:20 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 196096 kb
Host smart-6183d399-95a0-416f-8f12-eac0a81aad81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481940945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2481940945
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.801962571
Short name T689
Test name
Test status
Simulation time 33268839 ps
CPU time 1.11 seconds
Started Feb 29 12:53:47 PM PST 24
Finished Feb 29 12:53:48 PM PST 24
Peak memory 196032 kb
Host smart-ac108886-e479-4e0d-b84e-eb2034c350c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801962571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.801962571
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.181233670
Short name T475
Test name
Test status
Simulation time 332984303 ps
CPU time 3.91 seconds
Started Feb 29 12:53:44 PM PST 24
Finished Feb 29 12:53:48 PM PST 24
Peak memory 198088 kb
Host smart-0e5daecc-7311-4413-93b9-a34e7f4d4b31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181233670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.181233670
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.540818755
Short name T215
Test name
Test status
Simulation time 81952823 ps
CPU time 1.44 seconds
Started Feb 29 12:53:24 PM PST 24
Finished Feb 29 12:53:26 PM PST 24
Peak memory 195584 kb
Host smart-9d69ac73-79b5-4e6e-a364-679667fb9c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540818755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.540818755
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2068091496
Short name T210
Test name
Test status
Simulation time 217895498 ps
CPU time 1.25 seconds
Started Feb 29 12:53:32 PM PST 24
Finished Feb 29 12:53:33 PM PST 24
Peak memory 195616 kb
Host smart-96b8c177-1252-47e9-8564-b0e191c652fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068091496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2068091496
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.377620544
Short name T7
Test name
Test status
Simulation time 10320171414 ps
CPU time 34.13 seconds
Started Feb 29 12:54:03 PM PST 24
Finished Feb 29 12:54:38 PM PST 24
Peak memory 198200 kb
Host smart-d93e0de3-e54b-4f87-b934-d1ce71594b47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377620544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.377620544
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.3282561811
Short name T60
Test name
Test status
Simulation time 63080931868 ps
CPU time 1320.97 seconds
Started Feb 29 12:53:53 PM PST 24
Finished Feb 29 01:15:55 PM PST 24
Peak memory 198348 kb
Host smart-fc08686c-8869-4f31-bc4d-9bfa3f718510
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3282561811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.3282561811
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3560571824
Short name T650
Test name
Test status
Simulation time 35046899 ps
CPU time 0.59 seconds
Started Feb 29 12:53:45 PM PST 24
Finished Feb 29 12:53:47 PM PST 24
Peak memory 194140 kb
Host smart-570aaf32-49df-4966-b2d6-8290d0701daf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560571824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3560571824
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1083618153
Short name T291
Test name
Test status
Simulation time 18103115 ps
CPU time 0.66 seconds
Started Feb 29 12:53:33 PM PST 24
Finished Feb 29 12:53:34 PM PST 24
Peak memory 194688 kb
Host smart-11b5b753-2f2e-4c68-b6d7-da861ad792ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083618153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1083618153
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.913454820
Short name T637
Test name
Test status
Simulation time 1952078110 ps
CPU time 20.34 seconds
Started Feb 29 12:53:36 PM PST 24
Finished Feb 29 12:53:56 PM PST 24
Peak memory 195632 kb
Host smart-73a2b0b8-50a3-4dc7-ae4a-6528b9944593
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913454820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.913454820
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.853388076
Short name T156
Test name
Test status
Simulation time 37526603 ps
CPU time 0.69 seconds
Started Feb 29 12:53:43 PM PST 24
Finished Feb 29 12:53:44 PM PST 24
Peak memory 194632 kb
Host smart-71686fad-6e52-4172-a4d1-930d7c5f8fec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853388076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.853388076
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2293941804
Short name T682
Test name
Test status
Simulation time 110916912 ps
CPU time 0.9 seconds
Started Feb 29 12:53:41 PM PST 24
Finished Feb 29 12:53:42 PM PST 24
Peak memory 196060 kb
Host smart-f0e67fd5-3d73-429d-ad28-3c2752bc8b91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293941804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2293941804
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.495428878
Short name T202
Test name
Test status
Simulation time 30206434 ps
CPU time 1.15 seconds
Started Feb 29 12:53:42 PM PST 24
Finished Feb 29 12:53:43 PM PST 24
Peak memory 197808 kb
Host smart-8d6b9d94-25c0-4630-bad9-f92dc44f4a88
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495428878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.495428878
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.344668520
Short name T128
Test name
Test status
Simulation time 59865140 ps
CPU time 1.29 seconds
Started Feb 29 12:53:33 PM PST 24
Finished Feb 29 12:53:34 PM PST 24
Peak memory 196876 kb
Host smart-707e35d1-4eb8-4e8d-a113-524c8aa5d892
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344668520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
344668520
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1528119039
Short name T499
Test name
Test status
Simulation time 25672973 ps
CPU time 0.7 seconds
Started Feb 29 12:53:36 PM PST 24
Finished Feb 29 12:53:37 PM PST 24
Peak memory 195304 kb
Host smart-b665a838-10d9-4334-8dee-e22470866e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528119039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1528119039
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1749198186
Short name T219
Test name
Test status
Simulation time 28468595 ps
CPU time 0.78 seconds
Started Feb 29 12:53:28 PM PST 24
Finished Feb 29 12:53:29 PM PST 24
Peak memory 195356 kb
Host smart-bc301746-50ce-42b5-b98f-32855cc499d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749198186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1749198186
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1569858161
Short name T369
Test name
Test status
Simulation time 400823012 ps
CPU time 5.09 seconds
Started Feb 29 12:53:49 PM PST 24
Finished Feb 29 12:53:55 PM PST 24
Peak memory 197904 kb
Host smart-d96dc9fd-47bf-4005-84a3-f1d5f706c08c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569858161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1569858161
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.265326483
Short name T159
Test name
Test status
Simulation time 25282306 ps
CPU time 0.86 seconds
Started Feb 29 12:53:42 PM PST 24
Finished Feb 29 12:53:43 PM PST 24
Peak memory 197020 kb
Host smart-654997f8-a513-478a-b178-0f392606a502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265326483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.265326483
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3709318011
Short name T364
Test name
Test status
Simulation time 315882734 ps
CPU time 1.13 seconds
Started Feb 29 12:53:48 PM PST 24
Finished Feb 29 12:53:49 PM PST 24
Peak memory 198036 kb
Host smart-4286d434-4f09-4578-a469-fc63a208308f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709318011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3709318011
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1979207906
Short name T591
Test name
Test status
Simulation time 17983734403 ps
CPU time 116.43 seconds
Started Feb 29 12:53:44 PM PST 24
Finished Feb 29 12:55:42 PM PST 24
Peak memory 198124 kb
Host smart-0cfad9c1-6f61-4bbe-871b-bf80e5d8c2f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979207906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1979207906
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3763445515
Short name T196
Test name
Test status
Simulation time 17219830 ps
CPU time 0.54 seconds
Started Feb 29 12:53:45 PM PST 24
Finished Feb 29 12:53:46 PM PST 24
Peak memory 193900 kb
Host smart-4afebc33-2379-4f18-aba9-691d92aa8c35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763445515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3763445515
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.118851476
Short name T268
Test name
Test status
Simulation time 23605199 ps
CPU time 0.64 seconds
Started Feb 29 12:53:31 PM PST 24
Finished Feb 29 12:53:32 PM PST 24
Peak memory 194044 kb
Host smart-1c7e4ee3-b5bb-4997-a61c-bf766703561a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118851476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.118851476
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3125116651
Short name T32
Test name
Test status
Simulation time 1968095152 ps
CPU time 24.53 seconds
Started Feb 29 12:53:42 PM PST 24
Finished Feb 29 12:54:07 PM PST 24
Peak memory 198068 kb
Host smart-abfc58e1-c133-4e03-9694-28600faaa6ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125116651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3125116651
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.836693463
Short name T710
Test name
Test status
Simulation time 80986719 ps
CPU time 0.92 seconds
Started Feb 29 12:53:49 PM PST 24
Finished Feb 29 12:53:50 PM PST 24
Peak memory 197196 kb
Host smart-020e2d87-6c82-47b8-9771-47c0295ea350
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836693463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.836693463
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3718019532
Short name T514
Test name
Test status
Simulation time 154160234 ps
CPU time 1.12 seconds
Started Feb 29 12:53:33 PM PST 24
Finished Feb 29 12:53:35 PM PST 24
Peak memory 195884 kb
Host smart-e62c6550-5f57-4f87-acba-1c7fa28a30f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718019532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3718019532
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3063336864
Short name T274
Test name
Test status
Simulation time 273953419 ps
CPU time 0.99 seconds
Started Feb 29 12:54:06 PM PST 24
Finished Feb 29 12:54:07 PM PST 24
Peak memory 196212 kb
Host smart-39105b77-8f30-437f-ab6d-ddd2b9e2a8ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063336864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3063336864
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.881884208
Short name T381
Test name
Test status
Simulation time 92096882 ps
CPU time 1.27 seconds
Started Feb 29 12:53:57 PM PST 24
Finished Feb 29 12:53:58 PM PST 24
Peak memory 196468 kb
Host smart-62d0ce15-9f3b-43d3-a5cd-42202ba233cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881884208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
881884208
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3430590075
Short name T497
Test name
Test status
Simulation time 82309625 ps
CPU time 1.19 seconds
Started Feb 29 12:53:46 PM PST 24
Finished Feb 29 12:53:48 PM PST 24
Peak memory 198088 kb
Host smart-1f2b6c11-ce51-4d9d-8b58-2626ae78a864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430590075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3430590075
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.4088199151
Short name T642
Test name
Test status
Simulation time 38083237 ps
CPU time 0.8 seconds
Started Feb 29 12:53:54 PM PST 24
Finished Feb 29 12:53:55 PM PST 24
Peak memory 195560 kb
Host smart-bfe0702d-02a4-4e4b-a003-eff60a54e08b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088199151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.4088199151
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.6331601
Short name T362
Test name
Test status
Simulation time 193584589 ps
CPU time 1.67 seconds
Started Feb 29 12:53:38 PM PST 24
Finished Feb 29 12:53:40 PM PST 24
Peak memory 197928 kb
Host smart-51967ade-5253-4450-a4d9-06cfee20aae9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6331601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_wr
ites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rando
m_long_reg_writes_reg_reads.6331601
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1315430396
Short name T672
Test name
Test status
Simulation time 450284851 ps
CPU time 1.12 seconds
Started Feb 29 12:53:50 PM PST 24
Finished Feb 29 12:53:52 PM PST 24
Peak memory 195652 kb
Host smart-2d302a3e-306c-4d64-bad1-f3b5971d33d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315430396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1315430396
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1692486713
Short name T519
Test name
Test status
Simulation time 200700428 ps
CPU time 0.98 seconds
Started Feb 29 12:53:29 PM PST 24
Finished Feb 29 12:53:30 PM PST 24
Peak memory 196544 kb
Host smart-17e34a71-cbe8-45a5-93cc-44beaac9d361
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692486713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1692486713
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3245209441
Short name T5
Test name
Test status
Simulation time 19499546424 ps
CPU time 170.28 seconds
Started Feb 29 12:53:51 PM PST 24
Finished Feb 29 12:56:42 PM PST 24
Peak memory 198148 kb
Host smart-4c37b14f-ee1b-4b41-bb63-6c422db92617
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245209441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3245209441
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.1537432635
Short name T255
Test name
Test status
Simulation time 123633546326 ps
CPU time 950.24 seconds
Started Feb 29 12:53:51 PM PST 24
Finished Feb 29 01:09:42 PM PST 24
Peak memory 198332 kb
Host smart-629cf39b-ca51-473a-82e0-6e5386dae517
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1537432635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.1537432635
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3075971481
Short name T213
Test name
Test status
Simulation time 43213884 ps
CPU time 0.57 seconds
Started Feb 29 12:53:44 PM PST 24
Finished Feb 29 12:53:45 PM PST 24
Peak memory 193924 kb
Host smart-bc049f1d-a85b-4ca3-b035-06b785825544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075971481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3075971481
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2676572526
Short name T368
Test name
Test status
Simulation time 33092507 ps
CPU time 0.95 seconds
Started Feb 29 12:53:52 PM PST 24
Finished Feb 29 12:53:53 PM PST 24
Peak memory 195916 kb
Host smart-f54f2bfe-000c-4b7e-95c5-5f47a1590f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676572526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2676572526
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2268912962
Short name T350
Test name
Test status
Simulation time 2228579271 ps
CPU time 10.09 seconds
Started Feb 29 12:53:51 PM PST 24
Finished Feb 29 12:54:02 PM PST 24
Peak memory 197320 kb
Host smart-f1fb7c46-4de0-4e83-a885-73c2366b0c1c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268912962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2268912962
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.183790316
Short name T688
Test name
Test status
Simulation time 144677953 ps
CPU time 1.01 seconds
Started Feb 29 12:53:40 PM PST 24
Finished Feb 29 12:53:41 PM PST 24
Peak memory 196508 kb
Host smart-819d8c9d-dd1d-463a-819a-fed1c8038fd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183790316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.183790316
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3583395883
Short name T204
Test name
Test status
Simulation time 64543081 ps
CPU time 0.82 seconds
Started Feb 29 12:53:58 PM PST 24
Finished Feb 29 12:53:59 PM PST 24
Peak memory 195564 kb
Host smart-7bd14d76-979f-409b-991d-f3f2a9a04e21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583395883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3583395883
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.238571514
Short name T177
Test name
Test status
Simulation time 140783731 ps
CPU time 2.66 seconds
Started Feb 29 12:54:01 PM PST 24
Finished Feb 29 12:54:04 PM PST 24
Peak memory 198184 kb
Host smart-f66cb1e2-d42b-4efe-b311-e8255da98a74
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238571514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.238571514
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.909736101
Short name T293
Test name
Test status
Simulation time 706280244 ps
CPU time 3.02 seconds
Started Feb 29 12:54:01 PM PST 24
Finished Feb 29 12:54:04 PM PST 24
Peak memory 196528 kb
Host smart-d5299c75-4556-4161-898d-374d381568d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909736101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
909736101
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.375765419
Short name T235
Test name
Test status
Simulation time 354391592 ps
CPU time 0.89 seconds
Started Feb 29 12:53:45 PM PST 24
Finished Feb 29 12:53:47 PM PST 24
Peak memory 196668 kb
Host smart-779fb731-e435-4575-899e-99ff72f325b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375765419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.375765419
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2321690001
Short name T281
Test name
Test status
Simulation time 31043851 ps
CPU time 0.76 seconds
Started Feb 29 12:53:36 PM PST 24
Finished Feb 29 12:53:37 PM PST 24
Peak memory 195580 kb
Host smart-6cb8bf48-82f8-484f-be19-12b7a8dfdea7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321690001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2321690001
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2655747438
Short name T4
Test name
Test status
Simulation time 246582065 ps
CPU time 1.8 seconds
Started Feb 29 12:53:48 PM PST 24
Finished Feb 29 12:53:50 PM PST 24
Peak memory 198056 kb
Host smart-5e659e92-15a2-452f-b163-b23ac3a1ba81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655747438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2655747438
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.4079402375
Short name T390
Test name
Test status
Simulation time 286558302 ps
CPU time 1.26 seconds
Started Feb 29 12:53:43 PM PST 24
Finished Feb 29 12:53:45 PM PST 24
Peak memory 196084 kb
Host smart-2d94e38a-f58c-4516-b0a0-9517c115d9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079402375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.4079402375
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.626596924
Short name T249
Test name
Test status
Simulation time 371646285 ps
CPU time 1.48 seconds
Started Feb 29 12:53:52 PM PST 24
Finished Feb 29 12:53:54 PM PST 24
Peak memory 196816 kb
Host smart-d1c34a91-4ae8-4646-8d28-3f9ad2dca8d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626596924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.626596924
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2732791686
Short name T23
Test name
Test status
Simulation time 26288108231 ps
CPU time 75.57 seconds
Started Feb 29 12:53:36 PM PST 24
Finished Feb 29 12:54:52 PM PST 24
Peak memory 198268 kb
Host smart-779ca784-c3c2-4b92-ab4c-d271b04f21c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732791686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2732791686
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3499422929
Short name T579
Test name
Test status
Simulation time 38189345 ps
CPU time 0.56 seconds
Started Feb 29 12:53:55 PM PST 24
Finished Feb 29 12:53:56 PM PST 24
Peak memory 193836 kb
Host smart-41fdbe00-06b4-45e1-853d-dc68e8cd658f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499422929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3499422929
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3803231240
Short name T687
Test name
Test status
Simulation time 178614223 ps
CPU time 0.68 seconds
Started Feb 29 12:53:58 PM PST 24
Finished Feb 29 12:53:59 PM PST 24
Peak memory 194120 kb
Host smart-87481aa3-283e-4ec9-8a23-3bebac02db61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803231240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3803231240
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.43521284
Short name T550
Test name
Test status
Simulation time 800388434 ps
CPU time 7.81 seconds
Started Feb 29 12:53:47 PM PST 24
Finished Feb 29 12:53:55 PM PST 24
Peak memory 198060 kb
Host smart-27ee364a-06ee-49ae-a970-80760d6abb73
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43521284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stress
.43521284
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2088568976
Short name T172
Test name
Test status
Simulation time 160382148 ps
CPU time 0.74 seconds
Started Feb 29 12:53:46 PM PST 24
Finished Feb 29 12:53:47 PM PST 24
Peak memory 196508 kb
Host smart-f909c296-44fa-4e29-a895-80d0f1d91354
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088568976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2088568976
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.4067736432
Short name T252
Test name
Test status
Simulation time 110069947 ps
CPU time 0.79 seconds
Started Feb 29 12:53:30 PM PST 24
Finished Feb 29 12:53:36 PM PST 24
Peak memory 195488 kb
Host smart-970330b5-9dcb-4d27-a66f-e7e35038a2b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067736432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.4067736432
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1822975601
Short name T55
Test name
Test status
Simulation time 59632536 ps
CPU time 2.41 seconds
Started Feb 29 12:53:51 PM PST 24
Finished Feb 29 12:53:54 PM PST 24
Peak memory 198136 kb
Host smart-1f2d4b7c-cb64-4a57-9182-837d0d6c0fdd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822975601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1822975601
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.920795325
Short name T125
Test name
Test status
Simulation time 566852538 ps
CPU time 3.17 seconds
Started Feb 29 12:53:42 PM PST 24
Finished Feb 29 12:53:46 PM PST 24
Peak memory 198100 kb
Host smart-580c3dd3-3aad-4f63-ba1e-48e1a44a527e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920795325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
920795325
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.4150027451
Short name T155
Test name
Test status
Simulation time 24696639 ps
CPU time 0.94 seconds
Started Feb 29 12:53:43 PM PST 24
Finished Feb 29 12:53:45 PM PST 24
Peak memory 196048 kb
Host smart-87a4776c-5de2-4e3b-840c-6cde28e278c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150027451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.4150027451
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1453698565
Short name T325
Test name
Test status
Simulation time 82064824 ps
CPU time 0.69 seconds
Started Feb 29 12:53:33 PM PST 24
Finished Feb 29 12:53:34 PM PST 24
Peak memory 194388 kb
Host smart-010f44ba-9626-4ca4-804b-30cc623a3fe7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453698565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1453698565
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2101421542
Short name T323
Test name
Test status
Simulation time 343400400 ps
CPU time 3.39 seconds
Started Feb 29 12:53:40 PM PST 24
Finished Feb 29 12:53:43 PM PST 24
Peak memory 198068 kb
Host smart-e774462b-633f-450d-aacf-cf8af053124d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101421542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2101421542
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2060914657
Short name T250
Test name
Test status
Simulation time 125718151 ps
CPU time 1.22 seconds
Started Feb 29 12:53:44 PM PST 24
Finished Feb 29 12:53:45 PM PST 24
Peak memory 195904 kb
Host smart-c126f934-4906-4ea4-8075-8dc2daf7d4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060914657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2060914657
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2574503913
Short name T211
Test name
Test status
Simulation time 51522755 ps
CPU time 0.98 seconds
Started Feb 29 12:53:45 PM PST 24
Finished Feb 29 12:53:47 PM PST 24
Peak memory 195788 kb
Host smart-f96279ee-f156-4fe3-808a-33f35002c3e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574503913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2574503913
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1992031226
Short name T589
Test name
Test status
Simulation time 43664861171 ps
CPU time 114.29 seconds
Started Feb 29 12:54:00 PM PST 24
Finished Feb 29 12:55:54 PM PST 24
Peak memory 198188 kb
Host smart-2bb6b8bf-7ec7-4b71-b295-f8753de0ecef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992031226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1992031226
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.2523931153
Short name T532
Test name
Test status
Simulation time 136791920498 ps
CPU time 1073.81 seconds
Started Feb 29 12:53:41 PM PST 24
Finished Feb 29 01:11:36 PM PST 24
Peak memory 198376 kb
Host smart-0dc147f3-61bf-4ba8-bc88-1f1fa2f55eac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2523931153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.2523931153
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1794953306
Short name T483
Test name
Test status
Simulation time 11218882 ps
CPU time 0.53 seconds
Started Feb 29 12:53:55 PM PST 24
Finished Feb 29 12:53:56 PM PST 24
Peak memory 193920 kb
Host smart-fd897e23-9d07-4dbf-a562-d769159f0b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794953306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1794953306
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1473038703
Short name T585
Test name
Test status
Simulation time 51110888 ps
CPU time 1 seconds
Started Feb 29 12:53:56 PM PST 24
Finished Feb 29 12:53:57 PM PST 24
Peak memory 196596 kb
Host smart-211c68d7-8fa1-4c5d-bb72-e4fd8811091f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473038703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1473038703
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1166731885
Short name T169
Test name
Test status
Simulation time 8853526433 ps
CPU time 22.42 seconds
Started Feb 29 12:53:49 PM PST 24
Finished Feb 29 12:54:12 PM PST 24
Peak memory 197404 kb
Host smart-333f7f3f-63b6-4190-a840-e8f895f7e42f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166731885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1166731885
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3716500576
Short name T647
Test name
Test status
Simulation time 155940601 ps
CPU time 1.15 seconds
Started Feb 29 12:53:42 PM PST 24
Finished Feb 29 12:53:44 PM PST 24
Peak memory 198076 kb
Host smart-947d9fde-6d50-49e5-afe3-4985f66ff5b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716500576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3716500576
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1753988826
Short name T631
Test name
Test status
Simulation time 138792473 ps
CPU time 0.78 seconds
Started Feb 29 12:53:50 PM PST 24
Finished Feb 29 12:53:52 PM PST 24
Peak memory 195496 kb
Host smart-a8ade42b-b9cd-4e32-88cd-261f8068846d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753988826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1753988826
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.4043741265
Short name T63
Test name
Test status
Simulation time 44674664 ps
CPU time 1.77 seconds
Started Feb 29 12:53:49 PM PST 24
Finished Feb 29 12:53:55 PM PST 24
Peak memory 198184 kb
Host smart-8986e1d6-4788-4cc5-8d49-93a79a04932f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043741265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.4043741265
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2723541407
Short name T234
Test name
Test status
Simulation time 125254885 ps
CPU time 1.93 seconds
Started Feb 29 12:53:34 PM PST 24
Finished Feb 29 12:53:36 PM PST 24
Peak memory 197008 kb
Host smart-7a1a87e8-a142-4540-8170-39c61d7f72e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723541407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2723541407
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2107356580
Short name T583
Test name
Test status
Simulation time 99938974 ps
CPU time 0.95 seconds
Started Feb 29 12:53:49 PM PST 24
Finished Feb 29 12:53:51 PM PST 24
Peak memory 195996 kb
Host smart-2ec320b6-caa7-4230-8b84-65a5ab403cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107356580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2107356580
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1780856730
Short name T175
Test name
Test status
Simulation time 18999818 ps
CPU time 0.76 seconds
Started Feb 29 12:53:59 PM PST 24
Finished Feb 29 12:54:01 PM PST 24
Peak memory 196236 kb
Host smart-a54fe6d1-af8a-43f6-ba67-3c9dad0104f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780856730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1780856730
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2882078301
Short name T608
Test name
Test status
Simulation time 431094490 ps
CPU time 5.1 seconds
Started Feb 29 12:53:43 PM PST 24
Finished Feb 29 12:53:49 PM PST 24
Peak memory 198252 kb
Host smart-142123c1-fa17-4f65-b224-2b5b8d4dc754
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882078301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2882078301
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.292230942
Short name T659
Test name
Test status
Simulation time 316016509 ps
CPU time 1.31 seconds
Started Feb 29 12:53:44 PM PST 24
Finished Feb 29 12:53:45 PM PST 24
Peak memory 195656 kb
Host smart-de273f09-62cf-4d7e-a143-f99de465bbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292230942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.292230942
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.395279205
Short name T189
Test name
Test status
Simulation time 244737169 ps
CPU time 1.05 seconds
Started Feb 29 12:53:46 PM PST 24
Finished Feb 29 12:53:48 PM PST 24
Peak memory 195680 kb
Host smart-b94cfcbd-84c0-45bb-a87a-909ad73a2559
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395279205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.395279205
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3442265318
Short name T127
Test name
Test status
Simulation time 4456818316 ps
CPU time 119.7 seconds
Started Feb 29 12:53:40 PM PST 24
Finished Feb 29 12:55:40 PM PST 24
Peak memory 198100 kb
Host smart-92f95aa2-7e4c-432f-922d-ad7051dd7637
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442265318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3442265318
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1091543572
Short name T310
Test name
Test status
Simulation time 23405729 ps
CPU time 0.59 seconds
Started Feb 29 12:53:38 PM PST 24
Finished Feb 29 12:53:39 PM PST 24
Peak memory 194816 kb
Host smart-70bbaf58-c279-4e01-95a0-413751b90492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091543572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1091543572
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1265402010
Short name T347
Test name
Test status
Simulation time 35581712 ps
CPU time 0.64 seconds
Started Feb 29 12:53:59 PM PST 24
Finished Feb 29 12:54:00 PM PST 24
Peak memory 194648 kb
Host smart-2f21455d-4801-487d-83dc-e3715b5d7787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265402010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1265402010
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1126575882
Short name T481
Test name
Test status
Simulation time 714017020 ps
CPU time 17.56 seconds
Started Feb 29 12:53:41 PM PST 24
Finished Feb 29 12:53:59 PM PST 24
Peak memory 196368 kb
Host smart-8dddcf07-49a9-45c9-8ec2-48435e81859a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126575882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1126575882
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2237675312
Short name T415
Test name
Test status
Simulation time 102087530 ps
CPU time 0.7 seconds
Started Feb 29 12:53:33 PM PST 24
Finished Feb 29 12:53:34 PM PST 24
Peak memory 195268 kb
Host smart-ed1c0fa5-727a-402c-aa72-ecae2bf05184
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237675312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2237675312
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1989179433
Short name T67
Test name
Test status
Simulation time 198711776 ps
CPU time 1.37 seconds
Started Feb 29 12:53:44 PM PST 24
Finished Feb 29 12:53:47 PM PST 24
Peak memory 198144 kb
Host smart-79e90d3e-bec4-407f-9e29-9a3105953089
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989179433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1989179433
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3905667104
Short name T461
Test name
Test status
Simulation time 1014372614 ps
CPU time 3.27 seconds
Started Feb 29 12:54:00 PM PST 24
Finished Feb 29 12:54:04 PM PST 24
Peak memory 198136 kb
Host smart-bb9c6345-878b-4f1c-a4c2-73204357a8ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905667104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3905667104
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2150509905
Short name T277
Test name
Test status
Simulation time 703909079 ps
CPU time 3.09 seconds
Started Feb 29 12:53:38 PM PST 24
Finished Feb 29 12:53:41 PM PST 24
Peak memory 196948 kb
Host smart-3aa196f9-a3e8-46b9-af55-56f74ba06c01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150509905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2150509905
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.169243607
Short name T598
Test name
Test status
Simulation time 23795847 ps
CPU time 0.94 seconds
Started Feb 29 12:53:44 PM PST 24
Finished Feb 29 12:53:45 PM PST 24
Peak memory 195828 kb
Host smart-a0e58fda-7d38-46ef-8044-a7e7ea0ab3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169243607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.169243607
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.306867285
Short name T479
Test name
Test status
Simulation time 24804325 ps
CPU time 0.96 seconds
Started Feb 29 12:53:50 PM PST 24
Finished Feb 29 12:53:51 PM PST 24
Peak memory 196056 kb
Host smart-bb3d497c-2a62-4ef8-8e11-1b8529c7d829
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306867285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.306867285
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1658761990
Short name T655
Test name
Test status
Simulation time 75098401 ps
CPU time 3.33 seconds
Started Feb 29 12:53:55 PM PST 24
Finished Feb 29 12:53:59 PM PST 24
Peak memory 198016 kb
Host smart-808609df-f9ee-4cf2-ab4c-cb3b4e18682c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658761990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1658761990
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.446402421
Short name T65
Test name
Test status
Simulation time 48206389 ps
CPU time 1.34 seconds
Started Feb 29 12:53:47 PM PST 24
Finished Feb 29 12:53:49 PM PST 24
Peak memory 196236 kb
Host smart-5662f182-ecc6-4453-a86c-79d59604e618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446402421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.446402421
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.196936695
Short name T706
Test name
Test status
Simulation time 61766884 ps
CPU time 1.23 seconds
Started Feb 29 12:53:47 PM PST 24
Finished Feb 29 12:53:48 PM PST 24
Peak memory 196644 kb
Host smart-1b70b2cb-4cb9-42a3-9e83-0568b51d108e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196936695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.196936695
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1073583445
Short name T610
Test name
Test status
Simulation time 45235528672 ps
CPU time 153.52 seconds
Started Feb 29 12:53:46 PM PST 24
Finished Feb 29 12:56:20 PM PST 24
Peak memory 198176 kb
Host smart-77b06925-2932-42a9-b965-d5d7ef7e51c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073583445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1073583445
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.161082628
Short name T653
Test name
Test status
Simulation time 29307448069 ps
CPU time 672.72 seconds
Started Feb 29 12:53:45 PM PST 24
Finished Feb 29 01:04:59 PM PST 24
Peak memory 198308 kb
Host smart-6d3a58d2-6036-46a5-851f-4eb1450df2b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=161082628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.161082628
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2363528890
Short name T469
Test name
Test status
Simulation time 47422479 ps
CPU time 0.58 seconds
Started Feb 29 12:54:04 PM PST 24
Finished Feb 29 12:54:05 PM PST 24
Peak memory 193844 kb
Host smart-6853a289-3f59-4c3d-be22-b2641ec76666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363528890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2363528890
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.889806448
Short name T353
Test name
Test status
Simulation time 143365695 ps
CPU time 0.78 seconds
Started Feb 29 12:54:03 PM PST 24
Finished Feb 29 12:54:05 PM PST 24
Peak memory 195908 kb
Host smart-d59134d4-138a-4c6b-9a69-1ddac6f41de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889806448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.889806448
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3508003818
Short name T657
Test name
Test status
Simulation time 609246783 ps
CPU time 5.77 seconds
Started Feb 29 12:54:02 PM PST 24
Finished Feb 29 12:54:08 PM PST 24
Peak memory 197968 kb
Host smart-cc94d58d-2a10-4e62-bb90-665c7fe435f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508003818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3508003818
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.813337056
Short name T527
Test name
Test status
Simulation time 488221856 ps
CPU time 0.8 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:09 PM PST 24
Peak memory 196576 kb
Host smart-8c6b2a8c-59d7-4594-affa-97151a4c180f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813337056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.813337056
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3330349173
Short name T185
Test name
Test status
Simulation time 17212235 ps
CPU time 0.68 seconds
Started Feb 29 12:53:51 PM PST 24
Finished Feb 29 12:53:53 PM PST 24
Peak memory 194256 kb
Host smart-4bd7e89b-ab8b-478c-8e21-655b0e5c38e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330349173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3330349173
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.35376364
Short name T300
Test name
Test status
Simulation time 86358967 ps
CPU time 3.18 seconds
Started Feb 29 12:54:07 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 196732 kb
Host smart-5bf72567-66d4-4f8e-83a0-27d9504cbaf0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35376364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.gpio_intr_with_filter_rand_intr_event.35376364
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3237504186
Short name T163
Test name
Test status
Simulation time 63582731 ps
CPU time 1.9 seconds
Started Feb 29 12:53:47 PM PST 24
Finished Feb 29 12:53:50 PM PST 24
Peak memory 197144 kb
Host smart-000d9035-a066-45b3-8775-dc038b22b940
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237504186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3237504186
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3758370385
Short name T705
Test name
Test status
Simulation time 86915093 ps
CPU time 0.66 seconds
Started Feb 29 12:53:49 PM PST 24
Finished Feb 29 12:53:50 PM PST 24
Peak memory 194200 kb
Host smart-26dafff6-2265-4097-a65a-caff5470afe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758370385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3758370385
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.631162672
Short name T476
Test name
Test status
Simulation time 25358556 ps
CPU time 0.9 seconds
Started Feb 29 12:53:56 PM PST 24
Finished Feb 29 12:53:57 PM PST 24
Peak memory 196124 kb
Host smart-e2f4e0fe-0032-47ec-885f-69e351e53565
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631162672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.631162672
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.519741567
Short name T435
Test name
Test status
Simulation time 345197369 ps
CPU time 5.35 seconds
Started Feb 29 12:54:06 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 198056 kb
Host smart-433bbf46-b40a-404d-84bf-6456b9e34e83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519741567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.519741567
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1101067740
Short name T246
Test name
Test status
Simulation time 220503395 ps
CPU time 1.25 seconds
Started Feb 29 12:53:33 PM PST 24
Finished Feb 29 12:53:34 PM PST 24
Peak memory 197980 kb
Host smart-d7eeb66a-b5a0-4e7a-b423-11d0c33624ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101067740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1101067740
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1571084295
Short name T54
Test name
Test status
Simulation time 15223485560 ps
CPU time 110.05 seconds
Started Feb 29 12:54:00 PM PST 24
Finished Feb 29 12:55:50 PM PST 24
Peak memory 198228 kb
Host smart-e1599c49-7eb2-4ab7-9f1a-032c1515a150
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571084295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1571084295
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3977069484
Short name T333
Test name
Test status
Simulation time 68468097 ps
CPU time 0.65 seconds
Started Feb 29 12:52:59 PM PST 24
Finished Feb 29 12:53:00 PM PST 24
Peak memory 194812 kb
Host smart-d8fc344e-01ce-4c87-a422-faf4901157e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977069484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3977069484
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2815822303
Short name T712
Test name
Test status
Simulation time 81555575 ps
CPU time 0.83 seconds
Started Feb 29 12:52:56 PM PST 24
Finished Feb 29 12:52:58 PM PST 24
Peak memory 195332 kb
Host smart-7ad055a9-b59b-49eb-b1fe-49181082e4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815822303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2815822303
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2107727068
Short name T270
Test name
Test status
Simulation time 390517414 ps
CPU time 19.5 seconds
Started Feb 29 12:52:50 PM PST 24
Finished Feb 29 12:53:09 PM PST 24
Peak memory 197204 kb
Host smart-f875b6df-0aad-45b4-bb2f-4909ee1e4a58
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107727068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2107727068
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1596307992
Short name T294
Test name
Test status
Simulation time 25719058 ps
CPU time 0.65 seconds
Started Feb 29 12:53:13 PM PST 24
Finished Feb 29 12:53:14 PM PST 24
Peak memory 194580 kb
Host smart-60911d78-5b2b-474f-8514-db895ed1f2e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596307992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1596307992
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3374937154
Short name T599
Test name
Test status
Simulation time 27923162 ps
CPU time 0.82 seconds
Started Feb 29 12:52:56 PM PST 24
Finished Feb 29 12:52:58 PM PST 24
Peak memory 195516 kb
Host smart-02aec7d9-6603-492d-930b-5807cdfc2fb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374937154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3374937154
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3450214132
Short name T478
Test name
Test status
Simulation time 46172741 ps
CPU time 1.62 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 12:53:12 PM PST 24
Peak memory 196780 kb
Host smart-1ebdb128-f0c6-4e0f-adb7-04c82c4b4d2c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450214132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3450214132
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2430155879
Short name T319
Test name
Test status
Simulation time 162153520 ps
CPU time 1.07 seconds
Started Feb 29 12:53:05 PM PST 24
Finished Feb 29 12:53:06 PM PST 24
Peak memory 195712 kb
Host smart-6ca0a26b-b5c8-471d-b88d-a32220c8d3ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430155879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2430155879
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1951487030
Short name T575
Test name
Test status
Simulation time 41676516 ps
CPU time 0.87 seconds
Started Feb 29 12:53:05 PM PST 24
Finished Feb 29 12:53:06 PM PST 24
Peak memory 196652 kb
Host smart-69a2cfb4-790e-414f-b8ee-a99af0481ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951487030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1951487030
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1745400759
Short name T681
Test name
Test status
Simulation time 32717653 ps
CPU time 1.16 seconds
Started Feb 29 12:52:59 PM PST 24
Finished Feb 29 12:53:00 PM PST 24
Peak memory 195920 kb
Host smart-884b626c-8c97-4ff3-ae42-d9781003eb5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745400759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1745400759
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2552042204
Short name T8
Test name
Test status
Simulation time 3308255507 ps
CPU time 4.22 seconds
Started Feb 29 12:53:03 PM PST 24
Finished Feb 29 12:53:08 PM PST 24
Peak memory 198164 kb
Host smart-ccdae0ec-bec8-47d5-b4f6-1713b6796a47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552042204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2552042204
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3914267708
Short name T33
Test name
Test status
Simulation time 124846052 ps
CPU time 0.91 seconds
Started Feb 29 12:52:53 PM PST 24
Finished Feb 29 12:52:59 PM PST 24
Peak memory 213772 kb
Host smart-1c8755d8-8135-4bd6-8ce1-a72e8e4e6228
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914267708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3914267708
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3433521017
Short name T404
Test name
Test status
Simulation time 63807369 ps
CPU time 1.31 seconds
Started Feb 29 12:53:01 PM PST 24
Finished Feb 29 12:53:02 PM PST 24
Peak memory 197976 kb
Host smart-d5e0797d-b56f-4860-abb0-3cf55ee3fb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433521017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3433521017
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.874039030
Short name T269
Test name
Test status
Simulation time 967444687 ps
CPU time 1.38 seconds
Started Feb 29 12:53:05 PM PST 24
Finished Feb 29 12:53:06 PM PST 24
Peak memory 196876 kb
Host smart-017e4b7a-cc8a-4605-b3f4-5f0a4355c401
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874039030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.874039030
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1712304380
Short name T529
Test name
Test status
Simulation time 2230534011 ps
CPU time 35.06 seconds
Started Feb 29 12:52:57 PM PST 24
Finished Feb 29 12:53:32 PM PST 24
Peak memory 198180 kb
Host smart-a18e61fa-8d4e-45ab-a1b4-15e600bcf841
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712304380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1712304380
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.500197792
Short name T668
Test name
Test status
Simulation time 255145916778 ps
CPU time 1786.44 seconds
Started Feb 29 12:52:52 PM PST 24
Finished Feb 29 01:22:39 PM PST 24
Peak memory 198304 kb
Host smart-c6b7cbba-03ce-412c-9c54-5e72bbf87b7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=500197792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.500197792
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2466124282
Short name T358
Test name
Test status
Simulation time 20524122 ps
CPU time 0.59 seconds
Started Feb 29 12:54:03 PM PST 24
Finished Feb 29 12:54:05 PM PST 24
Peak memory 194604 kb
Host smart-93835310-4153-4cca-b1e8-936b67ccf7ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466124282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2466124282
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.723553156
Short name T600
Test name
Test status
Simulation time 48010940 ps
CPU time 0.87 seconds
Started Feb 29 12:54:03 PM PST 24
Finished Feb 29 12:54:05 PM PST 24
Peak memory 196360 kb
Host smart-238a4042-4105-4b8e-8d6d-96c02010764a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723553156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.723553156
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1421731655
Short name T314
Test name
Test status
Simulation time 1039684479 ps
CPU time 26.82 seconds
Started Feb 29 12:53:57 PM PST 24
Finished Feb 29 12:54:24 PM PST 24
Peak memory 195548 kb
Host smart-dcb7a435-48fe-4d87-b6d9-7d8e89ae18ec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421731655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1421731655
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2618675550
Short name T634
Test name
Test status
Simulation time 334362258 ps
CPU time 0.9 seconds
Started Feb 29 12:54:12 PM PST 24
Finished Feb 29 12:54:14 PM PST 24
Peak memory 197268 kb
Host smart-90952584-3768-42ed-b763-55fc38f40f81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618675550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2618675550
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3774823300
Short name T147
Test name
Test status
Simulation time 203404017 ps
CPU time 1.03 seconds
Started Feb 29 12:54:02 PM PST 24
Finished Feb 29 12:54:03 PM PST 24
Peak memory 196004 kb
Host smart-7c4fce9f-3439-47d3-a6c8-7cae049c5e80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774823300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3774823300
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.834429032
Short name T203
Test name
Test status
Simulation time 102605436 ps
CPU time 1.16 seconds
Started Feb 29 12:54:04 PM PST 24
Finished Feb 29 12:54:06 PM PST 24
Peak memory 197468 kb
Host smart-3a5e956a-829b-47ec-85f4-1857da723ae9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834429032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.834429032
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1925262162
Short name T205
Test name
Test status
Simulation time 65690314 ps
CPU time 1.09 seconds
Started Feb 29 12:54:24 PM PST 24
Finished Feb 29 12:54:26 PM PST 24
Peak memory 196856 kb
Host smart-352427e3-39e4-4ee6-99bb-ef7964f1422a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925262162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1925262162
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2209430700
Short name T559
Test name
Test status
Simulation time 31744299 ps
CPU time 1.27 seconds
Started Feb 29 12:54:07 PM PST 24
Finished Feb 29 12:54:08 PM PST 24
Peak memory 198080 kb
Host smart-cd759bda-2009-4398-a687-6e73f3564909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209430700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2209430700
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1576270054
Short name T355
Test name
Test status
Simulation time 57596049 ps
CPU time 1.12 seconds
Started Feb 29 12:54:03 PM PST 24
Finished Feb 29 12:54:05 PM PST 24
Peak memory 196708 kb
Host smart-86edc645-5fca-4a13-9f93-e43c02b893fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576270054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1576270054
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3416899650
Short name T691
Test name
Test status
Simulation time 369767997 ps
CPU time 6.07 seconds
Started Feb 29 12:54:05 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 198040 kb
Host smart-ed12a66d-260a-4720-a113-26ca5519d7e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416899650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3416899650
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1372714821
Short name T438
Test name
Test status
Simulation time 66422830 ps
CPU time 1.25 seconds
Started Feb 29 12:54:05 PM PST 24
Finished Feb 29 12:54:07 PM PST 24
Peak memory 196920 kb
Host smart-9bfe0cca-23d5-487f-bd75-cbf8074f76d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372714821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1372714821
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2165052836
Short name T335
Test name
Test status
Simulation time 28573530 ps
CPU time 0.87 seconds
Started Feb 29 12:54:09 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 195448 kb
Host smart-3f2113f2-3ef0-487c-a98b-f64783cea703
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165052836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2165052836
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2011346021
Short name T324
Test name
Test status
Simulation time 20681999111 ps
CPU time 78.08 seconds
Started Feb 29 12:54:02 PM PST 24
Finished Feb 29 12:55:20 PM PST 24
Peak memory 198228 kb
Host smart-a8f0a182-dc8f-4c4f-96dd-118cfd5f69a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011346021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2011346021
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.4250997234
Short name T670
Test name
Test status
Simulation time 45721717 ps
CPU time 0.57 seconds
Started Feb 29 12:53:54 PM PST 24
Finished Feb 29 12:53:55 PM PST 24
Peak memory 193876 kb
Host smart-4549251a-b5fd-4ef3-be71-804fa3023363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250997234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.4250997234
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3867330461
Short name T187
Test name
Test status
Simulation time 159786741 ps
CPU time 0.81 seconds
Started Feb 29 12:54:14 PM PST 24
Finished Feb 29 12:54:15 PM PST 24
Peak memory 195456 kb
Host smart-7a421122-b02c-42f1-ac1b-366543698ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867330461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3867330461
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.381401913
Short name T704
Test name
Test status
Simulation time 1557361082 ps
CPU time 19.11 seconds
Started Feb 29 12:53:59 PM PST 24
Finished Feb 29 12:54:18 PM PST 24
Peak memory 197060 kb
Host smart-29421bb9-1840-4570-9ab0-8bf8e88665aa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381401913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.381401913
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.366534070
Short name T166
Test name
Test status
Simulation time 51341444 ps
CPU time 0.81 seconds
Started Feb 29 12:54:05 PM PST 24
Finished Feb 29 12:54:06 PM PST 24
Peak memory 195988 kb
Host smart-e504fc5c-a620-41a6-8f38-aac02299971b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366534070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.366534070
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.841941911
Short name T306
Test name
Test status
Simulation time 413183710 ps
CPU time 1.09 seconds
Started Feb 29 12:54:04 PM PST 24
Finished Feb 29 12:54:06 PM PST 24
Peak memory 196736 kb
Host smart-5d0935a2-1975-45f1-ae04-011b1ee4c528
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841941911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.841941911
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3646104526
Short name T507
Test name
Test status
Simulation time 25686544 ps
CPU time 1.1 seconds
Started Feb 29 12:54:06 PM PST 24
Finished Feb 29 12:54:07 PM PST 24
Peak memory 197868 kb
Host smart-491706fe-f798-43ea-b96d-c90a3ffb5b95
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646104526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3646104526
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1795545561
Short name T500
Test name
Test status
Simulation time 195664786 ps
CPU time 1.87 seconds
Started Feb 29 12:54:11 PM PST 24
Finished Feb 29 12:54:23 PM PST 24
Peak memory 196152 kb
Host smart-542c31ea-6868-4480-86a2-92a3ec12f14a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795545561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1795545561
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3044504674
Short name T421
Test name
Test status
Simulation time 50911903 ps
CPU time 0.98 seconds
Started Feb 29 12:53:59 PM PST 24
Finished Feb 29 12:54:01 PM PST 24
Peak memory 196088 kb
Host smart-6f9ebe1c-46c3-4b28-a0c4-a613266255df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044504674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3044504674
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2895096364
Short name T192
Test name
Test status
Simulation time 23417945 ps
CPU time 0.62 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:09 PM PST 24
Peak memory 194304 kb
Host smart-82e153fd-1aa5-41e9-b630-8c974200a087
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895096364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2895096364
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.429744678
Short name T365
Test name
Test status
Simulation time 125042088 ps
CPU time 5.61 seconds
Started Feb 29 12:53:48 PM PST 24
Finished Feb 29 12:53:54 PM PST 24
Peak memory 198056 kb
Host smart-a218e8b0-a8be-424b-9f45-a01386f4b9f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429744678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.429744678
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.48193848
Short name T617
Test name
Test status
Simulation time 26270187 ps
CPU time 0.76 seconds
Started Feb 29 12:54:01 PM PST 24
Finished Feb 29 12:54:02 PM PST 24
Peak memory 195132 kb
Host smart-433b6be3-6a8f-4af5-8047-83a467fccd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48193848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.48193848
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3545107649
Short name T578
Test name
Test status
Simulation time 203507779 ps
CPU time 1.12 seconds
Started Feb 29 12:54:03 PM PST 24
Finished Feb 29 12:54:05 PM PST 24
Peak memory 195848 kb
Host smart-86ad8d6e-911e-4ad1-8182-829d7f647b86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545107649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3545107649
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1405753981
Short name T502
Test name
Test status
Simulation time 5911592665 ps
CPU time 64.58 seconds
Started Feb 29 12:54:05 PM PST 24
Finished Feb 29 12:55:10 PM PST 24
Peak memory 198156 kb
Host smart-422bb5d6-5081-46e3-98bc-ab745ba1463b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405753981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1405753981
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.677261507
Short name T407
Test name
Test status
Simulation time 329744472812 ps
CPU time 1710.63 seconds
Started Feb 29 12:54:02 PM PST 24
Finished Feb 29 01:22:34 PM PST 24
Peak memory 198328 kb
Host smart-99b5a6b5-6387-45db-88dc-7bd3927eb86b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=677261507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.677261507
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2878557567
Short name T463
Test name
Test status
Simulation time 13075999 ps
CPU time 0.58 seconds
Started Feb 29 12:53:50 PM PST 24
Finished Feb 29 12:53:51 PM PST 24
Peak memory 193816 kb
Host smart-d1fa02e7-509b-4ce5-85b3-f59aea78f96f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878557567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2878557567
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2794434217
Short name T596
Test name
Test status
Simulation time 36435830 ps
CPU time 0.8 seconds
Started Feb 29 12:54:18 PM PST 24
Finished Feb 29 12:54:19 PM PST 24
Peak memory 195968 kb
Host smart-d75a3cb1-c9f9-4887-9bda-891e967313dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794434217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2794434217
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.107286405
Short name T212
Test name
Test status
Simulation time 1804909915 ps
CPU time 14.82 seconds
Started Feb 29 12:53:58 PM PST 24
Finished Feb 29 12:54:13 PM PST 24
Peak memory 196332 kb
Host smart-4763ce0c-de17-4864-a197-f67a67ed6b61
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107286405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.107286405
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3654656324
Short name T543
Test name
Test status
Simulation time 322021421 ps
CPU time 0.81 seconds
Started Feb 29 12:54:15 PM PST 24
Finished Feb 29 12:54:17 PM PST 24
Peak memory 196648 kb
Host smart-9800cdea-3c6f-4c19-9936-93410862d240
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654656324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3654656324
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.508046414
Short name T272
Test name
Test status
Simulation time 86674130 ps
CPU time 0.71 seconds
Started Feb 29 12:53:59 PM PST 24
Finished Feb 29 12:54:01 PM PST 24
Peak memory 194320 kb
Host smart-ea7db023-879e-4391-b27f-fa043a0d49a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508046414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.508046414
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2541481008
Short name T339
Test name
Test status
Simulation time 50977390 ps
CPU time 1.83 seconds
Started Feb 29 12:54:00 PM PST 24
Finished Feb 29 12:54:02 PM PST 24
Peak memory 198068 kb
Host smart-07d06adc-4613-4d69-bbf9-69e184c2e2ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541481008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2541481008
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3941293729
Short name T656
Test name
Test status
Simulation time 107890148 ps
CPU time 2.22 seconds
Started Feb 29 12:54:03 PM PST 24
Finished Feb 29 12:54:07 PM PST 24
Peak memory 196212 kb
Host smart-4845376e-d623-4353-88bd-acab3983ef01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941293729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3941293729
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2492082328
Short name T628
Test name
Test status
Simulation time 64701533 ps
CPU time 1.21 seconds
Started Feb 29 12:54:04 PM PST 24
Finished Feb 29 12:54:06 PM PST 24
Peak memory 197100 kb
Host smart-3dc68c5c-7165-4021-8085-6a29c42610ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492082328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2492082328
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.4214656386
Short name T328
Test name
Test status
Simulation time 67524035 ps
CPU time 0.85 seconds
Started Feb 29 12:54:05 PM PST 24
Finished Feb 29 12:54:06 PM PST 24
Peak memory 196608 kb
Host smart-72f4a562-6dfd-4fd0-88fd-84c3654b5c55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214656386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.4214656386
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1981872385
Short name T271
Test name
Test status
Simulation time 202023887 ps
CPU time 3.5 seconds
Started Feb 29 12:54:03 PM PST 24
Finished Feb 29 12:54:06 PM PST 24
Peak memory 198052 kb
Host smart-bcd70d5d-67fc-4468-8bdc-1b7caab74bba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981872385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1981872385
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2986504052
Short name T150
Test name
Test status
Simulation time 307397525 ps
CPU time 0.94 seconds
Started Feb 29 12:54:16 PM PST 24
Finished Feb 29 12:54:17 PM PST 24
Peak memory 196524 kb
Host smart-dd9af1c3-140a-489b-aca3-3b5a18675044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986504052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2986504052
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1109658297
Short name T482
Test name
Test status
Simulation time 598799194 ps
CPU time 1.14 seconds
Started Feb 29 12:54:01 PM PST 24
Finished Feb 29 12:54:02 PM PST 24
Peak memory 195732 kb
Host smart-4827ce1b-d1ee-4f2b-a9aa-ecea45a92f5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109658297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1109658297
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.4176215650
Short name T556
Test name
Test status
Simulation time 130341946461 ps
CPU time 161.39 seconds
Started Feb 29 12:54:10 PM PST 24
Finished Feb 29 12:56:52 PM PST 24
Peak memory 198188 kb
Host smart-22781cba-dd61-46bc-b2f1-f0f5b4c6ab93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176215650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.4176215650
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2797415486
Short name T162
Test name
Test status
Simulation time 18665753 ps
CPU time 0.56 seconds
Started Feb 29 12:53:51 PM PST 24
Finished Feb 29 12:53:51 PM PST 24
Peak memory 194064 kb
Host smart-61ae9ca3-d33d-4b2f-870b-3467df653a83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797415486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2797415486
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2028510
Short name T301
Test name
Test status
Simulation time 59859833 ps
CPU time 0.99 seconds
Started Feb 29 12:54:03 PM PST 24
Finished Feb 29 12:54:05 PM PST 24
Peak memory 196772 kb
Host smart-a86829cb-d149-47ff-8a62-0cdd5a8f77a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2028510
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1987020225
Short name T611
Test name
Test status
Simulation time 818483446 ps
CPU time 19.47 seconds
Started Feb 29 12:53:54 PM PST 24
Finished Feb 29 12:54:14 PM PST 24
Peak memory 195636 kb
Host smart-3383ba3c-3c70-4abd-8839-b3523f475cfa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987020225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1987020225
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2357117424
Short name T675
Test name
Test status
Simulation time 184390103 ps
CPU time 0.83 seconds
Started Feb 29 12:54:05 PM PST 24
Finished Feb 29 12:54:07 PM PST 24
Peak memory 196624 kb
Host smart-9efaefb5-4e05-4af8-b735-d7baa30b50f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357117424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2357117424
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2136233912
Short name T601
Test name
Test status
Simulation time 116246236 ps
CPU time 1.19 seconds
Started Feb 29 12:53:56 PM PST 24
Finished Feb 29 12:53:57 PM PST 24
Peak memory 196056 kb
Host smart-6cedf942-2c84-43ef-9f63-fc17f0240b8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136233912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2136233912
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2450608895
Short name T340
Test name
Test status
Simulation time 67882487 ps
CPU time 2.65 seconds
Started Feb 29 12:54:07 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 198064 kb
Host smart-257e1ebf-b7aa-4646-bd26-b45c16df265c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450608895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2450608895
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.917402234
Short name T439
Test name
Test status
Simulation time 1848378802 ps
CPU time 2.79 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 196968 kb
Host smart-242a95de-ce8b-416b-b728-40d6b45c56ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917402234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
917402234
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3109805679
Short name T641
Test name
Test status
Simulation time 24059608 ps
CPU time 0.91 seconds
Started Feb 29 12:54:05 PM PST 24
Finished Feb 29 12:54:07 PM PST 24
Peak memory 195984 kb
Host smart-05c66825-32e3-4373-922b-e9493ac163e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109805679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3109805679
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1191237319
Short name T405
Test name
Test status
Simulation time 45937649 ps
CPU time 0.66 seconds
Started Feb 29 12:54:06 PM PST 24
Finished Feb 29 12:54:07 PM PST 24
Peak memory 194240 kb
Host smart-c2fca84e-4af8-4b14-9fa0-29cd0b454275
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191237319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1191237319
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.701708897
Short name T6
Test name
Test status
Simulation time 1825022003 ps
CPU time 5.31 seconds
Started Feb 29 12:54:00 PM PST 24
Finished Feb 29 12:54:05 PM PST 24
Peak memory 198052 kb
Host smart-d40868de-4573-472a-9e5a-4ff1016c9829
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701708897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.701708897
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3106972918
Short name T173
Test name
Test status
Simulation time 247106554 ps
CPU time 1.12 seconds
Started Feb 29 12:53:54 PM PST 24
Finished Feb 29 12:53:55 PM PST 24
Peak memory 195744 kb
Host smart-458e7785-ca8f-4899-82f3-df3dce285cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106972918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3106972918
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.4257372173
Short name T106
Test name
Test status
Simulation time 155854520 ps
CPU time 1.41 seconds
Started Feb 29 12:53:57 PM PST 24
Finished Feb 29 12:53:58 PM PST 24
Peak memory 196784 kb
Host smart-4643756f-fbca-4130-8720-6b8c98064ad8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257372173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.4257372173
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.484292879
Short name T232
Test name
Test status
Simulation time 47478274727 ps
CPU time 150.39 seconds
Started Feb 29 12:54:16 PM PST 24
Finished Feb 29 12:56:47 PM PST 24
Peak memory 198232 kb
Host smart-bfaf82e7-c25c-4519-bd7d-8637ec95d4ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484292879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.484292879
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.113205246
Short name T661
Test name
Test status
Simulation time 48231755 ps
CPU time 0.57 seconds
Started Feb 29 12:54:10 PM PST 24
Finished Feb 29 12:54:12 PM PST 24
Peak memory 193912 kb
Host smart-a89c0e21-8173-4b61-a83a-d8140a6a0a3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113205246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.113205246
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.708340969
Short name T630
Test name
Test status
Simulation time 176511724 ps
CPU time 0.93 seconds
Started Feb 29 12:53:59 PM PST 24
Finished Feb 29 12:54:01 PM PST 24
Peak memory 195980 kb
Host smart-0372f108-21e3-4101-8113-26bee50595ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708340969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.708340969
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1852375998
Short name T525
Test name
Test status
Simulation time 148695151 ps
CPU time 7.47 seconds
Started Feb 29 12:54:03 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 195628 kb
Host smart-3fe1c3a8-64aa-426d-b4b1-3184db4b0f69
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852375998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1852375998
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3889252068
Short name T284
Test name
Test status
Simulation time 238385457 ps
CPU time 0.96 seconds
Started Feb 29 12:54:00 PM PST 24
Finished Feb 29 12:54:01 PM PST 24
Peak memory 197228 kb
Host smart-4907707c-1ee8-48e3-8eec-5314a92a08e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889252068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3889252068
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1990317073
Short name T265
Test name
Test status
Simulation time 606189942 ps
CPU time 1.29 seconds
Started Feb 29 12:53:59 PM PST 24
Finished Feb 29 12:54:01 PM PST 24
Peak memory 197048 kb
Host smart-0272a5b5-45bc-4995-a1a2-cb6747b97c0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990317073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1990317073
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1461878254
Short name T487
Test name
Test status
Simulation time 61257862 ps
CPU time 2.44 seconds
Started Feb 29 12:54:05 PM PST 24
Finished Feb 29 12:54:08 PM PST 24
Peak memory 198104 kb
Host smart-c0349abe-072d-445a-9984-86654fa924c7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461878254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1461878254
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3619008387
Short name T167
Test name
Test status
Simulation time 224604767 ps
CPU time 1.35 seconds
Started Feb 29 12:54:07 PM PST 24
Finished Feb 29 12:54:09 PM PST 24
Peak memory 196540 kb
Host smart-4b5c452a-a576-4610-9ac2-d7848e160853
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619008387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3619008387
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1959814499
Short name T318
Test name
Test status
Simulation time 95469895 ps
CPU time 1.19 seconds
Started Feb 29 12:54:19 PM PST 24
Finished Feb 29 12:54:21 PM PST 24
Peak memory 198104 kb
Host smart-24e83265-5de2-496b-bf21-8f353b98a3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959814499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1959814499
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.281724298
Short name T715
Test name
Test status
Simulation time 43627546 ps
CPU time 0.95 seconds
Started Feb 29 12:53:51 PM PST 24
Finished Feb 29 12:53:53 PM PST 24
Peak memory 195948 kb
Host smart-46cf184d-151d-4606-b845-19e5aa4f23ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281724298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.281724298
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1770914295
Short name T702
Test name
Test status
Simulation time 66356072 ps
CPU time 1.37 seconds
Started Feb 29 12:54:01 PM PST 24
Finished Feb 29 12:54:03 PM PST 24
Peak memory 197996 kb
Host smart-5556cfdd-190b-4716-b724-e6d77f67ae00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770914295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1770914295
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3558094042
Short name T279
Test name
Test status
Simulation time 35959891 ps
CPU time 1.04 seconds
Started Feb 29 12:54:11 PM PST 24
Finished Feb 29 12:54:13 PM PST 24
Peak memory 196580 kb
Host smart-c9a10a17-40e8-4442-8067-589bb846dd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558094042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3558094042
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2336339542
Short name T488
Test name
Test status
Simulation time 73850103 ps
CPU time 1.15 seconds
Started Feb 29 12:54:04 PM PST 24
Finished Feb 29 12:54:06 PM PST 24
Peak memory 196512 kb
Host smart-fd06c6f7-3d89-484e-b2b8-f2bf732d8282
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336339542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2336339542
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2354342691
Short name T452
Test name
Test status
Simulation time 7529061378 ps
CPU time 191.84 seconds
Started Feb 29 12:53:51 PM PST 24
Finished Feb 29 12:57:04 PM PST 24
Peak memory 198088 kb
Host smart-8846e933-bb63-4eb7-b32a-0ccd413ee816
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354342691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2354342691
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2175749094
Short name T305
Test name
Test status
Simulation time 29992967 ps
CPU time 0.57 seconds
Started Feb 29 12:54:02 PM PST 24
Finished Feb 29 12:54:02 PM PST 24
Peak memory 193820 kb
Host smart-26adc23c-4ff4-49cf-a19c-6d0ac7c3c16a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175749094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2175749094
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.4015324157
Short name T625
Test name
Test status
Simulation time 43716859 ps
CPU time 0.63 seconds
Started Feb 29 12:53:59 PM PST 24
Finished Feb 29 12:54:01 PM PST 24
Peak memory 194816 kb
Host smart-9dd79ce4-709e-45c2-af61-be583469a7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015324157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.4015324157
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2663924067
Short name T227
Test name
Test status
Simulation time 253030236 ps
CPU time 12.05 seconds
Started Feb 29 12:54:10 PM PST 24
Finished Feb 29 12:54:22 PM PST 24
Peak memory 197304 kb
Host smart-e29fd885-011f-4b02-b491-b8b5939148fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663924067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2663924067
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.153838045
Short name T377
Test name
Test status
Simulation time 141044812 ps
CPU time 0.89 seconds
Started Feb 29 12:54:04 PM PST 24
Finished Feb 29 12:54:06 PM PST 24
Peak memory 197780 kb
Host smart-57e7ec63-e127-4d59-b8ab-d1413c311fbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153838045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.153838045
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2498657243
Short name T379
Test name
Test status
Simulation time 107767295 ps
CPU time 1.35 seconds
Started Feb 29 12:54:09 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 195860 kb
Host smart-8172762e-abe7-478a-86d4-56c831f02d93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498657243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2498657243
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3769838991
Short name T302
Test name
Test status
Simulation time 46623753 ps
CPU time 1.74 seconds
Started Feb 29 12:53:46 PM PST 24
Finished Feb 29 12:53:48 PM PST 24
Peak memory 196780 kb
Host smart-2e536416-f9f9-40d1-8ea3-ea4b44a098ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769838991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3769838991
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1715580943
Short name T367
Test name
Test status
Simulation time 44663465 ps
CPU time 1.18 seconds
Started Feb 29 12:54:20 PM PST 24
Finished Feb 29 12:54:22 PM PST 24
Peak memory 197228 kb
Host smart-9e3e3e20-d12e-4d21-8cda-6a6b976fa376
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715580943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1715580943
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1382241677
Short name T15
Test name
Test status
Simulation time 385413934 ps
CPU time 0.91 seconds
Started Feb 29 12:53:53 PM PST 24
Finished Feb 29 12:53:54 PM PST 24
Peak memory 196200 kb
Host smart-a9fa5148-ccf8-4bae-aad7-9e9941e22598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382241677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1382241677
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2153471153
Short name T412
Test name
Test status
Simulation time 34558632 ps
CPU time 0.92 seconds
Started Feb 29 12:53:53 PM PST 24
Finished Feb 29 12:53:54 PM PST 24
Peak memory 196612 kb
Host smart-3872ab38-4810-4181-9feb-5059cd6d9318
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153471153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2153471153
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2030738474
Short name T221
Test name
Test status
Simulation time 188056898 ps
CPU time 2.37 seconds
Started Feb 29 12:54:01 PM PST 24
Finished Feb 29 12:54:04 PM PST 24
Peak memory 198012 kb
Host smart-407161af-8546-490d-b66f-d97fa818fe95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030738474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2030738474
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3622930510
Short name T326
Test name
Test status
Simulation time 374480229 ps
CPU time 1.09 seconds
Started Feb 29 12:54:09 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 195480 kb
Host smart-85ee6df2-a6fa-4d33-8b7f-5cbbf483d8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622930510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3622930510
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3756733182
Short name T711
Test name
Test status
Simulation time 39220490 ps
CPU time 0.98 seconds
Started Feb 29 12:54:12 PM PST 24
Finished Feb 29 12:54:19 PM PST 24
Peak memory 195748 kb
Host smart-3c6508b6-65fa-4b23-b343-5d26e92e3bd6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756733182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3756733182
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2556422810
Short name T66
Test name
Test status
Simulation time 12654332020 ps
CPU time 86.55 seconds
Started Feb 29 12:54:19 PM PST 24
Finished Feb 29 12:55:46 PM PST 24
Peak memory 198208 kb
Host smart-c9121270-14d2-4dca-8b1b-b1ea4db56117
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556422810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2556422810
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.3254768215
Short name T635
Test name
Test status
Simulation time 362670981700 ps
CPU time 1806.57 seconds
Started Feb 29 12:54:22 PM PST 24
Finished Feb 29 01:24:29 PM PST 24
Peak memory 206568 kb
Host smart-1f0e5274-c577-45a5-bedf-a556decf6324
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3254768215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.3254768215
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1810461652
Short name T152
Test name
Test status
Simulation time 19545722 ps
CPU time 0.58 seconds
Started Feb 29 12:54:00 PM PST 24
Finished Feb 29 12:54:01 PM PST 24
Peak memory 194140 kb
Host smart-ad2e6b07-fabe-4546-86dc-fdbf7ede8212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810461652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1810461652
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2180560417
Short name T142
Test name
Test status
Simulation time 41031393 ps
CPU time 0.8 seconds
Started Feb 29 12:54:07 PM PST 24
Finished Feb 29 12:54:09 PM PST 24
Peak memory 195244 kb
Host smart-d20519a4-ded1-4123-a006-3e5190dc01c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180560417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2180560417
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.334388136
Short name T627
Test name
Test status
Simulation time 4098752746 ps
CPU time 17.15 seconds
Started Feb 29 12:54:09 PM PST 24
Finished Feb 29 12:54:27 PM PST 24
Peak memory 197068 kb
Host smart-909548e9-3886-4b52-b615-4e297b9ce52e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334388136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.334388136
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1800991110
Short name T258
Test name
Test status
Simulation time 69201546 ps
CPU time 0.98 seconds
Started Feb 29 12:54:01 PM PST 24
Finished Feb 29 12:54:02 PM PST 24
Peak memory 197684 kb
Host smart-55cc189f-394b-4114-b98b-4f106ba88197
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800991110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1800991110
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1350002207
Short name T394
Test name
Test status
Simulation time 285016677 ps
CPU time 1.04 seconds
Started Feb 29 12:54:15 PM PST 24
Finished Feb 29 12:54:16 PM PST 24
Peak memory 195796 kb
Host smart-333e2552-838c-4a8c-92c5-c36e54fffbf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350002207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1350002207
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.728060274
Short name T251
Test name
Test status
Simulation time 66662310 ps
CPU time 2.44 seconds
Started Feb 29 12:54:15 PM PST 24
Finished Feb 29 12:54:18 PM PST 24
Peak memory 198056 kb
Host smart-ad0bb605-3d0e-4c9e-977b-7ab66ed9233a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728060274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.728060274
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.422777928
Short name T348
Test name
Test status
Simulation time 57484765 ps
CPU time 1.33 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:54:16 PM PST 24
Peak memory 197592 kb
Host smart-0844ec91-094c-4589-bc8a-f7d5cc77ed48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422777928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
422777928
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.593222961
Short name T509
Test name
Test status
Simulation time 444214645 ps
CPU time 0.99 seconds
Started Feb 29 12:54:06 PM PST 24
Finished Feb 29 12:54:08 PM PST 24
Peak memory 195860 kb
Host smart-e7d29153-1306-45cd-b5fc-fb6820879e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593222961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.593222961
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.206741091
Short name T413
Test name
Test status
Simulation time 859616756 ps
CPU time 1.24 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 198052 kb
Host smart-679843d4-67dd-4c62-8d76-fd5467a457ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206741091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.206741091
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1367046498
Short name T264
Test name
Test status
Simulation time 63455231 ps
CPU time 2.8 seconds
Started Feb 29 12:54:12 PM PST 24
Finished Feb 29 12:54:21 PM PST 24
Peak memory 198152 kb
Host smart-498bcfe0-363d-4777-af29-d7b2f8dcb9b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367046498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1367046498
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.845262711
Short name T231
Test name
Test status
Simulation time 173130709 ps
CPU time 1.45 seconds
Started Feb 29 12:53:56 PM PST 24
Finished Feb 29 12:53:58 PM PST 24
Peak memory 196192 kb
Host smart-397a4039-d476-4f30-bfcb-c7828359d3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845262711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.845262711
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1164568681
Short name T371
Test name
Test status
Simulation time 35367743 ps
CPU time 1.07 seconds
Started Feb 29 12:54:12 PM PST 24
Finished Feb 29 12:54:13 PM PST 24
Peak memory 195852 kb
Host smart-744fc145-19e3-4d2f-a318-793e42ef3a37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164568681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1164568681
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3958151099
Short name T209
Test name
Test status
Simulation time 13231121698 ps
CPU time 180.06 seconds
Started Feb 29 12:53:52 PM PST 24
Finished Feb 29 12:56:52 PM PST 24
Peak memory 198192 kb
Host smart-15d143ae-c9bc-4aa8-8a71-802b71e08c80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958151099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3958151099
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.4263107037
Short name T28
Test name
Test status
Simulation time 243756090142 ps
CPU time 2088.26 seconds
Started Feb 29 12:54:01 PM PST 24
Finished Feb 29 01:28:50 PM PST 24
Peak memory 198312 kb
Host smart-d297424d-ca50-4e77-9d24-19c96b59db0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4263107037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.4263107037
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.434150914
Short name T603
Test name
Test status
Simulation time 32633355 ps
CPU time 0.61 seconds
Started Feb 29 12:53:56 PM PST 24
Finished Feb 29 12:53:57 PM PST 24
Peak memory 193888 kb
Host smart-5abbf552-d94c-43cf-9257-0ccada4a608b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434150914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.434150914
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.124826746
Short name T700
Test name
Test status
Simulation time 27822860 ps
CPU time 0.85 seconds
Started Feb 29 12:54:19 PM PST 24
Finished Feb 29 12:54:21 PM PST 24
Peak memory 197304 kb
Host smart-9e8bc8c3-0e1b-4e57-ae78-038816797845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124826746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.124826746
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2123544064
Short name T581
Test name
Test status
Simulation time 300576431 ps
CPU time 8.74 seconds
Started Feb 29 12:54:09 PM PST 24
Finished Feb 29 12:54:18 PM PST 24
Peak memory 196920 kb
Host smart-488fd37b-14d0-4341-b35a-1dbbfef0e6ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123544064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2123544064
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2388321410
Short name T709
Test name
Test status
Simulation time 127518192 ps
CPU time 0.62 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 195164 kb
Host smart-0b0ac829-581d-43c8-bb97-fb516f9ff706
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388321410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2388321410
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3397702331
Short name T354
Test name
Test status
Simulation time 250579662 ps
CPU time 1.06 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 196140 kb
Host smart-40c7f7a9-882c-406b-aefa-09d959171e2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397702331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3397702331
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1853564226
Short name T395
Test name
Test status
Simulation time 89242003 ps
CPU time 3.33 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 196284 kb
Host smart-7bdbb4dc-f7de-4d1d-a984-a1a32196dbd0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853564226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1853564226
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.800772328
Short name T375
Test name
Test status
Simulation time 174112031 ps
CPU time 2.15 seconds
Started Feb 29 12:54:06 PM PST 24
Finished Feb 29 12:54:08 PM PST 24
Peak memory 197348 kb
Host smart-d90204ea-5e86-4ff2-ab02-ba77fec2a474
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800772328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
800772328
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1438050655
Short name T638
Test name
Test status
Simulation time 134816526 ps
CPU time 1.27 seconds
Started Feb 29 12:54:30 PM PST 24
Finished Feb 29 12:54:32 PM PST 24
Peak memory 197132 kb
Host smart-c7af6a9f-9547-4958-8f37-f5c63da99fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438050655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1438050655
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2998062895
Short name T694
Test name
Test status
Simulation time 22934285 ps
CPU time 0.74 seconds
Started Feb 29 12:54:05 PM PST 24
Finished Feb 29 12:54:06 PM PST 24
Peak memory 195480 kb
Host smart-dfc320fa-50cd-46aa-a69f-fdbdfd413e54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998062895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2998062895
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3913779783
Short name T620
Test name
Test status
Simulation time 216414420 ps
CPU time 2.1 seconds
Started Feb 29 12:54:07 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 197968 kb
Host smart-5241c985-03d3-4330-a82c-3ca5ee69dc81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913779783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3913779783
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.474403637
Short name T356
Test name
Test status
Simulation time 236963755 ps
CPU time 1.3 seconds
Started Feb 29 12:54:12 PM PST 24
Finished Feb 29 12:54:19 PM PST 24
Peak memory 195836 kb
Host smart-93c15154-e22c-4aab-b4f1-95f8800124e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474403637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.474403637
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.270760836
Short name T138
Test name
Test status
Simulation time 92282040 ps
CPU time 1.16 seconds
Started Feb 29 12:54:03 PM PST 24
Finished Feb 29 12:54:06 PM PST 24
Peak memory 195796 kb
Host smart-b18c29c7-8421-41ef-88f4-72b04b130b70
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270760836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.270760836
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1068488946
Short name T547
Test name
Test status
Simulation time 21758620199 ps
CPU time 119.69 seconds
Started Feb 29 12:54:02 PM PST 24
Finished Feb 29 12:56:02 PM PST 24
Peak memory 198148 kb
Host smart-7497084c-2cac-45e1-8a56-2f06996c902d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068488946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1068488946
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3462901019
Short name T312
Test name
Test status
Simulation time 24537037 ps
CPU time 0.54 seconds
Started Feb 29 12:54:05 PM PST 24
Finished Feb 29 12:54:06 PM PST 24
Peak memory 193864 kb
Host smart-fe570d20-7abb-4150-89ff-49587d77e747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462901019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3462901019
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.747861312
Short name T597
Test name
Test status
Simulation time 60479918 ps
CPU time 0.66 seconds
Started Feb 29 12:54:10 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 194080 kb
Host smart-7af8a60a-febc-44dc-928d-14bfcfbc1e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747861312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.747861312
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1267382658
Short name T72
Test name
Test status
Simulation time 708973539 ps
CPU time 20.38 seconds
Started Feb 29 12:54:03 PM PST 24
Finished Feb 29 12:54:25 PM PST 24
Peak memory 196240 kb
Host smart-0f911625-2c75-47d4-bfdc-b375cc5f8432
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267382658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1267382658
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3410585614
Short name T336
Test name
Test status
Simulation time 60352203 ps
CPU time 0.88 seconds
Started Feb 29 12:53:54 PM PST 24
Finished Feb 29 12:53:55 PM PST 24
Peak memory 196956 kb
Host smart-f87a783b-90bd-46f4-9ad0-f4958998fe8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410585614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3410585614
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.291237907
Short name T414
Test name
Test status
Simulation time 36976033 ps
CPU time 1.02 seconds
Started Feb 29 12:54:12 PM PST 24
Finished Feb 29 12:54:13 PM PST 24
Peak memory 196096 kb
Host smart-9ef21c46-c160-4370-8aca-d4d7c65d4a2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291237907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.291237907
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3847209666
Short name T470
Test name
Test status
Simulation time 49722569 ps
CPU time 1.99 seconds
Started Feb 29 12:54:02 PM PST 24
Finished Feb 29 12:54:04 PM PST 24
Peak memory 198088 kb
Host smart-cabcde0c-365a-42fa-a548-014b0ba218ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847209666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3847209666
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3314144700
Short name T397
Test name
Test status
Simulation time 278229785 ps
CPU time 2.16 seconds
Started Feb 29 12:54:04 PM PST 24
Finished Feb 29 12:54:07 PM PST 24
Peak memory 196588 kb
Host smart-8fa69665-7f54-4943-a25c-7aee0dcc9ad8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314144700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3314144700
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3183276834
Short name T586
Test name
Test status
Simulation time 342643976 ps
CPU time 1.3 seconds
Started Feb 29 12:54:00 PM PST 24
Finished Feb 29 12:54:01 PM PST 24
Peak memory 197024 kb
Host smart-4f0ab5c9-bb00-4438-82c0-0efdd65efccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183276834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3183276834
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2245861743
Short name T248
Test name
Test status
Simulation time 31201566 ps
CPU time 1.17 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:54:15 PM PST 24
Peak memory 197204 kb
Host smart-d676ae4a-131e-4687-b557-183e113c12f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245861743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2245861743
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.498182412
Short name T552
Test name
Test status
Simulation time 1693208056 ps
CPU time 5.57 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:14 PM PST 24
Peak memory 198012 kb
Host smart-2e968134-7bb3-4291-bc09-550ce2f265a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498182412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.498182412
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1281287207
Short name T433
Test name
Test status
Simulation time 230069940 ps
CPU time 0.89 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:54:15 PM PST 24
Peak memory 195328 kb
Host smart-b0974737-6305-4790-a255-e3c3c83d9bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281287207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1281287207
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2516892858
Short name T451
Test name
Test status
Simulation time 266299580 ps
CPU time 0.85 seconds
Started Feb 29 12:54:20 PM PST 24
Finished Feb 29 12:54:22 PM PST 24
Peak memory 195244 kb
Host smart-3692b1a2-c5b4-4671-a024-dac2d9a930ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516892858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2516892858
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.4219926645
Short name T276
Test name
Test status
Simulation time 12435484765 ps
CPU time 152.86 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:56:47 PM PST 24
Peak memory 198388 kb
Host smart-e522ad59-fb54-492d-8d31-0db6c3721c0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219926645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.4219926645
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2417729595
Short name T473
Test name
Test status
Simulation time 10776056 ps
CPU time 0.59 seconds
Started Feb 29 12:54:09 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 193900 kb
Host smart-248f01e4-7441-4cc8-bd9f-3c41cb545eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417729595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2417729595
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2086231168
Short name T107
Test name
Test status
Simulation time 30666664 ps
CPU time 0.61 seconds
Started Feb 29 12:54:16 PM PST 24
Finished Feb 29 12:54:17 PM PST 24
Peak memory 194540 kb
Host smart-a76356af-a242-4e80-a26a-556310493198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086231168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2086231168
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.570140235
Short name T186
Test name
Test status
Simulation time 1378937043 ps
CPU time 9.4 seconds
Started Feb 29 12:54:12 PM PST 24
Finished Feb 29 12:54:22 PM PST 24
Peak memory 198076 kb
Host smart-09b5b76c-ed73-4be8-a704-899d45a36d50
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570140235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.570140235
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.736695277
Short name T366
Test name
Test status
Simulation time 450049721 ps
CPU time 0.8 seconds
Started Feb 29 12:53:59 PM PST 24
Finished Feb 29 12:54:00 PM PST 24
Peak memory 196872 kb
Host smart-a0ba8322-a934-4492-9d7b-b5619dbbe4fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736695277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.736695277
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3909627380
Short name T633
Test name
Test status
Simulation time 23412849 ps
CPU time 0.63 seconds
Started Feb 29 12:54:17 PM PST 24
Finished Feb 29 12:54:18 PM PST 24
Peak memory 194300 kb
Host smart-c723c7c7-c143-473c-9d07-802bec16bb5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909627380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3909627380
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.4244593520
Short name T623
Test name
Test status
Simulation time 41907067 ps
CPU time 1.6 seconds
Started Feb 29 12:54:10 PM PST 24
Finished Feb 29 12:54:13 PM PST 24
Peak memory 198176 kb
Host smart-0147ded9-f248-4e26-8b5e-c07203b5bd32
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244593520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.4244593520
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1423994572
Short name T123
Test name
Test status
Simulation time 102789536 ps
CPU time 2.96 seconds
Started Feb 29 12:54:05 PM PST 24
Finished Feb 29 12:54:08 PM PST 24
Peak memory 195852 kb
Host smart-72d5a4f5-c193-4876-8ddb-a0695b8819b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423994572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1423994572
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3745579171
Short name T126
Test name
Test status
Simulation time 52781818 ps
CPU time 0.99 seconds
Started Feb 29 12:54:05 PM PST 24
Finished Feb 29 12:54:06 PM PST 24
Peak memory 195872 kb
Host smart-9e6668f5-3b1d-43c0-8e23-1c956c9e2b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745579171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3745579171
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.692218026
Short name T121
Test name
Test status
Simulation time 51166065 ps
CPU time 1.13 seconds
Started Feb 29 12:54:02 PM PST 24
Finished Feb 29 12:54:03 PM PST 24
Peak memory 196604 kb
Host smart-44faa652-cb17-431b-9511-5cd290e9bc62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692218026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.692218026
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1492302789
Short name T110
Test name
Test status
Simulation time 1248216225 ps
CPU time 3.4 seconds
Started Feb 29 12:54:11 PM PST 24
Finished Feb 29 12:54:15 PM PST 24
Peak memory 198052 kb
Host smart-f5c591d6-022a-416c-af0c-a5a8d0bd01a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492302789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1492302789
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3012883811
Short name T511
Test name
Test status
Simulation time 37552251 ps
CPU time 0.91 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 197428 kb
Host smart-8b72792a-46bc-4a57-9a8a-90d03a2c635a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012883811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3012883811
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3621743849
Short name T645
Test name
Test status
Simulation time 36479921 ps
CPU time 0.9 seconds
Started Feb 29 12:54:20 PM PST 24
Finished Feb 29 12:54:21 PM PST 24
Peak memory 196448 kb
Host smart-93ced289-3d31-465f-8bc5-e7cb27583cfc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621743849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3621743849
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.67745269
Short name T434
Test name
Test status
Simulation time 30373279887 ps
CPU time 161.69 seconds
Started Feb 29 12:54:09 PM PST 24
Finished Feb 29 12:56:51 PM PST 24
Peak memory 198252 kb
Host smart-68a09a03-64cf-4500-99da-e135e731cdcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67745269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gp
io_stress_all.67745269
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.854149690
Short name T646
Test name
Test status
Simulation time 14852956 ps
CPU time 0.58 seconds
Started Feb 29 12:52:54 PM PST 24
Finished Feb 29 12:52:55 PM PST 24
Peak memory 194632 kb
Host smart-f1ef6f2d-8d40-410e-b612-3dfd2cea0a4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854149690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.854149690
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.622087748
Short name T201
Test name
Test status
Simulation time 18931111 ps
CPU time 0.7 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 12:53:12 PM PST 24
Peak memory 195872 kb
Host smart-2c13c87e-66fe-4bd1-960f-c28acc8d8604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622087748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.622087748
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.692991640
Short name T14
Test name
Test status
Simulation time 1043144490 ps
CPU time 25.14 seconds
Started Feb 29 12:52:59 PM PST 24
Finished Feb 29 12:53:24 PM PST 24
Peak memory 198092 kb
Host smart-cdf26659-c5cf-40d3-addd-fd41ad5f42d6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692991640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.692991640
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2229979477
Short name T113
Test name
Test status
Simulation time 826354704 ps
CPU time 0.84 seconds
Started Feb 29 12:52:56 PM PST 24
Finished Feb 29 12:52:58 PM PST 24
Peak memory 196872 kb
Host smart-1bca04bf-d367-4fda-b78f-d2ce92a9b424
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229979477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2229979477
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3034317911
Short name T233
Test name
Test status
Simulation time 170684298 ps
CPU time 0.99 seconds
Started Feb 29 12:52:51 PM PST 24
Finished Feb 29 12:52:52 PM PST 24
Peak memory 195868 kb
Host smart-605844ec-76c7-4567-819c-517cb6ed7c60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034317911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3034317911
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2709897697
Short name T406
Test name
Test status
Simulation time 184679939 ps
CPU time 3.81 seconds
Started Feb 29 12:52:57 PM PST 24
Finished Feb 29 12:53:01 PM PST 24
Peak memory 198132 kb
Host smart-826aef34-8566-4929-b30d-fdf688338fb3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709897697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2709897697
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3219548639
Short name T141
Test name
Test status
Simulation time 29902547 ps
CPU time 0.87 seconds
Started Feb 29 12:52:54 PM PST 24
Finished Feb 29 12:52:56 PM PST 24
Peak memory 195056 kb
Host smart-79160f81-3709-43eb-be73-21abdb1d4d7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219548639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3219548639
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2256709243
Short name T654
Test name
Test status
Simulation time 71863220 ps
CPU time 0.87 seconds
Started Feb 29 12:52:57 PM PST 24
Finished Feb 29 12:52:58 PM PST 24
Peak memory 196052 kb
Host smart-5834242d-f4dc-485e-b032-393b01cef511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256709243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2256709243
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.1867383255
Short name T190
Test name
Test status
Simulation time 43896159 ps
CPU time 0.68 seconds
Started Feb 29 12:53:12 PM PST 24
Finished Feb 29 12:53:18 PM PST 24
Peak memory 195420 kb
Host smart-b63bb50d-2df4-48df-8dfa-8d9b3928dff1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867383255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.1867383255
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1546415691
Short name T429
Test name
Test status
Simulation time 394136219 ps
CPU time 6.78 seconds
Started Feb 29 12:53:04 PM PST 24
Finished Feb 29 12:53:11 PM PST 24
Peak memory 198012 kb
Host smart-41e96c1f-c6bf-40e6-9716-c9c52ccb7868
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546415691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1546415691
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.181534307
Short name T46
Test name
Test status
Simulation time 65917892 ps
CPU time 0.77 seconds
Started Feb 29 12:53:12 PM PST 24
Finished Feb 29 12:53:13 PM PST 24
Peak memory 213784 kb
Host smart-0462b278-d354-4bb8-8fd0-0e9153487fc9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181534307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.181534307
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.4205493050
Short name T614
Test name
Test status
Simulation time 38526145 ps
CPU time 0.9 seconds
Started Feb 29 12:53:00 PM PST 24
Finished Feb 29 12:53:02 PM PST 24
Peak memory 196388 kb
Host smart-6590feeb-ce15-4477-9afd-6788eb071afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205493050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.4205493050
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3708855678
Short name T685
Test name
Test status
Simulation time 200964432 ps
CPU time 1.21 seconds
Started Feb 29 12:53:02 PM PST 24
Finished Feb 29 12:53:03 PM PST 24
Peak memory 195876 kb
Host smart-4107756e-b0c6-49ab-8cfc-d3cb4b338d1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708855678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3708855678
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3979834085
Short name T548
Test name
Test status
Simulation time 67811869293 ps
CPU time 184.4 seconds
Started Feb 29 12:53:06 PM PST 24
Finished Feb 29 12:56:10 PM PST 24
Peak memory 198192 kb
Host smart-190b2a18-8ea4-4aa0-8d2a-724f2999fca0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979834085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3979834085
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.261896486
Short name T280
Test name
Test status
Simulation time 12535575 ps
CPU time 0.57 seconds
Started Feb 29 12:54:10 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 193800 kb
Host smart-f789e5ff-7482-4d72-962e-65b66582081d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261896486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.261896486
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.18287707
Short name T360
Test name
Test status
Simulation time 296497298 ps
CPU time 0.83 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:54:14 PM PST 24
Peak memory 196576 kb
Host smart-f52c9f2b-3184-438d-9869-c3eeaf9cc745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18287707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.18287707
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1016941672
Short name T605
Test name
Test status
Simulation time 948170751 ps
CPU time 23.83 seconds
Started Feb 29 12:54:10 PM PST 24
Finished Feb 29 12:54:34 PM PST 24
Peak memory 197148 kb
Host smart-2f0c4774-b3f1-48da-9972-7a14991ff91c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016941672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1016941672
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3240641956
Short name T496
Test name
Test status
Simulation time 83106851 ps
CPU time 0.66 seconds
Started Feb 29 12:54:38 PM PST 24
Finished Feb 29 12:54:39 PM PST 24
Peak memory 194432 kb
Host smart-543ccd41-e2a3-47d7-a113-a923733ddb28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240641956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3240641956
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2138684590
Short name T191
Test name
Test status
Simulation time 77874287 ps
CPU time 0.84 seconds
Started Feb 29 12:54:11 PM PST 24
Finished Feb 29 12:54:13 PM PST 24
Peak memory 196904 kb
Host smart-a543d781-3402-4663-99d6-a3c446a72dfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138684590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2138684590
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2845508452
Short name T332
Test name
Test status
Simulation time 166859243 ps
CPU time 3.18 seconds
Started Feb 29 12:54:07 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 198108 kb
Host smart-9b0e73d3-9429-4842-a378-a75b3063342e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845508452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2845508452
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.85796916
Short name T503
Test name
Test status
Simulation time 808369984 ps
CPU time 1.51 seconds
Started Feb 29 12:54:11 PM PST 24
Finished Feb 29 12:54:13 PM PST 24
Peak memory 195988 kb
Host smart-abadfa96-b644-46a4-b379-9d78f36a9063
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85796916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.85796916
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1662163350
Short name T384
Test name
Test status
Simulation time 36894649 ps
CPU time 0.95 seconds
Started Feb 29 12:54:11 PM PST 24
Finished Feb 29 12:54:13 PM PST 24
Peak memory 196000 kb
Host smart-bfc7dcb3-3287-40ae-8104-8f5c2d3ce88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662163350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1662163350
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2545837508
Short name T602
Test name
Test status
Simulation time 62966977 ps
CPU time 1.28 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:09 PM PST 24
Peak memory 198180 kb
Host smart-056480b8-d509-4bef-8b5e-1eff36cfff51
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545837508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2545837508
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.733774345
Short name T49
Test name
Test status
Simulation time 405775353 ps
CPU time 6.42 seconds
Started Feb 29 12:54:11 PM PST 24
Finished Feb 29 12:54:19 PM PST 24
Peak memory 198036 kb
Host smart-983b9456-b542-412a-a14a-b483fca4866a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733774345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.733774345
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.543545212
Short name T154
Test name
Test status
Simulation time 648708554 ps
CPU time 1.39 seconds
Started Feb 29 12:54:14 PM PST 24
Finished Feb 29 12:54:16 PM PST 24
Peak memory 195604 kb
Host smart-fd931828-c742-4a12-ba4e-23d811dc5eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543545212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.543545212
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.871270691
Short name T220
Test name
Test status
Simulation time 117859781 ps
CPU time 1.1 seconds
Started Feb 29 12:54:10 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 195660 kb
Host smart-0b6ecc05-fb7d-46c9-90a5-46d8cdb24b07
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871270691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.871270691
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.203241749
Short name T137
Test name
Test status
Simulation time 36021542798 ps
CPU time 39 seconds
Started Feb 29 12:54:40 PM PST 24
Finished Feb 29 12:55:19 PM PST 24
Peak memory 198196 kb
Host smart-aa5aa8f9-ca38-49c5-83c6-d69fee297578
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203241749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.203241749
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2413395821
Short name T295
Test name
Test status
Simulation time 50082504 ps
CPU time 0.62 seconds
Started Feb 29 12:54:09 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 194816 kb
Host smart-de0426a4-f40f-4353-84ca-7a2a7c0a967d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413395821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2413395821
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1401889765
Short name T345
Test name
Test status
Simulation time 29076899 ps
CPU time 0.79 seconds
Started Feb 29 12:54:09 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 196152 kb
Host smart-1edd6a05-fa34-479e-9e6c-174f15123802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401889765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1401889765
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.970024139
Short name T140
Test name
Test status
Simulation time 7368619420 ps
CPU time 15.65 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:54:29 PM PST 24
Peak memory 196660 kb
Host smart-62a2ff50-7d62-498d-9a4f-396ba69c651d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970024139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.970024139
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3164985098
Short name T477
Test name
Test status
Simulation time 127409466 ps
CPU time 0.89 seconds
Started Feb 29 12:54:22 PM PST 24
Finished Feb 29 12:54:24 PM PST 24
Peak memory 197676 kb
Host smart-fec7b7e5-1744-48f2-9cab-bb024e81866b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164985098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3164985098
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3240483893
Short name T640
Test name
Test status
Simulation time 31945975 ps
CPU time 0.94 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 195784 kb
Host smart-a18bda21-64c3-43e5-9f01-37543b6d474d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240483893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3240483893
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2679643401
Short name T197
Test name
Test status
Simulation time 57615167 ps
CPU time 1.22 seconds
Started Feb 29 12:54:20 PM PST 24
Finished Feb 29 12:54:22 PM PST 24
Peak memory 196528 kb
Host smart-cf865992-eb60-4ed0-abcf-5039f9a275f3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679643401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2679643401
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.319307515
Short name T613
Test name
Test status
Simulation time 82289134 ps
CPU time 2.29 seconds
Started Feb 29 12:54:11 PM PST 24
Finished Feb 29 12:54:14 PM PST 24
Peak memory 196780 kb
Host smart-896bcc49-c7bb-4be9-b18a-22a639ec6474
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319307515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
319307515
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3312030367
Short name T528
Test name
Test status
Simulation time 96614013 ps
CPU time 0.86 seconds
Started Feb 29 12:54:36 PM PST 24
Finished Feb 29 12:54:37 PM PST 24
Peak memory 196632 kb
Host smart-8fa9f62c-e211-47e1-9276-1a6f04648eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312030367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3312030367
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.434460716
Short name T506
Test name
Test status
Simulation time 57186453 ps
CPU time 0.74 seconds
Started Feb 29 12:54:03 PM PST 24
Finished Feb 29 12:54:05 PM PST 24
Peak memory 195376 kb
Host smart-13565316-7299-4319-b80f-2cbeebf3615b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434460716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.434460716
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.472226995
Short name T25
Test name
Test status
Simulation time 342074352 ps
CPU time 2.33 seconds
Started Feb 29 12:54:15 PM PST 24
Finished Feb 29 12:54:17 PM PST 24
Peak memory 198048 kb
Host smart-7863dbab-ea9f-4be7-b669-49a06b324367
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472226995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.472226995
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1647783558
Short name T448
Test name
Test status
Simulation time 110453151 ps
CPU time 1.53 seconds
Started Feb 29 12:54:17 PM PST 24
Finished Feb 29 12:54:19 PM PST 24
Peak memory 195672 kb
Host smart-305862e9-4da3-4ff2-96cc-2a4863c2523a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647783558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1647783558
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.4227611319
Short name T632
Test name
Test status
Simulation time 46736531 ps
CPU time 1.27 seconds
Started Feb 29 12:54:18 PM PST 24
Finished Feb 29 12:54:20 PM PST 24
Peak memory 198104 kb
Host smart-b5c8b04e-3d50-449e-aa08-68bfa8148d3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227611319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.4227611319
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.228445043
Short name T171
Test name
Test status
Simulation time 13211238229 ps
CPU time 183.72 seconds
Started Feb 29 12:54:11 PM PST 24
Finished Feb 29 12:57:16 PM PST 24
Peak memory 198232 kb
Host smart-afd35e2d-aeb1-4beb-b653-f35042dc9a36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228445043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.228445043
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.878231840
Short name T257
Test name
Test status
Simulation time 16107053 ps
CPU time 0.6 seconds
Started Feb 29 12:54:04 PM PST 24
Finished Feb 29 12:54:05 PM PST 24
Peak memory 194052 kb
Host smart-4bfa3c85-8fff-43c3-9cdd-8f9ffafb5e31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878231840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.878231840
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.108356386
Short name T230
Test name
Test status
Simulation time 32686070 ps
CPU time 0.74 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:54:15 PM PST 24
Peak memory 196084 kb
Host smart-5a445283-abd1-463b-90a2-ea51df6b1a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108356386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.108356386
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2459830731
Short name T331
Test name
Test status
Simulation time 4945663509 ps
CPU time 14.89 seconds
Started Feb 29 12:54:54 PM PST 24
Finished Feb 29 12:55:09 PM PST 24
Peak memory 198220 kb
Host smart-eca79483-dc81-4b60-8049-63c6a3114d5a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459830731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2459830731
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3019302409
Short name T3
Test name
Test status
Simulation time 79100873 ps
CPU time 0.92 seconds
Started Feb 29 12:54:18 PM PST 24
Finished Feb 29 12:54:19 PM PST 24
Peak memory 197276 kb
Host smart-db7b841f-14fc-4d22-9f99-fdc42fa449d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019302409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3019302409
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1645175056
Short name T164
Test name
Test status
Simulation time 437431953 ps
CPU time 1.47 seconds
Started Feb 29 12:54:09 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 197060 kb
Host smart-84af344c-9ce1-42dc-9798-18cd7e92d7a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645175056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1645175056
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.258260843
Short name T717
Test name
Test status
Simulation time 282854986 ps
CPU time 2.88 seconds
Started Feb 29 12:54:30 PM PST 24
Finished Feb 29 12:54:33 PM PST 24
Peak memory 198032 kb
Host smart-68e0cb7d-201d-4399-864a-e79214212476
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258260843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.258260843
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1112108012
Short name T693
Test name
Test status
Simulation time 1594955142 ps
CPU time 3.16 seconds
Started Feb 29 12:54:20 PM PST 24
Finished Feb 29 12:54:24 PM PST 24
Peak memory 196608 kb
Host smart-b02580ad-d362-40e6-8252-8dba0c6948df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112108012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1112108012
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3887911718
Short name T577
Test name
Test status
Simulation time 79347965 ps
CPU time 0.89 seconds
Started Feb 29 12:54:26 PM PST 24
Finished Feb 29 12:54:27 PM PST 24
Peak memory 195864 kb
Host smart-36243943-0734-47a2-8869-7f5a3323cc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887911718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3887911718
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3012942927
Short name T111
Test name
Test status
Simulation time 412319871 ps
CPU time 1.14 seconds
Started Feb 29 12:54:26 PM PST 24
Finished Feb 29 12:54:27 PM PST 24
Peak memory 196076 kb
Host smart-9fc6aa97-b00d-453c-a95b-4cd26af1a2af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012942927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3012942927
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1303426106
Short name T1
Test name
Test status
Simulation time 91731417 ps
CPU time 1.43 seconds
Started Feb 29 12:54:07 PM PST 24
Finished Feb 29 12:54:09 PM PST 24
Peak memory 198056 kb
Host smart-37dce807-4b9b-40cc-9b71-63cb3d80dbeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303426106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1303426106
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1413857453
Short name T47
Test name
Test status
Simulation time 92213946 ps
CPU time 0.87 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:54:15 PM PST 24
Peak memory 196088 kb
Host smart-d91ec505-35a5-4426-bc7f-c8d6a03c246e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413857453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1413857453
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3132823321
Short name T11
Test name
Test status
Simulation time 187932049 ps
CPU time 1.03 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 195604 kb
Host smart-4512f7ae-e4dc-4cb3-bc4c-729ba9f8a04a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132823321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3132823321
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1468577933
Short name T539
Test name
Test status
Simulation time 9975320893 ps
CPU time 127.83 seconds
Started Feb 29 12:54:04 PM PST 24
Finished Feb 29 12:56:13 PM PST 24
Peak memory 198088 kb
Host smart-f8dc0843-4e75-426e-8549-7618d64ab822
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468577933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1468577933
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3164111265
Short name T474
Test name
Test status
Simulation time 13044027 ps
CPU time 0.56 seconds
Started Feb 29 12:54:18 PM PST 24
Finished Feb 29 12:54:20 PM PST 24
Peak memory 194612 kb
Host smart-831fcaf7-fcf8-40d9-9c59-231991399c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164111265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3164111265
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2365382310
Short name T698
Test name
Test status
Simulation time 38210980 ps
CPU time 0.74 seconds
Started Feb 29 12:54:19 PM PST 24
Finished Feb 29 12:54:21 PM PST 24
Peak memory 196020 kb
Host smart-460f452d-5231-4413-8759-e4a73e10e9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365382310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2365382310
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2502451281
Short name T174
Test name
Test status
Simulation time 492277181 ps
CPU time 3.44 seconds
Started Feb 29 12:54:04 PM PST 24
Finished Feb 29 12:54:08 PM PST 24
Peak memory 196028 kb
Host smart-f51a8b7a-69f3-4bf7-af09-576852483964
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502451281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2502451281
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2040074069
Short name T649
Test name
Test status
Simulation time 129367409 ps
CPU time 1.03 seconds
Started Feb 29 12:54:32 PM PST 24
Finished Feb 29 12:54:33 PM PST 24
Peak memory 197104 kb
Host smart-794702f6-5e6e-4b1a-a6ef-3c902aeb3d52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040074069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2040074069
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2157967704
Short name T69
Test name
Test status
Simulation time 233962868 ps
CPU time 0.96 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:54:14 PM PST 24
Peak memory 196708 kb
Host smart-f80ed0e9-7c1d-4674-a3d6-594362898078
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157967704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2157967704
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3861074612
Short name T697
Test name
Test status
Simulation time 151460179 ps
CPU time 1.09 seconds
Started Feb 29 12:54:26 PM PST 24
Finished Feb 29 12:54:27 PM PST 24
Peak memory 197312 kb
Host smart-871a60b7-d783-4dff-a0dc-754b96151e01
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861074612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3861074612
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3361503640
Short name T442
Test name
Test status
Simulation time 193284523 ps
CPU time 2.29 seconds
Started Feb 29 12:54:07 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 197076 kb
Host smart-bdf1bf5f-55de-40a9-ab7d-3d05be8572b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361503640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3361503640
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.914730168
Short name T663
Test name
Test status
Simulation time 393691667 ps
CPU time 0.95 seconds
Started Feb 29 12:54:18 PM PST 24
Finished Feb 29 12:54:20 PM PST 24
Peak memory 195908 kb
Host smart-ff1d4036-7afa-40ca-92e7-14ef2500d210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914730168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.914730168
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.128439975
Short name T419
Test name
Test status
Simulation time 30641771 ps
CPU time 1.01 seconds
Started Feb 29 12:54:14 PM PST 24
Finished Feb 29 12:54:15 PM PST 24
Peak memory 195876 kb
Host smart-d163393a-5bf1-4a1b-a317-46c66b1ffb56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128439975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.128439975
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3611532865
Short name T309
Test name
Test status
Simulation time 95762401 ps
CPU time 2.39 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:54:16 PM PST 24
Peak memory 198132 kb
Host smart-f8b282c2-82c7-4fb1-983e-640ef4da7489
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611532865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3611532865
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2684602237
Short name T153
Test name
Test status
Simulation time 52855930 ps
CPU time 1.33 seconds
Started Feb 29 12:54:18 PM PST 24
Finished Feb 29 12:54:20 PM PST 24
Peak memory 196884 kb
Host smart-6ee2c6bd-6998-4568-b116-fc26e70bb401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684602237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2684602237
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3477591752
Short name T112
Test name
Test status
Simulation time 304344601 ps
CPU time 1.07 seconds
Started Feb 29 12:54:17 PM PST 24
Finished Feb 29 12:54:18 PM PST 24
Peak memory 195808 kb
Host smart-75e6b6ba-4c94-44c3-9668-212e32d5152c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477591752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3477591752
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2874522247
Short name T560
Test name
Test status
Simulation time 29805329316 ps
CPU time 200.31 seconds
Started Feb 29 12:54:26 PM PST 24
Finished Feb 29 12:57:46 PM PST 24
Peak memory 198144 kb
Host smart-10960316-425f-4155-bfa5-c2312a78b946
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874522247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2874522247
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.1559681925
Short name T27
Test name
Test status
Simulation time 478068205404 ps
CPU time 859.94 seconds
Started Feb 29 12:54:27 PM PST 24
Finished Feb 29 01:08:47 PM PST 24
Peak memory 198376 kb
Host smart-1db7eac1-b7a5-42b4-807f-8ee147a6fb1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1559681925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.1559681925
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2648413468
Short name T648
Test name
Test status
Simulation time 40468358 ps
CPU time 0.57 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:54:14 PM PST 24
Peak memory 194060 kb
Host smart-72645a79-4679-4169-84e8-84ebd5760421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648413468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2648413468
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3192418614
Short name T239
Test name
Test status
Simulation time 68090918 ps
CPU time 0.71 seconds
Started Feb 29 12:54:23 PM PST 24
Finished Feb 29 12:54:24 PM PST 24
Peak memory 195304 kb
Host smart-cacbf4a5-6818-416f-a935-4c4e6d9a69a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192418614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3192418614
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.7387845
Short name T574
Test name
Test status
Simulation time 975888421 ps
CPU time 11.7 seconds
Started Feb 29 12:54:22 PM PST 24
Finished Feb 29 12:54:35 PM PST 24
Peak memory 198144 kb
Host smart-522a936e-536b-463b-b631-22e24ed540da
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7387845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stress.7387845
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.4150412877
Short name T450
Test name
Test status
Simulation time 241822251 ps
CPU time 1.01 seconds
Started Feb 29 12:54:34 PM PST 24
Finished Feb 29 12:54:36 PM PST 24
Peak memory 197820 kb
Host smart-08ef3742-bd70-47c6-99ac-db33703eae83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150412877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.4150412877
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.632638920
Short name T569
Test name
Test status
Simulation time 295626938 ps
CPU time 1.27 seconds
Started Feb 29 12:54:28 PM PST 24
Finished Feb 29 12:54:30 PM PST 24
Peak memory 196848 kb
Host smart-bbb6a9f2-0f12-4c7f-9a6f-ba8e88ebddbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632638920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.632638920
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3100971651
Short name T259
Test name
Test status
Simulation time 179801860 ps
CPU time 2.05 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:54:16 PM PST 24
Peak memory 198140 kb
Host smart-b17f6015-d86b-4bcf-bee3-ccda9761a92d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100971651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3100971651
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1619376894
Short name T359
Test name
Test status
Simulation time 46112305 ps
CPU time 1.44 seconds
Started Feb 29 12:54:21 PM PST 24
Finished Feb 29 12:54:23 PM PST 24
Peak memory 196828 kb
Host smart-9a7044bc-d3d3-446c-95cb-c7ea9e936b61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619376894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1619376894
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.4205851588
Short name T465
Test name
Test status
Simulation time 35251650 ps
CPU time 1.22 seconds
Started Feb 29 12:54:18 PM PST 24
Finished Feb 29 12:54:19 PM PST 24
Peak memory 197056 kb
Host smart-b2851c19-51ed-4482-9665-d8f2920d2041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205851588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.4205851588
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.681564164
Short name T674
Test name
Test status
Simulation time 92891853 ps
CPU time 0.97 seconds
Started Feb 29 12:54:06 PM PST 24
Finished Feb 29 12:54:08 PM PST 24
Peak memory 196028 kb
Host smart-7006a571-1f9f-4313-b3c2-3050e8a7cfee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681564164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.681564164
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.220803119
Short name T454
Test name
Test status
Simulation time 321035220 ps
CPU time 4.46 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:18 PM PST 24
Peak memory 197972 kb
Host smart-4c921dee-790d-4a82-bd80-295fda278c49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220803119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.220803119
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3361955226
Short name T459
Test name
Test status
Simulation time 63247287 ps
CPU time 1.25 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 196744 kb
Host smart-c9a970d5-dba5-4555-bd7c-26ed43f89e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361955226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3361955226
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.328621305
Short name T208
Test name
Test status
Simulation time 160100913 ps
CPU time 0.83 seconds
Started Feb 29 12:54:11 PM PST 24
Finished Feb 29 12:54:13 PM PST 24
Peak memory 196844 kb
Host smart-da026fd3-0b9a-4f74-985b-175c81f313fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328621305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.328621305
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.4278852175
Short name T262
Test name
Test status
Simulation time 11343357762 ps
CPU time 57.79 seconds
Started Feb 29 12:54:32 PM PST 24
Finished Feb 29 12:55:30 PM PST 24
Peak memory 198200 kb
Host smart-599a8318-471a-48c4-beb3-4119fa78c79f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278852175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.4278852175
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1659449885
Short name T555
Test name
Test status
Simulation time 36417167 ps
CPU time 0.57 seconds
Started Feb 29 12:54:11 PM PST 24
Finished Feb 29 12:54:12 PM PST 24
Peak memory 194628 kb
Host smart-4b09607d-b85b-4bda-a836-b84cc8386ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659449885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1659449885
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2699952657
Short name T538
Test name
Test status
Simulation time 148822957 ps
CPU time 0.71 seconds
Started Feb 29 12:54:09 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 195148 kb
Host smart-ec731341-d0e8-4597-a73a-6235d3890b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699952657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2699952657
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1895359291
Short name T76
Test name
Test status
Simulation time 1002450517 ps
CPU time 23.7 seconds
Started Feb 29 12:54:16 PM PST 24
Finished Feb 29 12:54:40 PM PST 24
Peak memory 196860 kb
Host smart-1df2c29c-7092-479b-95b3-45472f8e01fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895359291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1895359291
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2358810399
Short name T570
Test name
Test status
Simulation time 81980083 ps
CPU time 0.77 seconds
Started Feb 29 12:54:11 PM PST 24
Finished Feb 29 12:54:13 PM PST 24
Peak memory 195864 kb
Host smart-61007017-8b72-4390-8134-e06cb2251625
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358810399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2358810399
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.4111298325
Short name T526
Test name
Test status
Simulation time 30757200 ps
CPU time 0.97 seconds
Started Feb 29 12:54:10 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 196876 kb
Host smart-dcefba4a-c489-4afc-9c5a-177e7f24e7aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111298325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.4111298325
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3669762430
Short name T622
Test name
Test status
Simulation time 48185940 ps
CPU time 1.09 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 196776 kb
Host smart-5796c82d-c13e-46c4-a485-03e29999d2c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669762430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3669762430
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.478341636
Short name T151
Test name
Test status
Simulation time 497541641 ps
CPU time 2.55 seconds
Started Feb 29 12:54:09 PM PST 24
Finished Feb 29 12:54:12 PM PST 24
Peak memory 195856 kb
Host smart-93886082-aaa1-4a5f-aac3-0db217c555cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478341636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
478341636
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1956582127
Short name T343
Test name
Test status
Simulation time 35606491 ps
CPU time 1.26 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 198172 kb
Host smart-fcb56552-dc81-4a94-b4aa-c1e6d65d5f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956582127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1956582127
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2810009959
Short name T24
Test name
Test status
Simulation time 40866430 ps
CPU time 1.01 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 195892 kb
Host smart-8aea7348-df43-4933-b96b-07de07ca09f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810009959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2810009959
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1633493374
Short name T385
Test name
Test status
Simulation time 303686368 ps
CPU time 3.63 seconds
Started Feb 29 12:54:06 PM PST 24
Finished Feb 29 12:54:09 PM PST 24
Peak memory 198012 kb
Host smart-3e0f62c8-067f-4b0a-a4dd-cb3ba2c814a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633493374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1633493374
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.934518695
Short name T510
Test name
Test status
Simulation time 123960050 ps
CPU time 1.26 seconds
Started Feb 29 12:54:24 PM PST 24
Finished Feb 29 12:54:26 PM PST 24
Peak memory 196912 kb
Host smart-3c58cd33-d485-4518-9467-7578471183d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934518695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.934518695
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1300553838
Short name T131
Test name
Test status
Simulation time 39382396 ps
CPU time 0.86 seconds
Started Feb 29 12:54:10 PM PST 24
Finished Feb 29 12:54:11 PM PST 24
Peak memory 195124 kb
Host smart-b0f4eae2-9198-4d9d-80bb-310741058a5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300553838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1300553838
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.87051075
Short name T535
Test name
Test status
Simulation time 2294337272 ps
CPU time 32.65 seconds
Started Feb 29 12:54:19 PM PST 24
Finished Feb 29 12:54:52 PM PST 24
Peak memory 198188 kb
Host smart-45fc6f66-796d-4ab5-a565-8198c3630645
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87051075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gp
io_stress_all.87051075
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.539512696
Short name T530
Test name
Test status
Simulation time 116387385793 ps
CPU time 357.81 seconds
Started Feb 29 12:54:41 PM PST 24
Finished Feb 29 01:00:39 PM PST 24
Peak memory 198332 kb
Host smart-bfee8840-5c96-44fe-a20e-8c7eaac12104
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=539512696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.539512696
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.217364199
Short name T683
Test name
Test status
Simulation time 11505497 ps
CPU time 0.58 seconds
Started Feb 29 12:54:09 PM PST 24
Finished Feb 29 12:54:10 PM PST 24
Peak memory 193912 kb
Host smart-8d289948-6e0c-43ed-994e-0c8034abc977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217364199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.217364199
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3976779308
Short name T491
Test name
Test status
Simulation time 30700557 ps
CPU time 0.78 seconds
Started Feb 29 12:54:32 PM PST 24
Finished Feb 29 12:54:33 PM PST 24
Peak memory 196004 kb
Host smart-a1be5140-1d77-4c4d-9e7a-ea2b2c6b712c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976779308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3976779308
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3538360122
Short name T383
Test name
Test status
Simulation time 3350413528 ps
CPU time 25.38 seconds
Started Feb 29 12:54:28 PM PST 24
Finished Feb 29 12:54:53 PM PST 24
Peak memory 196788 kb
Host smart-542ad39c-2b6d-4815-a130-e5e9e9757319
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538360122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3538360122
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3779853540
Short name T572
Test name
Test status
Simulation time 76388522 ps
CPU time 0.76 seconds
Started Feb 29 12:54:17 PM PST 24
Finished Feb 29 12:54:18 PM PST 24
Peak memory 196808 kb
Host smart-41144781-f021-4c24-98c5-b0796177adc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779853540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3779853540
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2609128138
Short name T134
Test name
Test status
Simulation time 76929048 ps
CPU time 0.71 seconds
Started Feb 29 12:54:35 PM PST 24
Finished Feb 29 12:54:36 PM PST 24
Peak memory 194496 kb
Host smart-b4c7f32e-d731-43f4-b725-44b36131fd68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609128138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2609128138
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.118214223
Short name T396
Test name
Test status
Simulation time 31846010 ps
CPU time 1.22 seconds
Started Feb 29 12:54:29 PM PST 24
Finished Feb 29 12:54:31 PM PST 24
Peak memory 198052 kb
Host smart-e034864f-15f8-488d-8aa2-e45c8dfe54fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118214223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.118214223
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3501142584
Short name T225
Test name
Test status
Simulation time 105312077 ps
CPU time 3.08 seconds
Started Feb 29 12:54:16 PM PST 24
Finished Feb 29 12:54:20 PM PST 24
Peak memory 197152 kb
Host smart-8722065e-315f-4cd4-a543-7bebe105a5c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501142584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3501142584
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2895811315
Short name T229
Test name
Test status
Simulation time 23890991 ps
CPU time 0.65 seconds
Started Feb 29 12:54:40 PM PST 24
Finished Feb 29 12:54:41 PM PST 24
Peak memory 194324 kb
Host smart-3f041bf3-c64a-4643-a614-2238096246df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895811315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2895811315
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2874996451
Short name T236
Test name
Test status
Simulation time 59751768 ps
CPU time 1.31 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:54:15 PM PST 24
Peak memory 196572 kb
Host smart-988a8be9-1188-4d5c-bb58-406c4791d337
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874996451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2874996451
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3922964270
Short name T604
Test name
Test status
Simulation time 452918732 ps
CPU time 4.54 seconds
Started Feb 29 12:54:09 PM PST 24
Finished Feb 29 12:54:15 PM PST 24
Peak memory 198024 kb
Host smart-87a94768-04fa-4d1f-87b8-a2c5b9eabe1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922964270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3922964270
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.305532707
Short name T567
Test name
Test status
Simulation time 241331528 ps
CPU time 1.2 seconds
Started Feb 29 12:54:08 PM PST 24
Finished Feb 29 12:54:09 PM PST 24
Peak memory 196568 kb
Host smart-86257e4c-a5dd-4757-916f-b95bd0dedb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305532707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.305532707
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.4126060967
Short name T170
Test name
Test status
Simulation time 64991339 ps
CPU time 1.18 seconds
Started Feb 29 12:54:12 PM PST 24
Finished Feb 29 12:54:18 PM PST 24
Peak memory 196528 kb
Host smart-36a91186-c80d-4e05-923a-895c1aa0e065
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126060967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.4126060967
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1628290621
Short name T590
Test name
Test status
Simulation time 8840322824 ps
CPU time 102.32 seconds
Started Feb 29 12:54:12 PM PST 24
Finished Feb 29 12:55:55 PM PST 24
Peak memory 198136 kb
Host smart-498c8ffb-9ec0-44fd-aaed-fd3037e03aad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628290621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1628290621
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3221495037
Short name T62
Test name
Test status
Simulation time 51205049048 ps
CPU time 408.59 seconds
Started Feb 29 12:54:12 PM PST 24
Finished Feb 29 01:01:02 PM PST 24
Peak memory 198348 kb
Host smart-0589fbbb-b369-4f7d-b549-fd4ffdf5b56a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3221495037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3221495037
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3549516018
Short name T322
Test name
Test status
Simulation time 20491830 ps
CPU time 0.54 seconds
Started Feb 29 12:54:27 PM PST 24
Finished Feb 29 12:54:28 PM PST 24
Peak memory 194572 kb
Host smart-525e6c32-60a9-4031-84c6-4f18d1c125dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549516018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3549516018
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.435451970
Short name T546
Test name
Test status
Simulation time 90869395 ps
CPU time 0.84 seconds
Started Feb 29 12:54:14 PM PST 24
Finished Feb 29 12:54:15 PM PST 24
Peak memory 196972 kb
Host smart-227ecf7a-9972-4635-b14c-6e24f2290a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435451970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.435451970
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3076038098
Short name T321
Test name
Test status
Simulation time 1090485618 ps
CPU time 9.34 seconds
Started Feb 29 12:54:10 PM PST 24
Finished Feb 29 12:54:20 PM PST 24
Peak memory 198068 kb
Host smart-3b1a5fe1-ec15-4406-a92f-bf96c5ec2fca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076038098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3076038098
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.668955518
Short name T344
Test name
Test status
Simulation time 104180896 ps
CPU time 0.62 seconds
Started Feb 29 12:54:19 PM PST 24
Finished Feb 29 12:54:20 PM PST 24
Peak memory 194208 kb
Host smart-c938f2bb-0821-4a41-88eb-b7bd9c04bbaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668955518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.668955518
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.872504214
Short name T498
Test name
Test status
Simulation time 194131584 ps
CPU time 1.37 seconds
Started Feb 29 12:54:16 PM PST 24
Finished Feb 29 12:54:19 PM PST 24
Peak memory 195880 kb
Host smart-4859cd91-d4b3-472f-b427-a91f2daeedb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872504214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.872504214
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1651802512
Short name T143
Test name
Test status
Simulation time 95973553 ps
CPU time 1.94 seconds
Started Feb 29 12:54:33 PM PST 24
Finished Feb 29 12:54:35 PM PST 24
Peak memory 198048 kb
Host smart-c4399c90-d4f1-4a5d-8109-29ccb787fdf4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651802512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1651802512
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2664891588
Short name T629
Test name
Test status
Simulation time 510416911 ps
CPU time 3.05 seconds
Started Feb 29 12:54:30 PM PST 24
Finished Feb 29 12:54:33 PM PST 24
Peak memory 198156 kb
Host smart-2016a248-75c3-468f-a13b-454ab397b78b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664891588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2664891588
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3228315722
Short name T446
Test name
Test status
Simulation time 38944511 ps
CPU time 0.95 seconds
Started Feb 29 12:54:10 PM PST 24
Finished Feb 29 12:54:12 PM PST 24
Peak memory 195864 kb
Host smart-d75faaec-cb64-4846-a745-63c6e2c81494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228315722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3228315722
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1432989791
Short name T703
Test name
Test status
Simulation time 53811026 ps
CPU time 1.01 seconds
Started Feb 29 12:54:27 PM PST 24
Finished Feb 29 12:54:28 PM PST 24
Peak memory 196828 kb
Host smart-d78569f7-037f-44a1-8140-c83bd970724f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432989791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1432989791
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2090648671
Short name T256
Test name
Test status
Simulation time 757616212 ps
CPU time 4.2 seconds
Started Feb 29 12:54:15 PM PST 24
Finished Feb 29 12:54:19 PM PST 24
Peak memory 198024 kb
Host smart-367784a5-09f8-41de-aad6-22896061849c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090648671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2090648671
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.657489016
Short name T296
Test name
Test status
Simulation time 51786793 ps
CPU time 0.84 seconds
Started Feb 29 12:54:33 PM PST 24
Finished Feb 29 12:54:34 PM PST 24
Peak memory 195556 kb
Host smart-d1faae67-c8f7-44df-9471-bc961acce80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657489016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.657489016
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.4086846210
Short name T504
Test name
Test status
Simulation time 190174843 ps
CPU time 1.3 seconds
Started Feb 29 12:54:25 PM PST 24
Finished Feb 29 12:54:27 PM PST 24
Peak memory 196836 kb
Host smart-f7a26e6c-ec25-4dd0-9eae-b77957f6bede
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086846210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.4086846210
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1063844620
Short name T247
Test name
Test status
Simulation time 12089043114 ps
CPU time 80.96 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:55:34 PM PST 24
Peak memory 198420 kb
Host smart-5cd59325-d309-48f1-9f34-64f1f0479242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063844620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1063844620
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.143742192
Short name T660
Test name
Test status
Simulation time 23387735 ps
CPU time 0.58 seconds
Started Feb 29 12:54:47 PM PST 24
Finished Feb 29 12:54:48 PM PST 24
Peak memory 193944 kb
Host smart-45624ffd-6693-4e25-99fe-07e72fd0cde1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143742192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.143742192
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2630176543
Short name T542
Test name
Test status
Simulation time 131243390 ps
CPU time 0.73 seconds
Started Feb 29 12:54:31 PM PST 24
Finished Feb 29 12:54:32 PM PST 24
Peak memory 195908 kb
Host smart-fab996d0-d3ad-4639-980c-b771c4b7399f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630176543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2630176543
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1875517288
Short name T408
Test name
Test status
Simulation time 961873545 ps
CPU time 12.41 seconds
Started Feb 29 12:54:11 PM PST 24
Finished Feb 29 12:54:24 PM PST 24
Peak memory 198028 kb
Host smart-954f1cb7-b8ca-43c8-be4a-7d762fa112e3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875517288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1875517288
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.995821885
Short name T285
Test name
Test status
Simulation time 87069812 ps
CPU time 0.64 seconds
Started Feb 29 12:54:22 PM PST 24
Finished Feb 29 12:54:23 PM PST 24
Peak memory 195356 kb
Host smart-405b2a86-a8aa-45d6-ae72-2c6246d7604d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995821885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.995821885
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3800029757
Short name T680
Test name
Test status
Simulation time 40962778 ps
CPU time 1.1 seconds
Started Feb 29 12:54:12 PM PST 24
Finished Feb 29 12:54:14 PM PST 24
Peak memory 195876 kb
Host smart-55873246-0a8a-4952-b16d-efda224b9880
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800029757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3800029757
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3565847059
Short name T389
Test name
Test status
Simulation time 46249897 ps
CPU time 2.04 seconds
Started Feb 29 12:54:13 PM PST 24
Finished Feb 29 12:54:16 PM PST 24
Peak memory 198000 kb
Host smart-56da8ea2-6f7a-4b10-a760-bd467e5e817f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565847059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3565847059
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1778744444
Short name T486
Test name
Test status
Simulation time 301916865 ps
CPU time 2.3 seconds
Started Feb 29 12:54:21 PM PST 24
Finished Feb 29 12:54:25 PM PST 24
Peak memory 197200 kb
Host smart-9bb6e82a-06df-4af7-bd3e-a913a17ad813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778744444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1778744444
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.272327034
Short name T471
Test name
Test status
Simulation time 61042125 ps
CPU time 0.76 seconds
Started Feb 29 12:54:35 PM PST 24
Finished Feb 29 12:54:36 PM PST 24
Peak memory 195536 kb
Host smart-b5ac4930-ae71-4fcb-b3a3-bd222b5cc5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272327034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.272327034
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3227230035
Short name T349
Test name
Test status
Simulation time 20707847 ps
CPU time 0.68 seconds
Started Feb 29 12:54:18 PM PST 24
Finished Feb 29 12:54:20 PM PST 24
Peak memory 194376 kb
Host smart-1b2ae444-3e4c-41da-acfc-4799b00d2e8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227230035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3227230035
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.938579792
Short name T120
Test name
Test status
Simulation time 75571645 ps
CPU time 1.83 seconds
Started Feb 29 12:54:26 PM PST 24
Finished Feb 29 12:54:28 PM PST 24
Peak memory 198020 kb
Host smart-070f38f8-f294-4850-978e-9732ba1d2762
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938579792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.938579792
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.434295879
Short name T612
Test name
Test status
Simulation time 393281046 ps
CPU time 1.31 seconds
Started Feb 29 12:54:19 PM PST 24
Finished Feb 29 12:54:21 PM PST 24
Peak memory 196592 kb
Host smart-71c9d16f-52fb-4fcd-9825-560edda9115e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434295879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.434295879
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.147132581
Short name T74
Test name
Test status
Simulation time 258954952 ps
CPU time 1.15 seconds
Started Feb 29 12:54:36 PM PST 24
Finished Feb 29 12:54:38 PM PST 24
Peak memory 196588 kb
Host smart-f92aca0f-2772-47c9-910b-f0a669a2edbf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147132581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.147132581
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1968322042
Short name T423
Test name
Test status
Simulation time 35321342136 ps
CPU time 191.74 seconds
Started Feb 29 12:54:35 PM PST 24
Finished Feb 29 12:57:47 PM PST 24
Peak memory 198120 kb
Host smart-18aaa911-7748-4fad-8745-4c0dafe4f570
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968322042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1968322042
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.1692882954
Short name T61
Test name
Test status
Simulation time 68713138861 ps
CPU time 756.56 seconds
Started Feb 29 12:54:21 PM PST 24
Finished Feb 29 01:06:59 PM PST 24
Peak memory 198332 kb
Host smart-7650d1a6-4e65-47f3-9a94-30c108fd9f6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1692882954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.1692882954
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1676823310
Short name T517
Test name
Test status
Simulation time 107494165 ps
CPU time 0.57 seconds
Started Feb 29 12:54:17 PM PST 24
Finished Feb 29 12:54:23 PM PST 24
Peak memory 193884 kb
Host smart-347c5285-e4f7-4189-a7c5-be8c1a721b3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676823310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1676823310
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3797885810
Short name T292
Test name
Test status
Simulation time 25933033 ps
CPU time 0.76 seconds
Started Feb 29 12:54:39 PM PST 24
Finished Feb 29 12:54:40 PM PST 24
Peak memory 195212 kb
Host smart-c496735c-87f8-4edd-a2b4-564ef13a3969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797885810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3797885810
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1255785514
Short name T460
Test name
Test status
Simulation time 1806187927 ps
CPU time 16.13 seconds
Started Feb 29 12:54:12 PM PST 24
Finished Feb 29 12:54:29 PM PST 24
Peak memory 196756 kb
Host smart-4fe010ca-755f-4451-98f4-7378ae6ea3f0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255785514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1255785514
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2990210834
Short name T537
Test name
Test status
Simulation time 446799225 ps
CPU time 0.66 seconds
Started Feb 29 12:54:32 PM PST 24
Finished Feb 29 12:54:33 PM PST 24
Peak memory 194704 kb
Host smart-c7b08eae-ea56-4e92-bd75-5f8e69f80c62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990210834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2990210834
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3236549300
Short name T544
Test name
Test status
Simulation time 104256017 ps
CPU time 1.42 seconds
Started Feb 29 12:54:35 PM PST 24
Finished Feb 29 12:54:37 PM PST 24
Peak memory 197068 kb
Host smart-40dff5e7-d255-449f-96f6-14dcb7a09fca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236549300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3236549300
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2955598825
Short name T70
Test name
Test status
Simulation time 120288187 ps
CPU time 1.37 seconds
Started Feb 29 12:54:42 PM PST 24
Finished Feb 29 12:54:44 PM PST 24
Peak memory 196824 kb
Host smart-9bea0b5a-9a31-4141-abd1-09f38a019c74
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955598825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2955598825
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1965660061
Short name T457
Test name
Test status
Simulation time 121832056 ps
CPU time 2.51 seconds
Started Feb 29 12:54:40 PM PST 24
Finished Feb 29 12:54:43 PM PST 24
Peak memory 196584 kb
Host smart-3d2287ed-2374-42f7-9f38-a0bd637f78e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965660061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1965660061
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.4102555838
Short name T707
Test name
Test status
Simulation time 938090925 ps
CPU time 1.05 seconds
Started Feb 29 12:54:40 PM PST 24
Finished Feb 29 12:54:42 PM PST 24
Peak memory 195860 kb
Host smart-7af536ea-f1bb-4ec8-9502-6680a1418ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102555838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.4102555838
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1743580647
Short name T392
Test name
Test status
Simulation time 26851106 ps
CPU time 0.77 seconds
Started Feb 29 12:54:42 PM PST 24
Finished Feb 29 12:54:43 PM PST 24
Peak memory 195336 kb
Host smart-a2afc1fb-57cf-4a8e-bdeb-39331e5faf78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743580647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1743580647
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1861269290
Short name T199
Test name
Test status
Simulation time 109796693 ps
CPU time 4.48 seconds
Started Feb 29 12:54:42 PM PST 24
Finished Feb 29 12:54:47 PM PST 24
Peak memory 198060 kb
Host smart-a5ccb8c1-e3e2-433a-a8bf-797e1809b0d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861269290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1861269290
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3261175617
Short name T420
Test name
Test status
Simulation time 68980698 ps
CPU time 1.05 seconds
Started Feb 29 12:54:19 PM PST 24
Finished Feb 29 12:54:21 PM PST 24
Peak memory 195676 kb
Host smart-ac547ded-c51c-4fa3-887b-f913e9d99feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261175617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3261175617
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2598074710
Short name T636
Test name
Test status
Simulation time 27352407 ps
CPU time 0.75 seconds
Started Feb 29 12:54:40 PM PST 24
Finished Feb 29 12:54:41 PM PST 24
Peak memory 194088 kb
Host smart-ba3e7672-a8b7-4ca9-843a-1cb20ffbb2b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598074710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2598074710
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2437771047
Short name T10
Test name
Test status
Simulation time 18787828143 ps
CPU time 203.48 seconds
Started Feb 29 12:54:34 PM PST 24
Finished Feb 29 12:57:58 PM PST 24
Peak memory 198196 kb
Host smart-fe57f47f-921b-4319-bb19-6410faea9320
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437771047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2437771047
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.892613614
Short name T245
Test name
Test status
Simulation time 122756700106 ps
CPU time 1969.62 seconds
Started Feb 29 12:54:40 PM PST 24
Finished Feb 29 01:27:30 PM PST 24
Peak memory 198368 kb
Host smart-75145514-eb37-4d56-9c66-fadeb94948ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=892613614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.892613614
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3829018857
Short name T416
Test name
Test status
Simulation time 12472143 ps
CPU time 0.57 seconds
Started Feb 29 12:53:02 PM PST 24
Finished Feb 29 12:53:02 PM PST 24
Peak memory 193856 kb
Host smart-1edda6e4-eaf5-4d9d-b67b-5d35d68739a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829018857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3829018857
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.896858363
Short name T240
Test name
Test status
Simulation time 48937657 ps
CPU time 0.85 seconds
Started Feb 29 12:52:48 PM PST 24
Finished Feb 29 12:52:49 PM PST 24
Peak memory 195284 kb
Host smart-5d385f35-5362-48f6-ad9d-717e9131b2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896858363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.896858363
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2739029707
Short name T587
Test name
Test status
Simulation time 458597150 ps
CPU time 6.46 seconds
Started Feb 29 12:52:52 PM PST 24
Finished Feb 29 12:52:59 PM PST 24
Peak memory 196900 kb
Host smart-bd78324e-1891-4747-a324-11e40db719ce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739029707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2739029707
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.4027773832
Short name T541
Test name
Test status
Simulation time 147180526 ps
CPU time 0.72 seconds
Started Feb 29 12:52:50 PM PST 24
Finished Feb 29 12:52:51 PM PST 24
Peak memory 194692 kb
Host smart-ea18b341-32b4-409c-aa6c-e1367edd142a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027773832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.4027773832
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.13359910
Short name T536
Test name
Test status
Simulation time 235611339 ps
CPU time 0.72 seconds
Started Feb 29 12:53:04 PM PST 24
Finished Feb 29 12:53:05 PM PST 24
Peak memory 195524 kb
Host smart-723d777e-3820-441d-bd0a-d77ec9ca4ba1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13359910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.13359910
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3846554798
Short name T329
Test name
Test status
Simulation time 155662162 ps
CPU time 1.75 seconds
Started Feb 29 12:52:56 PM PST 24
Finished Feb 29 12:52:59 PM PST 24
Peak memory 196440 kb
Host smart-3652bc1b-d73e-49b4-8179-aa1bd55a2cf2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846554798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3846554798
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2674468291
Short name T492
Test name
Test status
Simulation time 94203217 ps
CPU time 2.13 seconds
Started Feb 29 12:52:59 PM PST 24
Finished Feb 29 12:53:01 PM PST 24
Peak memory 196752 kb
Host smart-aa385f92-c497-4c95-a216-4c245731a3c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674468291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2674468291
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3067171659
Short name T195
Test name
Test status
Simulation time 26128318 ps
CPU time 1.02 seconds
Started Feb 29 12:52:58 PM PST 24
Finished Feb 29 12:52:59 PM PST 24
Peak memory 196060 kb
Host smart-205d1d40-48e8-4182-b5b9-949e7fb6d52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067171659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3067171659
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1723222169
Short name T75
Test name
Test status
Simulation time 153384492 ps
CPU time 0.89 seconds
Started Feb 29 12:53:12 PM PST 24
Finished Feb 29 12:53:13 PM PST 24
Peak memory 196056 kb
Host smart-70d4ed68-fcda-497a-a9ec-5978e617e680
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723222169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1723222169
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1206009397
Short name T9
Test name
Test status
Simulation time 3261894982 ps
CPU time 4.81 seconds
Started Feb 29 12:53:03 PM PST 24
Finished Feb 29 12:53:08 PM PST 24
Peak memory 198100 kb
Host smart-dc02b434-d232-4566-a81c-c4a3cd1f1ec3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206009397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1206009397
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.927659715
Short name T524
Test name
Test status
Simulation time 168573290 ps
CPU time 0.95 seconds
Started Feb 29 12:53:03 PM PST 24
Finished Feb 29 12:53:04 PM PST 24
Peak memory 195300 kb
Host smart-1f43939e-3165-4602-aa55-82eb9d56c723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927659715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.927659715
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.414241522
Short name T188
Test name
Test status
Simulation time 27306353 ps
CPU time 0.78 seconds
Started Feb 29 12:52:47 PM PST 24
Finished Feb 29 12:52:48 PM PST 24
Peak memory 195812 kb
Host smart-2b3ba477-93dc-4235-8edf-c1f4d12107b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414241522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.414241522
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_alert_test.785181050
Short name T718
Test name
Test status
Simulation time 40784158 ps
CPU time 0.55 seconds
Started Feb 29 12:53:10 PM PST 24
Finished Feb 29 12:53:11 PM PST 24
Peak memory 193912 kb
Host smart-eef8fc4e-354a-46dd-a255-e12e5cf3ebee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785181050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.785181050
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3015867499
Short name T117
Test name
Test status
Simulation time 70300809 ps
CPU time 0.75 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 12:53:11 PM PST 24
Peak memory 195236 kb
Host smart-5b905415-8b12-4a4a-ab3f-a72393b0a1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015867499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3015867499
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.4100132493
Short name T303
Test name
Test status
Simulation time 1216263841 ps
CPU time 11.09 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:53:27 PM PST 24
Peak memory 197016 kb
Host smart-ab00b840-e023-4ec3-ac6f-e6f0cf1013b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100132493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.4100132493
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2928265189
Short name T417
Test name
Test status
Simulation time 127851146 ps
CPU time 1.05 seconds
Started Feb 29 12:53:04 PM PST 24
Finished Feb 29 12:53:05 PM PST 24
Peak memory 197928 kb
Host smart-ae82bd3e-896e-46ac-b00b-922672a49169
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928265189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2928265189
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.4168522261
Short name T224
Test name
Test status
Simulation time 30942647 ps
CPU time 0.86 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:53:16 PM PST 24
Peak memory 196868 kb
Host smart-0404cb66-2fc7-45f4-aca1-bc8ef6f9fbb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168522261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.4168522261
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.21854890
Short name T304
Test name
Test status
Simulation time 156641452 ps
CPU time 3.01 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 12:53:14 PM PST 24
Peak memory 198192 kb
Host smart-52bca429-e2ed-4a4c-ac99-6c04cd99b4b8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21854890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.gpio_intr_with_filter_rand_intr_event.21854890
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2628129818
Short name T363
Test name
Test status
Simulation time 62421962 ps
CPU time 0.97 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 12:53:12 PM PST 24
Peak memory 196140 kb
Host smart-56fe6fab-b71a-4095-b2da-4da113a6eac1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628129818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2628129818
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2023458176
Short name T453
Test name
Test status
Simulation time 183477437 ps
CPU time 0.99 seconds
Started Feb 29 12:53:00 PM PST 24
Finished Feb 29 12:53:02 PM PST 24
Peak memory 196112 kb
Host smart-3e225610-4e32-462f-8c70-89226bdc694d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023458176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2023458176
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.854727911
Short name T557
Test name
Test status
Simulation time 69272265 ps
CPU time 1.26 seconds
Started Feb 29 12:53:12 PM PST 24
Finished Feb 29 12:53:14 PM PST 24
Peak memory 198104 kb
Host smart-7e6003f3-e1b7-4ac5-b99a-f777f82df02a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854727911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.854727911
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1365152527
Short name T244
Test name
Test status
Simulation time 268071281 ps
CPU time 4.56 seconds
Started Feb 29 12:53:13 PM PST 24
Finished Feb 29 12:53:18 PM PST 24
Peak memory 198056 kb
Host smart-189bb2b4-4293-441e-bf52-15d5fe5d3cfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365152527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1365152527
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1165999875
Short name T278
Test name
Test status
Simulation time 286293990 ps
CPU time 1.12 seconds
Started Feb 29 12:52:51 PM PST 24
Finished Feb 29 12:52:52 PM PST 24
Peak memory 195856 kb
Host smart-8465fdaf-3595-4749-b022-b48d97352e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165999875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1165999875
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1640631688
Short name T145
Test name
Test status
Simulation time 33019170 ps
CPU time 0.8 seconds
Started Feb 29 12:52:58 PM PST 24
Finished Feb 29 12:52:59 PM PST 24
Peak memory 195332 kb
Host smart-b7d76a15-c893-4afb-92e7-77e0dd3e3fb7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640631688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1640631688
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.47107758
Short name T330
Test name
Test status
Simulation time 13882850190 ps
CPU time 142.02 seconds
Started Feb 29 12:53:01 PM PST 24
Finished Feb 29 12:55:24 PM PST 24
Peak memory 198116 kb
Host smart-40f02388-b0e0-4a17-b5fd-dfed7d7db55b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47107758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpi
o_stress_all.47107758
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1764613761
Short name T444
Test name
Test status
Simulation time 38213578604 ps
CPU time 979.79 seconds
Started Feb 29 12:53:04 PM PST 24
Finished Feb 29 01:09:24 PM PST 24
Peak memory 198212 kb
Host smart-7994ff42-de80-4d6f-baeb-1c40bb0969ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1764613761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1764613761
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.4005764544
Short name T666
Test name
Test status
Simulation time 51762400 ps
CPU time 0.56 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:53:16 PM PST 24
Peak memory 193908 kb
Host smart-e244663e-8d86-4bcf-8808-1773aafe5d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005764544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.4005764544
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3339419570
Short name T678
Test name
Test status
Simulation time 33911449 ps
CPU time 0.77 seconds
Started Feb 29 12:53:18 PM PST 24
Finished Feb 29 12:53:19 PM PST 24
Peak memory 195940 kb
Host smart-3359653d-95ee-490d-8eeb-fe893e8b167c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339419570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3339419570
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3661573443
Short name T490
Test name
Test status
Simulation time 468361170 ps
CPU time 26.64 seconds
Started Feb 29 12:52:59 PM PST 24
Finished Feb 29 12:53:26 PM PST 24
Peak memory 198048 kb
Host smart-a816c3bb-8f9f-45e8-bfed-c7746c7e5dd4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661573443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3661573443
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1456800639
Short name T20
Test name
Test status
Simulation time 663782592 ps
CPU time 1.1 seconds
Started Feb 29 12:53:13 PM PST 24
Finished Feb 29 12:53:14 PM PST 24
Peak memory 196672 kb
Host smart-90563063-c0db-4f3e-972b-a4d272d3ad45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456800639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1456800639
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4188614360
Short name T307
Test name
Test status
Simulation time 22096495 ps
CPU time 0.73 seconds
Started Feb 29 12:53:01 PM PST 24
Finished Feb 29 12:53:02 PM PST 24
Peak memory 195480 kb
Host smart-a35f5d9f-104e-4151-97aa-19ba13b3b75b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188614360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4188614360
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3049135507
Short name T684
Test name
Test status
Simulation time 247543173 ps
CPU time 2.49 seconds
Started Feb 29 12:53:09 PM PST 24
Finished Feb 29 12:53:11 PM PST 24
Peak memory 197924 kb
Host smart-f735f761-fda9-46ce-8481-8e2b5105a584
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049135507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3049135507
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1271171644
Short name T53
Test name
Test status
Simulation time 250043331 ps
CPU time 3.63 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 12:53:15 PM PST 24
Peak memory 198136 kb
Host smart-54b71bae-15d5-4de4-85b9-528c47c08b95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271171644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1271171644
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1886250346
Short name T686
Test name
Test status
Simulation time 80606843 ps
CPU time 1.08 seconds
Started Feb 29 12:53:04 PM PST 24
Finished Feb 29 12:53:05 PM PST 24
Peak memory 196164 kb
Host smart-918d0905-6a42-4a4d-9a68-1f4b43b7783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886250346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1886250346
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2912546210
Short name T713
Test name
Test status
Simulation time 56956559 ps
CPU time 1.32 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:18 PM PST 24
Peak memory 197052 kb
Host smart-bf50a333-7cf9-4ee9-86e6-32b06258aa73
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912546210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2912546210
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3263709524
Short name T266
Test name
Test status
Simulation time 60661715 ps
CPU time 2.81 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:19 PM PST 24
Peak memory 197936 kb
Host smart-2feeacdb-aae5-4184-9ffe-de4de6856f2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263709524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3263709524
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3145077208
Short name T317
Test name
Test status
Simulation time 119173705 ps
CPU time 1.11 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 195620 kb
Host smart-452f914a-781a-46bd-a142-136abc96dce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145077208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3145077208
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.556762250
Short name T158
Test name
Test status
Simulation time 747395032 ps
CPU time 0.98 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 12:53:12 PM PST 24
Peak memory 195492 kb
Host smart-d2094746-dd6e-4e44-90f2-83c37364b328
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556762250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.556762250
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.824160789
Short name T566
Test name
Test status
Simulation time 23988310816 ps
CPU time 108.61 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 12:55:00 PM PST 24
Peak memory 198196 kb
Host smart-0fdf3c55-2a35-45d1-baee-ccc835a4f9f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824160789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.824160789
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2335634996
Short name T57
Test name
Test status
Simulation time 1200882755522 ps
CPU time 1519.28 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 01:18:36 PM PST 24
Peak memory 198344 kb
Host smart-a90cbd3b-5c71-43bd-8252-39a88197da0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2335634996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2335634996
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.164874257
Short name T327
Test name
Test status
Simulation time 80908257 ps
CPU time 0.56 seconds
Started Feb 29 12:53:09 PM PST 24
Finished Feb 29 12:53:10 PM PST 24
Peak memory 194708 kb
Host smart-b89efb86-f2c4-4609-9f55-021081d9d01a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164874257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.164874257
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2122601836
Short name T467
Test name
Test status
Simulation time 70266979 ps
CPU time 0.61 seconds
Started Feb 29 12:53:14 PM PST 24
Finished Feb 29 12:53:15 PM PST 24
Peak memory 194044 kb
Host smart-3a7e190e-9dae-40d4-b1a8-e17d40a4a0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122601836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2122601836
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.940944023
Short name T440
Test name
Test status
Simulation time 2392568004 ps
CPU time 14.93 seconds
Started Feb 29 12:53:04 PM PST 24
Finished Feb 29 12:53:19 PM PST 24
Peak memory 197452 kb
Host smart-e79ce012-eeca-437c-84e1-7eb98fa18dab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940944023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.940944023
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2973830196
Short name T297
Test name
Test status
Simulation time 368177946 ps
CPU time 0.7 seconds
Started Feb 29 12:53:09 PM PST 24
Finished Feb 29 12:53:10 PM PST 24
Peak memory 194868 kb
Host smart-877b9d48-36f2-4b1e-9bf1-1dc533c03b66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973830196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2973830196
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2416776090
Short name T382
Test name
Test status
Simulation time 731747787 ps
CPU time 1.34 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:53:22 PM PST 24
Peak memory 196872 kb
Host smart-413d5bd0-acd6-4b6f-a150-37520b978c6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416776090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2416776090
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2993125629
Short name T17
Test name
Test status
Simulation time 307551870 ps
CPU time 2.93 seconds
Started Feb 29 12:53:08 PM PST 24
Finished Feb 29 12:53:11 PM PST 24
Peak memory 198124 kb
Host smart-207691f0-a638-46f0-81f9-00e77c9de829
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993125629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2993125629
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3139306812
Short name T624
Test name
Test status
Simulation time 131654780 ps
CPU time 2.93 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:19 PM PST 24
Peak memory 197252 kb
Host smart-97b605d9-c3f7-48b2-93ea-f1bd7536b450
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139306812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3139306812
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3744085894
Short name T426
Test name
Test status
Simulation time 177730740 ps
CPU time 1.25 seconds
Started Feb 29 12:53:09 PM PST 24
Finished Feb 29 12:53:11 PM PST 24
Peak memory 197112 kb
Host smart-ad6e147f-6383-4739-a952-eacdf4d1d306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744085894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3744085894
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2519784751
Short name T595
Test name
Test status
Simulation time 17572350 ps
CPU time 0.66 seconds
Started Feb 29 12:52:59 PM PST 24
Finished Feb 29 12:52:59 PM PST 24
Peak memory 195300 kb
Host smart-a754d6e1-99a9-4b35-bc21-7c619fc2785e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519784751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2519784751
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2530212422
Short name T427
Test name
Test status
Simulation time 122615306 ps
CPU time 1.71 seconds
Started Feb 29 12:53:00 PM PST 24
Finished Feb 29 12:53:03 PM PST 24
Peak memory 198016 kb
Host smart-b7819518-c2f2-4383-bfc8-9525674c3ab0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530212422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2530212422
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1447462099
Short name T480
Test name
Test status
Simulation time 236228740 ps
CPU time 1.09 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:53:16 PM PST 24
Peak memory 195704 kb
Host smart-d5f31a77-e2a1-4354-b9c7-f36325bf698e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447462099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1447462099
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1669784575
Short name T288
Test name
Test status
Simulation time 41935250 ps
CPU time 0.81 seconds
Started Feb 29 12:53:12 PM PST 24
Finished Feb 29 12:53:12 PM PST 24
Peak memory 195296 kb
Host smart-73bb47f6-2b18-446f-9fc5-faa23731ceba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669784575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1669784575
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.4112884367
Short name T200
Test name
Test status
Simulation time 12135313135 ps
CPU time 140.72 seconds
Started Feb 29 12:53:19 PM PST 24
Finished Feb 29 12:55:40 PM PST 24
Peak memory 198172 kb
Host smart-38fe8c38-b772-4cfa-960e-68c24007d44a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112884367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.4112884367
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2174920135
Short name T263
Test name
Test status
Simulation time 81194164476 ps
CPU time 1749.17 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 01:22:20 PM PST 24
Peak memory 198368 kb
Host smart-4049a67d-4de6-44e2-924d-0ddad5ccce06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2174920135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.2174920135
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.21664718
Short name T275
Test name
Test status
Simulation time 16482281 ps
CPU time 0.57 seconds
Started Feb 29 12:53:14 PM PST 24
Finished Feb 29 12:53:15 PM PST 24
Peak memory 194616 kb
Host smart-60af3323-e119-4ecc-9723-12283a3fa228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21664718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.21664718
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.462561838
Short name T51
Test name
Test status
Simulation time 36081781 ps
CPU time 0.73 seconds
Started Feb 29 12:53:08 PM PST 24
Finished Feb 29 12:53:09 PM PST 24
Peak memory 195044 kb
Host smart-22d12d71-b699-4727-aebd-dda970b63e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462561838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.462561838
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1630720570
Short name T558
Test name
Test status
Simulation time 1158872392 ps
CPU time 19.67 seconds
Started Feb 29 12:53:04 PM PST 24
Finished Feb 29 12:53:24 PM PST 24
Peak memory 197984 kb
Host smart-4fd65829-c978-4d0c-be71-9a54bbc3571d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630720570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1630720570
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2056134226
Short name T223
Test name
Test status
Simulation time 65317438 ps
CPU time 0.89 seconds
Started Feb 29 12:53:07 PM PST 24
Finished Feb 29 12:53:08 PM PST 24
Peak memory 196812 kb
Host smart-86b28e9f-cb0f-47c4-b957-3cf82c6df8b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056134226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2056134226
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1098423217
Short name T437
Test name
Test status
Simulation time 47648818 ps
CPU time 0.84 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:53:16 PM PST 24
Peak memory 195616 kb
Host smart-9ad46b05-f4bf-489e-806f-ab6d7fffb4dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098423217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1098423217
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.496846284
Short name T105
Test name
Test status
Simulation time 102557681 ps
CPU time 2.1 seconds
Started Feb 29 12:53:10 PM PST 24
Finished Feb 29 12:53:17 PM PST 24
Peak memory 198080 kb
Host smart-4fac958c-1b5a-43dc-abaf-c4f7202aac34
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496846284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.496846284
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3058884593
Short name T576
Test name
Test status
Simulation time 57420680 ps
CPU time 1.4 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:53:17 PM PST 24
Peak memory 196640 kb
Host smart-7eeb3b04-e7f5-4616-8489-957b3744f895
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058884593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3058884593
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.113177790
Short name T361
Test name
Test status
Simulation time 191860885 ps
CPU time 1.18 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 12:53:12 PM PST 24
Peak memory 196652 kb
Host smart-c79abc4c-4bb2-4f93-bf66-b178d7c0c79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113177790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.113177790
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3527509993
Short name T449
Test name
Test status
Simulation time 107187618 ps
CPU time 0.98 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:53:16 PM PST 24
Peak memory 196752 kb
Host smart-88c7cc22-e083-4748-8382-812523b5c640
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527509993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3527509993
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2063743009
Short name T374
Test name
Test status
Simulation time 853059744 ps
CPU time 2.64 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:53:18 PM PST 24
Peak memory 198044 kb
Host smart-65d23fba-54df-4549-bcfe-24487e86a328
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063743009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2063743009
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.4247798826
Short name T282
Test name
Test status
Simulation time 122755178 ps
CPU time 1.23 seconds
Started Feb 29 12:53:15 PM PST 24
Finished Feb 29 12:53:17 PM PST 24
Peak memory 195980 kb
Host smart-739574a8-3eb4-4c42-bd5b-b9210f82b882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247798826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.4247798826
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1760106090
Short name T299
Test name
Test status
Simulation time 60092083 ps
CPU time 1.05 seconds
Started Feb 29 12:53:13 PM PST 24
Finished Feb 29 12:53:14 PM PST 24
Peak memory 195896 kb
Host smart-3a785462-9c56-4ec8-b6bf-2dfbf0b0ab96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760106090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1760106090
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3386032620
Short name T447
Test name
Test status
Simulation time 17191661932 ps
CPU time 116.51 seconds
Started Feb 29 12:53:16 PM PST 24
Finished Feb 29 12:55:13 PM PST 24
Peak memory 198144 kb
Host smart-a63898bc-fa13-4b5a-b8c9-19242a46d91d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386032620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3386032620
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2469812588
Short name T866
Test name
Test status
Simulation time 304773885 ps
CPU time 1.35 seconds
Started Feb 29 12:42:31 PM PST 24
Finished Feb 29 12:42:34 PM PST 24
Peak memory 197160 kb
Host smart-b17b751e-7062-4c8d-9272-bdf76cc89912
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2469812588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2469812588
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1408170272
Short name T865
Test name
Test status
Simulation time 37261315 ps
CPU time 0.83 seconds
Started Feb 29 12:42:25 PM PST 24
Finished Feb 29 12:42:26 PM PST 24
Peak memory 196236 kb
Host smart-bdb18bab-e318-4b68-96ef-35dba1a1af51
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408170272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1408170272
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3844998941
Short name T857
Test name
Test status
Simulation time 56595583 ps
CPU time 1.18 seconds
Started Feb 29 12:42:30 PM PST 24
Finished Feb 29 12:42:31 PM PST 24
Peak memory 198524 kb
Host smart-c32600a0-e4af-4b0f-8f98-e4a45b1d9417
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3844998941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3844998941
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2129417987
Short name T852
Test name
Test status
Simulation time 29547587 ps
CPU time 0.98 seconds
Started Feb 29 12:42:26 PM PST 24
Finished Feb 29 12:42:29 PM PST 24
Peak memory 196600 kb
Host smart-76af4908-e118-42ec-8c9d-8542146222d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129417987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2129417987
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.741382550
Short name T858
Test name
Test status
Simulation time 621720523 ps
CPU time 1.1 seconds
Started Feb 29 12:42:34 PM PST 24
Finished Feb 29 12:42:35 PM PST 24
Peak memory 198472 kb
Host smart-5cc9905c-ad69-4172-af49-606c76fe205d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=741382550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.741382550
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3359022855
Short name T928
Test name
Test status
Simulation time 235325144 ps
CPU time 1.1 seconds
Started Feb 29 12:42:28 PM PST 24
Finished Feb 29 12:42:31 PM PST 24
Peak memory 197056 kb
Host smart-afe518ab-4bde-435a-b864-715a72e296b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359022855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3359022855
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1457615694
Short name T849
Test name
Test status
Simulation time 974631402 ps
CPU time 1.21 seconds
Started Feb 29 12:42:36 PM PST 24
Finished Feb 29 12:42:38 PM PST 24
Peak memory 196312 kb
Host smart-18e43e0f-9e07-4760-abe9-128f840d757e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1457615694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1457615694
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.891026714
Short name T850
Test name
Test status
Simulation time 50526320 ps
CPU time 1.04 seconds
Started Feb 29 12:42:29 PM PST 24
Finished Feb 29 12:42:31 PM PST 24
Peak memory 197292 kb
Host smart-90d3caca-1d77-47b5-8af0-39f5fa8d4f26
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891026714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.891026714
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3285598668
Short name T847
Test name
Test status
Simulation time 216528781 ps
CPU time 0.96 seconds
Started Feb 29 12:42:26 PM PST 24
Finished Feb 29 12:42:28 PM PST 24
Peak memory 196128 kb
Host smart-9900b7a5-7847-4609-aa54-2e9cd5033b3e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3285598668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3285598668
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2918211312
Short name T945
Test name
Test status
Simulation time 191254625 ps
CPU time 1.15 seconds
Started Feb 29 12:42:26 PM PST 24
Finished Feb 29 12:42:28 PM PST 24
Peak memory 196916 kb
Host smart-79ed1705-1103-4218-9570-2191a34fd80d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918211312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2918211312
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1976883686
Short name T922
Test name
Test status
Simulation time 79728622 ps
CPU time 1.17 seconds
Started Feb 29 12:42:26 PM PST 24
Finished Feb 29 12:42:28 PM PST 24
Peak memory 196320 kb
Host smart-d1d510c2-a2ff-418d-b548-74f724026023
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1976883686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1976883686
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.856415604
Short name T895
Test name
Test status
Simulation time 91542339 ps
CPU time 0.79 seconds
Started Feb 29 12:42:26 PM PST 24
Finished Feb 29 12:42:28 PM PST 24
Peak memory 195528 kb
Host smart-69a5388a-ae60-46ed-875f-daed59829cd7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856415604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.856415604
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3712390013
Short name T887
Test name
Test status
Simulation time 190817402 ps
CPU time 0.96 seconds
Started Feb 29 12:42:24 PM PST 24
Finished Feb 29 12:42:25 PM PST 24
Peak memory 195844 kb
Host smart-eb80e5df-71ed-4de6-b4b9-600369970a05
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3712390013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3712390013
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2621840996
Short name T854
Test name
Test status
Simulation time 103780248 ps
CPU time 0.85 seconds
Started Feb 29 12:42:41 PM PST 24
Finished Feb 29 12:42:42 PM PST 24
Peak memory 195568 kb
Host smart-2f7b5f5a-a347-4a4f-860a-f21005b9725b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621840996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2621840996
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1752175639
Short name T878
Test name
Test status
Simulation time 127559502 ps
CPU time 1.04 seconds
Started Feb 29 12:42:36 PM PST 24
Finished Feb 29 12:42:38 PM PST 24
Peak memory 198248 kb
Host smart-0d0d0f86-fcf2-4944-91c6-9443f44d6937
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1752175639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1752175639
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2132339659
Short name T943
Test name
Test status
Simulation time 51502792 ps
CPU time 1.42 seconds
Started Feb 29 12:42:39 PM PST 24
Finished Feb 29 12:42:41 PM PST 24
Peak memory 196980 kb
Host smart-924f28bb-ccab-467c-807f-1a0fa7e16998
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132339659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2132339659
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4293882513
Short name T920
Test name
Test status
Simulation time 29491893 ps
CPU time 0.89 seconds
Started Feb 29 12:42:30 PM PST 24
Finished Feb 29 12:42:32 PM PST 24
Peak memory 195572 kb
Host smart-38ed7685-a16e-411f-ad63-674b1fa9a021
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4293882513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.4293882513
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3707970749
Short name T883
Test name
Test status
Simulation time 68950203 ps
CPU time 0.96 seconds
Started Feb 29 12:42:28 PM PST 24
Finished Feb 29 12:42:30 PM PST 24
Peak memory 198116 kb
Host smart-00aed233-9f02-4752-aa22-f80c6ac2d533
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707970749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3707970749
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.498409254
Short name T846
Test name
Test status
Simulation time 221622980 ps
CPU time 1.04 seconds
Started Feb 29 12:42:29 PM PST 24
Finished Feb 29 12:42:31 PM PST 24
Peak memory 196940 kb
Host smart-fcdbae4d-6114-4a6a-9fa7-75d8c00078ee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=498409254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.498409254
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1927690117
Short name T880
Test name
Test status
Simulation time 31054931 ps
CPU time 0.81 seconds
Started Feb 29 12:42:28 PM PST 24
Finished Feb 29 12:42:30 PM PST 24
Peak memory 195572 kb
Host smart-a6b7e3e1-dc07-4e21-906b-e1907b6ad73e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927690117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1927690117
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.218046561
Short name T931
Test name
Test status
Simulation time 116695341 ps
CPU time 1.25 seconds
Started Feb 29 12:42:39 PM PST 24
Finished Feb 29 12:42:41 PM PST 24
Peak memory 196876 kb
Host smart-2ed70273-626b-48b6-b807-3d3192a3232b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=218046561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.218046561
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1483478239
Short name T870
Test name
Test status
Simulation time 45889227 ps
CPU time 1.14 seconds
Started Feb 29 12:42:32 PM PST 24
Finished Feb 29 12:42:34 PM PST 24
Peak memory 196856 kb
Host smart-928e0afb-81a4-4b6d-8b5a-3b3b7dd55cad
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483478239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1483478239
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3207425451
Short name T889
Test name
Test status
Simulation time 34097998 ps
CPU time 0.79 seconds
Started Feb 29 12:42:23 PM PST 24
Finished Feb 29 12:42:24 PM PST 24
Peak memory 196344 kb
Host smart-e9abd1e0-886c-44bd-ac6a-ebd7c7d48082
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3207425451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3207425451
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1857778992
Short name T933
Test name
Test status
Simulation time 798655462 ps
CPU time 0.92 seconds
Started Feb 29 12:42:27 PM PST 24
Finished Feb 29 12:42:30 PM PST 24
Peak memory 196008 kb
Host smart-035490cd-608a-4df1-958a-f87d9db9589c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857778992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1857778992
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2307833960
Short name T903
Test name
Test status
Simulation time 24061187 ps
CPU time 0.72 seconds
Started Feb 29 12:42:27 PM PST 24
Finished Feb 29 12:42:28 PM PST 24
Peak memory 195348 kb
Host smart-3758cfda-4cec-47b1-9011-20522aa0f408
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2307833960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2307833960
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1122994040
Short name T888
Test name
Test status
Simulation time 206328520 ps
CPU time 1.02 seconds
Started Feb 29 12:42:31 PM PST 24
Finished Feb 29 12:42:33 PM PST 24
Peak memory 196408 kb
Host smart-9375ef0d-8210-44bc-86b2-25983dda3119
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122994040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1122994040
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1636307549
Short name T860
Test name
Test status
Simulation time 103213895 ps
CPU time 1.47 seconds
Started Feb 29 12:42:59 PM PST 24
Finished Feb 29 12:43:02 PM PST 24
Peak memory 197352 kb
Host smart-10d32074-5557-49d0-9307-291068ce9e18
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1636307549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1636307549
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.422781728
Short name T898
Test name
Test status
Simulation time 519496752 ps
CPU time 1.03 seconds
Started Feb 29 12:42:31 PM PST 24
Finished Feb 29 12:42:33 PM PST 24
Peak memory 197268 kb
Host smart-f2d8269b-138b-4804-8cfc-e9a2e62b8349
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422781728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.422781728
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3398310547
Short name T851
Test name
Test status
Simulation time 30080891 ps
CPU time 0.83 seconds
Started Feb 29 12:42:31 PM PST 24
Finished Feb 29 12:42:32 PM PST 24
Peak memory 195584 kb
Host smart-ea48158f-7b8c-4a31-8503-82a65f290fbc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3398310547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3398310547
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2834271101
Short name T924
Test name
Test status
Simulation time 27350377 ps
CPU time 0.77 seconds
Started Feb 29 12:42:25 PM PST 24
Finished Feb 29 12:42:25 PM PST 24
Peak memory 194696 kb
Host smart-39cf83e5-564b-4bec-abcb-1cfa97dc6a0b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834271101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2834271101
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1208268511
Short name T921
Test name
Test status
Simulation time 129863543 ps
CPU time 1.33 seconds
Started Feb 29 12:42:35 PM PST 24
Finished Feb 29 12:42:37 PM PST 24
Peak memory 198312 kb
Host smart-6abd9c3c-d1fc-450c-b988-c98df83a403c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1208268511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1208268511
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1171462164
Short name T899
Test name
Test status
Simulation time 42814696 ps
CPU time 1.04 seconds
Started Feb 29 12:42:47 PM PST 24
Finished Feb 29 12:42:49 PM PST 24
Peak memory 197128 kb
Host smart-0de8ad85-2776-48be-94be-1c42f6be6d41
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171462164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1171462164
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2133833186
Short name T862
Test name
Test status
Simulation time 86010616 ps
CPU time 1.16 seconds
Started Feb 29 12:42:39 PM PST 24
Finished Feb 29 12:42:41 PM PST 24
Peak memory 198304 kb
Host smart-8d6afa72-b7d9-448b-b5ac-e646ad5b7985
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2133833186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2133833186
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3728531139
Short name T938
Test name
Test status
Simulation time 107541589 ps
CPU time 0.84 seconds
Started Feb 29 12:42:34 PM PST 24
Finished Feb 29 12:42:36 PM PST 24
Peak memory 196852 kb
Host smart-abecb4b6-c22c-419b-ad7c-c848754ae3d9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728531139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3728531139
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.80704864
Short name T848
Test name
Test status
Simulation time 112203994 ps
CPU time 1 seconds
Started Feb 29 12:42:57 PM PST 24
Finished Feb 29 12:42:58 PM PST 24
Peak memory 196732 kb
Host smart-3b3b4cca-f6ed-417c-9051-7d3fab6f474f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=80704864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.80704864
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3501490728
Short name T942
Test name
Test status
Simulation time 257476516 ps
CPU time 1.12 seconds
Started Feb 29 12:42:43 PM PST 24
Finished Feb 29 12:42:45 PM PST 24
Peak memory 197092 kb
Host smart-08347c7f-d069-478a-b029-6f544c100dba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501490728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3501490728
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.647962729
Short name T929
Test name
Test status
Simulation time 85978853 ps
CPU time 1.16 seconds
Started Feb 29 12:42:37 PM PST 24
Finished Feb 29 12:42:39 PM PST 24
Peak memory 198316 kb
Host smart-18c07bf7-f86c-4c14-8a5c-601cf62b3154
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=647962729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.647962729
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1336345981
Short name T859
Test name
Test status
Simulation time 143151546 ps
CPU time 1.27 seconds
Started Feb 29 12:42:36 PM PST 24
Finished Feb 29 12:42:37 PM PST 24
Peak memory 197256 kb
Host smart-08b19459-4bd4-4bec-b27d-b9e2296d4950
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336345981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1336345981
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3511541782
Short name T939
Test name
Test status
Simulation time 157252761 ps
CPU time 0.93 seconds
Started Feb 29 12:42:45 PM PST 24
Finished Feb 29 12:42:46 PM PST 24
Peak memory 196780 kb
Host smart-a8f6a10c-5289-4a5d-bcf0-a3d5e5b8c56f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3511541782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3511541782
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3222515530
Short name T913
Test name
Test status
Simulation time 165789619 ps
CPU time 1.12 seconds
Started Feb 29 12:42:45 PM PST 24
Finished Feb 29 12:42:46 PM PST 24
Peak memory 197128 kb
Host smart-49bd1c8d-9548-401a-8659-1794c059fa3f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222515530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3222515530
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2343539784
Short name T894
Test name
Test status
Simulation time 223239417 ps
CPU time 1.24 seconds
Started Feb 29 12:42:32 PM PST 24
Finished Feb 29 12:42:34 PM PST 24
Peak memory 197128 kb
Host smart-d590335f-d318-4a44-a814-ef184eed9a29
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2343539784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2343539784
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.178441142
Short name T861
Test name
Test status
Simulation time 225151978 ps
CPU time 1.06 seconds
Started Feb 29 12:42:50 PM PST 24
Finished Feb 29 12:42:51 PM PST 24
Peak memory 196672 kb
Host smart-b2731fa2-9a4b-4fb7-93ef-bd02b7489bb6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178441142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.178441142
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1159309933
Short name T915
Test name
Test status
Simulation time 104196461 ps
CPU time 1.51 seconds
Started Feb 29 12:42:36 PM PST 24
Finished Feb 29 12:42:38 PM PST 24
Peak memory 197140 kb
Host smart-0e06ec24-84dd-48cb-943a-920138b361a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1159309933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1159309933
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1488589980
Short name T936
Test name
Test status
Simulation time 251116789 ps
CPU time 1.05 seconds
Started Feb 29 12:42:42 PM PST 24
Finished Feb 29 12:42:44 PM PST 24
Peak memory 197040 kb
Host smart-4846146f-4438-4b4d-8b9e-dfaae4e42b37
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488589980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1488589980
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.539078879
Short name T867
Test name
Test status
Simulation time 106716312 ps
CPU time 1.04 seconds
Started Feb 29 12:42:36 PM PST 24
Finished Feb 29 12:42:38 PM PST 24
Peak memory 196720 kb
Host smart-85fb3ee6-a2e0-4af2-9200-207463716b64
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=539078879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.539078879
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.558224940
Short name T855
Test name
Test status
Simulation time 355486038 ps
CPU time 1.3 seconds
Started Feb 29 12:42:36 PM PST 24
Finished Feb 29 12:42:38 PM PST 24
Peak memory 196976 kb
Host smart-b3188439-315e-414a-bdd3-14e23467e296
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558224940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.558224940
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.749400301
Short name T917
Test name
Test status
Simulation time 509691270 ps
CPU time 1.25 seconds
Started Feb 29 12:42:28 PM PST 24
Finished Feb 29 12:42:31 PM PST 24
Peak memory 196828 kb
Host smart-c3f31df6-72db-4931-ab82-3cb9e5c84c0a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=749400301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.749400301
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1555354295
Short name T916
Test name
Test status
Simulation time 60133624 ps
CPU time 1.03 seconds
Started Feb 29 12:42:27 PM PST 24
Finished Feb 29 12:42:29 PM PST 24
Peak memory 196940 kb
Host smart-35fd7f6b-613d-43ac-b6b8-c9c85d3715d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555354295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1555354295
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.772211062
Short name T911
Test name
Test status
Simulation time 110277819 ps
CPU time 0.69 seconds
Started Feb 29 12:42:37 PM PST 24
Finished Feb 29 12:42:38 PM PST 24
Peak memory 194960 kb
Host smart-c8fdc0a3-b6a1-4927-89ab-df4e4f64e177
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=772211062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.772211062
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1389320236
Short name T907
Test name
Test status
Simulation time 112751292 ps
CPU time 1.05 seconds
Started Feb 29 12:42:39 PM PST 24
Finished Feb 29 12:42:46 PM PST 24
Peak memory 196852 kb
Host smart-511a8a9c-c9c5-4268-ba70-0d43f389f7ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389320236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1389320236
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2809193028
Short name T900
Test name
Test status
Simulation time 139412933 ps
CPU time 1.16 seconds
Started Feb 29 12:42:39 PM PST 24
Finished Feb 29 12:42:41 PM PST 24
Peak memory 196952 kb
Host smart-922a9ec4-7cad-4e84-90f5-bf662cc61d3d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2809193028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2809193028
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.446678716
Short name T901
Test name
Test status
Simulation time 40601438 ps
CPU time 0.83 seconds
Started Feb 29 12:42:32 PM PST 24
Finished Feb 29 12:42:33 PM PST 24
Peak memory 196480 kb
Host smart-ddda4b32-af1a-4d31-bb33-edd4c03ea487
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446678716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.446678716
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.129554382
Short name T926
Test name
Test status
Simulation time 40881256 ps
CPU time 0.9 seconds
Started Feb 29 12:42:43 PM PST 24
Finished Feb 29 12:42:44 PM PST 24
Peak memory 196920 kb
Host smart-4795b5c8-e35f-4c69-a619-5d96f17d5064
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=129554382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.129554382
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1683061823
Short name T940
Test name
Test status
Simulation time 89347197 ps
CPU time 1.48 seconds
Started Feb 29 12:42:35 PM PST 24
Finished Feb 29 12:42:37 PM PST 24
Peak memory 198428 kb
Host smart-5c008c78-eb7e-41fc-9e04-b39af96c7e56
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683061823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1683061823
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3377401756
Short name T853
Test name
Test status
Simulation time 590553398 ps
CPU time 1.07 seconds
Started Feb 29 12:42:39 PM PST 24
Finished Feb 29 12:42:40 PM PST 24
Peak memory 197024 kb
Host smart-423ae2de-f0a2-4930-801b-cccaecd7ac52
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3377401756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3377401756
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1632326477
Short name T906
Test name
Test status
Simulation time 45888845 ps
CPU time 0.96 seconds
Started Feb 29 12:42:37 PM PST 24
Finished Feb 29 12:42:39 PM PST 24
Peak memory 195784 kb
Host smart-bfa43891-c3f2-4536-bf5b-0539df4c27dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632326477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1632326477
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2834150223
Short name T875
Test name
Test status
Simulation time 72833133 ps
CPU time 1.28 seconds
Started Feb 29 12:42:32 PM PST 24
Finished Feb 29 12:42:34 PM PST 24
Peak memory 197296 kb
Host smart-656cc6c5-31f7-4d38-9271-c2c8851862e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2834150223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2834150223
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2993926410
Short name T908
Test name
Test status
Simulation time 81222325 ps
CPU time 0.9 seconds
Started Feb 29 12:42:24 PM PST 24
Finished Feb 29 12:42:25 PM PST 24
Peak memory 196976 kb
Host smart-674fc0eb-6fe0-42bb-8d14-7aaee45b360f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993926410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2993926410
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1138346893
Short name T914
Test name
Test status
Simulation time 71125171 ps
CPU time 1.34 seconds
Started Feb 29 12:42:35 PM PST 24
Finished Feb 29 12:42:37 PM PST 24
Peak memory 197228 kb
Host smart-c3e97a05-d00c-44b1-a7b2-d1731fe7f291
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1138346893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1138346893
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1422157328
Short name T886
Test name
Test status
Simulation time 401764743 ps
CPU time 1.18 seconds
Started Feb 29 12:42:27 PM PST 24
Finished Feb 29 12:42:29 PM PST 24
Peak memory 196796 kb
Host smart-86883038-343a-4dea-a876-202560c4f439
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422157328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1422157328
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3903028062
Short name T893
Test name
Test status
Simulation time 29882296 ps
CPU time 0.79 seconds
Started Feb 29 12:42:49 PM PST 24
Finished Feb 29 12:42:50 PM PST 24
Peak memory 195548 kb
Host smart-6a5c68b7-f301-4c5d-8af5-2c1de4da41f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3903028062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3903028062
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1166113369
Short name T927
Test name
Test status
Simulation time 29384830 ps
CPU time 0.85 seconds
Started Feb 29 12:42:30 PM PST 24
Finished Feb 29 12:42:31 PM PST 24
Peak memory 195616 kb
Host smart-087301ef-93be-4138-82f4-c48f06bac7ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166113369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1166113369
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2023093802
Short name T930
Test name
Test status
Simulation time 36019682 ps
CPU time 0.91 seconds
Started Feb 29 12:42:31 PM PST 24
Finished Feb 29 12:42:33 PM PST 24
Peak memory 197588 kb
Host smart-2a52feb0-9c6e-4f7d-88f3-ab0d7856b48f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2023093802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2023093802
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1905665768
Short name T882
Test name
Test status
Simulation time 87545533 ps
CPU time 1.33 seconds
Started Feb 29 12:42:27 PM PST 24
Finished Feb 29 12:42:29 PM PST 24
Peak memory 196040 kb
Host smart-5688b6f9-9509-4d48-8e3a-dc21f3484bc4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905665768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1905665768
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3065353324
Short name T885
Test name
Test status
Simulation time 54365698 ps
CPU time 0.77 seconds
Started Feb 29 12:42:45 PM PST 24
Finished Feb 29 12:42:47 PM PST 24
Peak memory 196748 kb
Host smart-b0aeb817-4468-47b7-8d95-118beeb7e519
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3065353324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3065353324
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.955320693
Short name T944
Test name
Test status
Simulation time 84683219 ps
CPU time 1.24 seconds
Started Feb 29 12:42:46 PM PST 24
Finished Feb 29 12:42:48 PM PST 24
Peak memory 197276 kb
Host smart-e24b35a9-31c8-40ef-91b8-6be9786ee60e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955320693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.955320693
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.782805997
Short name T879
Test name
Test status
Simulation time 193665483 ps
CPU time 0.95 seconds
Started Feb 29 12:42:40 PM PST 24
Finished Feb 29 12:42:41 PM PST 24
Peak memory 196600 kb
Host smart-7df93427-88da-44f6-88f8-e10f279f66a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=782805997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.782805997
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.345462791
Short name T904
Test name
Test status
Simulation time 139419086 ps
CPU time 1.15 seconds
Started Feb 29 12:42:29 PM PST 24
Finished Feb 29 12:42:31 PM PST 24
Peak memory 198388 kb
Host smart-b1209e34-de2a-47d0-9e10-2658112f82e7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345462791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.345462791
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3936012672
Short name T932
Test name
Test status
Simulation time 50450210 ps
CPU time 1.12 seconds
Started Feb 29 12:42:36 PM PST 24
Finished Feb 29 12:42:37 PM PST 24
Peak memory 196928 kb
Host smart-a08b8fdc-3898-4eee-a136-47dd2e55e8a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3936012672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3936012672
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3410086608
Short name T881
Test name
Test status
Simulation time 38256848 ps
CPU time 1 seconds
Started Feb 29 12:42:30 PM PST 24
Finished Feb 29 12:42:32 PM PST 24
Peak memory 195940 kb
Host smart-5fb57bb1-57b1-4723-9e7b-0e31cab1276b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410086608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3410086608
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1481974752
Short name T897
Test name
Test status
Simulation time 64013350 ps
CPU time 1.06 seconds
Started Feb 29 12:42:30 PM PST 24
Finished Feb 29 12:42:31 PM PST 24
Peak memory 196032 kb
Host smart-21815e8e-41d5-4b7d-a6c4-4441191b8a7b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1481974752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1481974752
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3775534592
Short name T891
Test name
Test status
Simulation time 234366701 ps
CPU time 1.2 seconds
Started Feb 29 12:42:43 PM PST 24
Finished Feb 29 12:42:45 PM PST 24
Peak memory 196872 kb
Host smart-b029a5f7-3a21-45b9-8df8-ff5739c92d02
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775534592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3775534592
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1011468225
Short name T864
Test name
Test status
Simulation time 427978579 ps
CPU time 1.04 seconds
Started Feb 29 12:42:37 PM PST 24
Finished Feb 29 12:42:38 PM PST 24
Peak memory 197240 kb
Host smart-1b482a5f-a61b-434d-a95b-9b7f38fc6427
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1011468225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1011468225
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2520087355
Short name T872
Test name
Test status
Simulation time 104828568 ps
CPU time 1.21 seconds
Started Feb 29 12:42:47 PM PST 24
Finished Feb 29 12:42:49 PM PST 24
Peak memory 196796 kb
Host smart-973fa14d-c6df-4424-93ae-6e4c80d6e1c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520087355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2520087355
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1206217431
Short name T877
Test name
Test status
Simulation time 139829312 ps
CPU time 1.17 seconds
Started Feb 29 12:42:35 PM PST 24
Finished Feb 29 12:42:37 PM PST 24
Peak memory 196916 kb
Host smart-849d6187-492f-40d0-bac6-4a52abeb49bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1206217431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1206217431
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4030729954
Short name T941
Test name
Test status
Simulation time 145260307 ps
CPU time 1.37 seconds
Started Feb 29 12:42:37 PM PST 24
Finished Feb 29 12:42:39 PM PST 24
Peak memory 198264 kb
Host smart-65b96eb6-5c92-404b-a09c-209c1ac7812e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030729954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4030729954
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2032213077
Short name T935
Test name
Test status
Simulation time 78118900 ps
CPU time 1.4 seconds
Started Feb 29 12:42:32 PM PST 24
Finished Feb 29 12:42:34 PM PST 24
Peak memory 197088 kb
Host smart-a2540461-0f4d-46eb-88af-40597e1ff704
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2032213077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2032213077
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3648758372
Short name T890
Test name
Test status
Simulation time 138361633 ps
CPU time 1.28 seconds
Started Feb 29 12:42:33 PM PST 24
Finished Feb 29 12:42:35 PM PST 24
Peak memory 198420 kb
Host smart-f7134110-582d-4d91-a6f9-9abf4ce423af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648758372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3648758372
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1271519146
Short name T923
Test name
Test status
Simulation time 82660106 ps
CPU time 1.38 seconds
Started Feb 29 12:42:34 PM PST 24
Finished Feb 29 12:42:36 PM PST 24
Peak memory 198624 kb
Host smart-b29fc0ee-762e-4fcc-9928-4200f5fdfb31
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1271519146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1271519146
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.345088226
Short name T892
Test name
Test status
Simulation time 173533083 ps
CPU time 0.99 seconds
Started Feb 29 12:42:48 PM PST 24
Finished Feb 29 12:42:50 PM PST 24
Peak memory 198384 kb
Host smart-5fa82b7d-ffd6-4b2e-b381-9c8957bbcef2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345088226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.345088226
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.542112473
Short name T871
Test name
Test status
Simulation time 126453404 ps
CPU time 1.03 seconds
Started Feb 29 12:42:40 PM PST 24
Finished Feb 29 12:42:41 PM PST 24
Peak memory 198436 kb
Host smart-0209753e-51d4-4d6e-8d2d-1ac777850746
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=542112473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.542112473
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.747718527
Short name T884
Test name
Test status
Simulation time 356631274 ps
CPU time 1.13 seconds
Started Feb 29 12:42:40 PM PST 24
Finished Feb 29 12:42:41 PM PST 24
Peak memory 198268 kb
Host smart-b27dfea9-0d63-46cc-9ce3-7f9fabb36065
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747718527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.747718527
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.650429459
Short name T902
Test name
Test status
Simulation time 77360948 ps
CPU time 1.1 seconds
Started Feb 29 12:42:34 PM PST 24
Finished Feb 29 12:42:35 PM PST 24
Peak memory 197216 kb
Host smart-07b06b64-6982-4bfb-b33d-1cec190929c1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=650429459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.650429459
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1716779273
Short name T905
Test name
Test status
Simulation time 149887794 ps
CPU time 1.16 seconds
Started Feb 29 12:42:35 PM PST 24
Finished Feb 29 12:42:41 PM PST 24
Peak memory 198068 kb
Host smart-8c3d147d-e704-4b51-9cf3-676ec877548e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716779273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1716779273
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2409344333
Short name T873
Test name
Test status
Simulation time 39318422 ps
CPU time 1.11 seconds
Started Feb 29 12:42:34 PM PST 24
Finished Feb 29 12:42:37 PM PST 24
Peak memory 195868 kb
Host smart-ea0c1807-eb94-4e5a-9da6-9b7d24d8cd9d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2409344333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2409344333
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2661484267
Short name T876
Test name
Test status
Simulation time 232583271 ps
CPU time 1.1 seconds
Started Feb 29 12:42:37 PM PST 24
Finished Feb 29 12:42:38 PM PST 24
Peak memory 196060 kb
Host smart-1895b847-6bc1-42a8-ae50-95b03816bde2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661484267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2661484267
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3227222336
Short name T863
Test name
Test status
Simulation time 94181495 ps
CPU time 0.85 seconds
Started Feb 29 12:42:35 PM PST 24
Finished Feb 29 12:42:36 PM PST 24
Peak memory 196528 kb
Host smart-16d81246-5c0b-4f28-ac3d-663a006d2b83
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3227222336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3227222336
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.326423522
Short name T869
Test name
Test status
Simulation time 266881905 ps
CPU time 0.98 seconds
Started Feb 29 12:42:35 PM PST 24
Finished Feb 29 12:42:36 PM PST 24
Peak memory 197040 kb
Host smart-1667ca28-0348-4cf3-a601-0758a8208fc8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326423522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.326423522
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3608946869
Short name T934
Test name
Test status
Simulation time 50678642 ps
CPU time 0.81 seconds
Started Feb 29 12:42:36 PM PST 24
Finished Feb 29 12:42:37 PM PST 24
Peak memory 195648 kb
Host smart-c0ad99e1-255a-4dbe-a7cd-7b19418e759c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3608946869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3608946869
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2304995460
Short name T909
Test name
Test status
Simulation time 170730826 ps
CPU time 1.34 seconds
Started Feb 29 12:42:39 PM PST 24
Finished Feb 29 12:42:41 PM PST 24
Peak memory 198352 kb
Host smart-be061735-6684-4bf3-84ef-7d0bb5e6552a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304995460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2304995460
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1694305383
Short name T856
Test name
Test status
Simulation time 144106350 ps
CPU time 1 seconds
Started Feb 29 12:42:38 PM PST 24
Finished Feb 29 12:42:39 PM PST 24
Peak memory 196760 kb
Host smart-64afc193-54f6-4013-bdc3-086095ea9cab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1694305383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1694305383
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3798722778
Short name T918
Test name
Test status
Simulation time 52465109 ps
CPU time 0.99 seconds
Started Feb 29 12:42:28 PM PST 24
Finished Feb 29 12:42:35 PM PST 24
Peak memory 196692 kb
Host smart-e887fcd0-ecf7-4689-a211-ec33d2cc2032
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798722778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3798722778
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.650135407
Short name T925
Test name
Test status
Simulation time 29166005 ps
CPU time 0.74 seconds
Started Feb 29 12:42:30 PM PST 24
Finished Feb 29 12:42:31 PM PST 24
Peak memory 195512 kb
Host smart-a6091b3f-a0a6-439d-ac56-5b80cbd22afa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=650135407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.650135407
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.49001750
Short name T874
Test name
Test status
Simulation time 125887789 ps
CPU time 0.94 seconds
Started Feb 29 12:42:32 PM PST 24
Finished Feb 29 12:42:33 PM PST 24
Peak memory 198464 kb
Host smart-fd6b742c-8304-48d5-ae4c-48093fba3480
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49001750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.49001750
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1653207257
Short name T910
Test name
Test status
Simulation time 76408888 ps
CPU time 1.42 seconds
Started Feb 29 12:42:34 PM PST 24
Finished Feb 29 12:42:36 PM PST 24
Peak memory 195920 kb
Host smart-48b2c093-b193-4411-976c-b87d7f8ead0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1653207257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1653207257
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1876320185
Short name T896
Test name
Test status
Simulation time 104409347 ps
CPU time 1.21 seconds
Started Feb 29 12:42:27 PM PST 24
Finished Feb 29 12:42:29 PM PST 24
Peak memory 196852 kb
Host smart-a664dda2-49d1-4518-816d-855062e6171c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876320185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1876320185
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2848753213
Short name T937
Test name
Test status
Simulation time 181580200 ps
CPU time 0.96 seconds
Started Feb 29 12:42:30 PM PST 24
Finished Feb 29 12:42:31 PM PST 24
Peak memory 196104 kb
Host smart-26927972-82b1-418d-8bb7-e0f13f4cc8af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2848753213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2848753213
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.392436309
Short name T919
Test name
Test status
Simulation time 32654928 ps
CPU time 0.81 seconds
Started Feb 29 12:42:28 PM PST 24
Finished Feb 29 12:42:30 PM PST 24
Peak memory 195744 kb
Host smart-75c68adc-28ad-45e4-b95e-888d608c48d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392436309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.392436309
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2799546445
Short name T912
Test name
Test status
Simulation time 83576394 ps
CPU time 1.21 seconds
Started Feb 29 12:42:29 PM PST 24
Finished Feb 29 12:42:31 PM PST 24
Peak memory 196896 kb
Host smart-2a8a2c99-2951-44e8-bda9-d6b167d5e1b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2799546445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2799546445
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3680482774
Short name T868
Test name
Test status
Simulation time 134988325 ps
CPU time 1.31 seconds
Started Feb 29 12:42:31 PM PST 24
Finished Feb 29 12:42:33 PM PST 24
Peak memory 196996 kb
Host smart-c57fd307-2946-4a90-bf46-61d28ddb677d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680482774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3680482774
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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