Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4129928	1			T21	61		T24	1		T25	45
all_pins[1]	4129928	1			T21	61		T24	1		T25	45
all_pins[2]	4129928	1			T21	61		T24	1		T25	45
all_pins[3]	4129928	1			T21	61		T24	1		T25	45
all_pins[4]	4129928	1			T21	61		T24	1		T25	45
all_pins[5]	4129928	1			T21	61		T24	1		T25	45
all_pins[6]	4129928	1			T21	61		T24	1		T25	45
all_pins[7]	4129928	1			T21	61		T24	1		T25	45
all_pins[8]	4129928	1			T21	61		T24	1		T25	45
all_pins[9]	4129928	1			T21	61		T24	1		T25	45
all_pins[10]	4129928	1			T21	61		T24	1		T25	45
all_pins[11]	4129928	1			T21	61		T24	1		T25	45
all_pins[12]	4129928	1			T21	61		T24	1		T25	45
all_pins[13]	4129928	1			T21	61		T24	1		T25	45
all_pins[14]	4129928	1			T21	61		T24	1		T25	45
all_pins[15]	4129928	1			T21	61		T24	1		T25	45
all_pins[16]	4129928	1			T21	61		T24	1		T25	45
all_pins[17]	4129928	1			T21	61		T24	1		T25	45
all_pins[18]	4129928	1			T21	61		T24	1		T25	45
all_pins[19]	4129928	1			T21	61		T24	1		T25	45
all_pins[20]	4129928	1			T21	61		T24	1		T25	45
all_pins[21]	4129928	1			T21	61		T24	1		T25	45
all_pins[22]	4129928	1			T21	61		T24	1		T25	45
all_pins[23]	4129928	1			T21	61		T24	1		T25	45
all_pins[24]	4129928	1			T21	61		T24	1		T25	45
all_pins[25]	4129928	1			T21	61		T24	1		T25	45
all_pins[26]	4129928	1			T21	61		T24	1		T25	45
all_pins[27]	4129928	1			T21	61		T24	1		T25	45
all_pins[28]	4129928	1			T21	61		T24	1		T25	45
all_pins[29]	4129928	1			T21	61		T24	1		T25	45
all_pins[30]	4129928	1			T21	61		T24	1		T25	45
all_pins[31]	4129928	1			T21	61		T24	1		T25	45

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	82097265	1			T21	1623		T24	32		T25	703
values[0x1]	50060431	1			T21	329		T25	737		T1	480
transitions[0x0=>0x1]	30002954	1			T21	212		T25	349		T1	290
transitions[0x1=>0x0]	30002791	1			T21	212		T25	349		T1	289

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2566035	1			T21	58		T24	1		T25	22
all_pins[0]	values[0x1]	1563893	1			T21	3		T25	23		T1	8
all_pins[0]	transitions[0x0=>0x1]	969229	1			T21	2		T25	10		T1	5
all_pins[0]	transitions[0x1=>0x0]	970079	1			T21	7		T25	12		T1	14
all_pins[1]	values[0x0]	2564976	1			T21	55		T24	1		T25	22
all_pins[1]	values[0x1]	1564952	1			T21	6		T25	23		T1	8
all_pins[1]	transitions[0x0=>0x1]	935859	1			T21	4		T25	10		T1	6
all_pins[1]	transitions[0x1=>0x0]	934800	1			T21	1		T25	10		T1	6
all_pins[2]	values[0x0]	2563811	1			T21	49		T24	1		T25	26
all_pins[2]	values[0x1]	1566117	1			T21	12		T25	19		T1	9
all_pins[2]	transitions[0x0=>0x1]	935972	1			T21	12		T25	9		T1	4
all_pins[2]	transitions[0x1=>0x0]	934807	1			T21	6		T25	13		T1	3
all_pins[3]	values[0x0]	2563387	1			T21	61		T24	1		T25	23
all_pins[3]	values[0x1]	1566541	1			T25	22		T1	20		T12	88616
all_pins[3]	transitions[0x0=>0x1]	936774	1			T25	9		T1	11		T12	53286
all_pins[3]	transitions[0x1=>0x0]	936350	1			T21	12		T25	6		T12	53314
all_pins[4]	values[0x0]	2566466	1			T21	50		T24	1		T25	27
all_pins[4]	values[0x1]	1563462	1			T21	11		T25	18		T1	12
all_pins[4]	transitions[0x0=>0x1]	935165	1			T21	11		T25	5		T1	6
all_pins[4]	transitions[0x1=>0x0]	938244	1			T25	9		T1	14		T12	53147
all_pins[5]	values[0x0]	2566534	1			T21	54		T24	1		T25	29
all_pins[5]	values[0x1]	1563394	1			T21	7		T25	16		T1	7
all_pins[5]	transitions[0x0=>0x1]	935444	1			T21	5		T25	12		T1	4
all_pins[5]	transitions[0x1=>0x0]	935512	1			T21	9		T25	14		T1	9
all_pins[6]	values[0x0]	2562100	1			T21	58		T24	1		T25	18
all_pins[6]	values[0x1]	1567828	1			T21	3		T25	27		T1	21
all_pins[6]	transitions[0x0=>0x1]	939618	1			T25	16		T1	17		T12	52431
all_pins[6]	transitions[0x1=>0x0]	935184	1			T21	4		T25	5		T1	3
all_pins[7]	values[0x0]	2565422	1			T21	43		T24	1		T25	26
all_pins[7]	values[0x1]	1564506	1			T21	18		T25	19		T1	25
all_pins[7]	transitions[0x0=>0x1]	936459	1			T21	18		T25	10		T1	16
all_pins[7]	transitions[0x1=>0x0]	939781	1			T21	3		T25	18		T1	12
all_pins[8]	values[0x0]	2566645	1			T21	50		T24	1		T25	20
all_pins[8]	values[0x1]	1563283	1			T21	11		T25	25		T1	20
all_pins[8]	transitions[0x0=>0x1]	934775	1			T21	2		T25	15		T1	9
all_pins[8]	transitions[0x1=>0x0]	935998	1			T21	9		T25	9		T1	14
all_pins[9]	values[0x0]	2563618	1			T21	48		T24	1		T25	24
all_pins[9]	values[0x1]	1566310	1			T21	13		T25	21		T1	7
all_pins[9]	transitions[0x0=>0x1]	938633	1			T21	7		T25	9		T1	4
all_pins[9]	transitions[0x1=>0x0]	935606	1			T21	5		T25	13		T1	17
all_pins[10]	values[0x0]	2561868	1			T21	46		T24	1		T25	23
all_pins[10]	values[0x1]	1568060	1			T21	15		T25	22		T1	1
all_pins[10]	transitions[0x0=>0x1]	940408	1			T21	6		T25	9		T1	1
all_pins[10]	transitions[0x1=>0x0]	938658	1			T21	4		T25	8		T1	7
all_pins[11]	values[0x0]	2564979	1			T21	56		T24	1		T25	19
all_pins[11]	values[0x1]	1564949	1			T21	5		T25	26		T1	19
all_pins[11]	transitions[0x0=>0x1]	937145	1			T21	1		T25	13		T1	19
all_pins[11]	transitions[0x1=>0x0]	940256	1			T21	11		T25	9		T1	1
all_pins[12]	values[0x0]	2566938	1			T21	35		T24	1		T25	16
all_pins[12]	values[0x1]	1562990	1			T21	26		T25	29		T1	11
all_pins[12]	transitions[0x0=>0x1]	934555	1			T21	21		T25	11		T1	3
all_pins[12]	transitions[0x1=>0x0]	936514	1			T25	8		T1	11		T12	53552
all_pins[13]	values[0x0]	2560541	1			T21	54		T24	1		T25	22
all_pins[13]	values[0x1]	1569387	1			T21	7		T25	23		T1	27
all_pins[13]	transitions[0x0=>0x1]	941483	1			T21	2		T25	5		T1	25
all_pins[13]	transitions[0x1=>0x0]	935086	1			T21	21		T25	11		T1	9
all_pins[14]	values[0x0]	2569835	1			T21	59		T24	1		T25	20
all_pins[14]	values[0x1]	1560093	1			T21	2		T25	25		T1	22
all_pins[14]	transitions[0x0=>0x1]	931331	1			T25	14		T12	51764		T13	9761
all_pins[14]	transitions[0x1=>0x0]	940625	1			T21	5		T25	12		T1	5
all_pins[15]	values[0x0]	2561850	1			T21	54		T24	1		T25	20
all_pins[15]	values[0x1]	1568078	1			T21	7		T25	25		T1	3
all_pins[15]	transitions[0x0=>0x1]	940409	1			T21	7		T25	11		T1	1
all_pins[15]	transitions[0x1=>0x0]	932424	1			T21	2		T25	11		T1	20
all_pins[16]	values[0x0]	2562053	1			T21	47		T24	1		T25	20
all_pins[16]	values[0x1]	1567875	1			T21	14		T25	25		T1	14
all_pins[16]	transitions[0x0=>0x1]	936577	1			T21	13		T25	13		T1	13
all_pins[16]	transitions[0x1=>0x0]	936780	1			T21	6		T25	13		T1	2
all_pins[17]	values[0x0]	2570906	1			T21	48		T24	1		T25	20
all_pins[17]	values[0x1]	1559022	1			T21	13		T25	25		T1	14
all_pins[17]	transitions[0x0=>0x1]	932995	1			T21	10		T25	9		T1	11
all_pins[17]	transitions[0x1=>0x0]	941848	1			T21	11		T25	9		T1	11
all_pins[18]	values[0x0]	2564358	1			T21	47		T24	1		T25	14
all_pins[18]	values[0x1]	1565570	1			T21	14		T25	31		T1	31
all_pins[18]	transitions[0x0=>0x1]	941167	1			T21	8		T25	14		T1	24
all_pins[18]	transitions[0x1=>0x0]	934619	1			T21	7		T25	8		T1	7
all_pins[19]	values[0x0]	2560919	1			T21	47		T24	1		T25	24
all_pins[19]	values[0x1]	1569009	1			T21	14		T25	21		T1	17
all_pins[19]	transitions[0x0=>0x1]	941592	1			T21	2		T25	7		T1	1
all_pins[19]	transitions[0x1=>0x0]	938153	1			T21	2		T25	17		T1	15
all_pins[20]	values[0x0]	2565334	1			T21	52		T24	1		T25	20
all_pins[20]	values[0x1]	1564594	1			T21	9		T25	25		T1	23
all_pins[20]	transitions[0x0=>0x1]	932360	1			T21	4		T25	14		T1	9
all_pins[20]	transitions[0x1=>0x0]	936775	1			T21	9		T25	10		T1	3
all_pins[21]	values[0x0]	2563728	1			T21	49		T24	1		T25	22
all_pins[21]	values[0x1]	1566200	1			T21	12		T25	23		T1	16
all_pins[21]	transitions[0x0=>0x1]	938559	1			T21	10		T25	9		T1	9
all_pins[21]	transitions[0x1=>0x0]	936953	1			T21	7		T25	11		T1	16
all_pins[22]	values[0x0]	2565329	1			T21	59		T24	1		T25	22
all_pins[22]	values[0x1]	1564599	1			T21	2		T25	23		T1	17
all_pins[22]	transitions[0x0=>0x1]	936665	1			T21	2		T25	13		T1	13
all_pins[22]	transitions[0x1=>0x0]	938266	1			T21	12		T25	13		T1	12
all_pins[23]	values[0x0]	2570976	1			T21	47		T24	1		T25	26
all_pins[23]	values[0x1]	1558952	1			T21	14		T25	19		T1	7
all_pins[23]	transitions[0x0=>0x1]	930682	1			T21	14		T25	10		T1	4
all_pins[23]	transitions[0x1=>0x0]	936329	1			T21	2		T25	14		T1	14
all_pins[24]	values[0x0]	2564248	1			T21	49		T24	1		T25	23
all_pins[24]	values[0x1]	1565680	1			T21	12		T25	22		T1	9
all_pins[24]	transitions[0x0=>0x1]	940134	1			T21	6		T25	14		T1	8
all_pins[24]	transitions[0x1=>0x0]	933406	1			T21	8		T25	11		T1	6
all_pins[25]	values[0x0]	2571786	1			T21	47		T24	1		T25	24
all_pins[25]	values[0x1]	1558142	1			T21	14		T25	21		T1	12
all_pins[25]	transitions[0x0=>0x1]	931484	1			T21	2		T25	9		T1	6
all_pins[25]	transitions[0x1=>0x0]	939022	1			T25	10		T1	3		T12	53041
all_pins[26]	values[0x0]	2566454	1			T21	48		T24	1		T25	17
all_pins[26]	values[0x1]	1563474	1			T21	13		T25	28		T1	30
all_pins[26]	transitions[0x0=>0x1]	939559	1			T21	8		T25	16		T1	20
all_pins[26]	transitions[0x1=>0x0]	934227	1			T21	9		T25	9		T1	2
all_pins[27]	values[0x0]	2568520	1			T21	51		T24	1		T25	26
all_pins[27]	values[0x1]	1561408	1			T21	10		T25	19		T1	18
all_pins[27]	transitions[0x0=>0x1]	933977	1			T21	6		T25	6		T1	7
all_pins[27]	transitions[0x1=>0x0]	936043	1			T21	9		T25	15		T1	19
all_pins[28]	values[0x0]	2567803	1			T21	48		T24	1		T25	29
all_pins[28]	values[0x1]	1562125	1			T21	13		T25	16		T1	8
all_pins[28]	transitions[0x0=>0x1]	934588	1			T21	10		T25	8		T1	8
all_pins[28]	transitions[0x1=>0x0]	933871	1			T21	7		T25	11		T1	18
all_pins[29]	values[0x0]	2570475	1			T21	55		T24	1		T25	18
all_pins[29]	values[0x1]	1559453	1			T21	6		T25	27		T1	15
all_pins[29]	transitions[0x0=>0x1]	936153	1			T21	2		T25	16		T1	8
all_pins[29]	transitions[0x1=>0x0]	938825	1			T21	9		T25	5		T1	1
all_pins[30]	values[0x0]	2564349	1			T21	46		T24	1		T25	21
all_pins[30]	values[0x1]	1565579	1			T21	15		T25	24		T1	11
all_pins[30]	transitions[0x0=>0x1]	937507	1			T21	13		T25	11		T1	8
all_pins[30]	transitions[0x1=>0x0]	931381	1			T21	4		T25	14		T1	12
all_pins[31]	values[0x0]	2565022	1			T21	53		T24	1		T25	20
all_pins[31]	values[0x1]	1564906	1			T21	8		T25	25		T1	18
all_pins[31]	transitions[0x0=>0x1]	935696	1			T21	4		T25	12		T1	10
all_pins[31]	transitions[0x1=>0x0]	936369	1			T21	11		T25	11		T1	3