Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13763098	1			T21	82		T24	1		T25	23163
all_values[1]	13763098	1			T21	82		T24	1		T25	23163
all_values[2]	13763098	1			T21	82		T24	1		T25	23163
all_values[3]	13763098	1			T21	82		T24	1		T25	23163
all_values[4]	13763098	1			T21	82		T24	1		T25	23163
all_values[5]	13763098	1			T21	82		T24	1		T25	23163
all_values[6]	13763098	1			T21	82		T24	1		T25	23163
all_values[7]	13763098	1			T21	82		T24	1		T25	23163
all_values[8]	13763098	1			T21	82		T24	1		T25	23163
all_values[9]	13763098	1			T21	82		T24	1		T25	23163
all_values[10]	13763098	1			T21	82		T24	1		T25	23163
all_values[11]	13763098	1			T21	82		T24	1		T25	23163
all_values[12]	13763098	1			T21	82		T24	1		T25	23163
all_values[13]	13763098	1			T21	82		T24	1		T25	23163
all_values[14]	13763098	1			T21	82		T24	1		T25	23163
all_values[15]	13763098	1			T21	82		T24	1		T25	23163
all_values[16]	13763098	1			T21	82		T24	1		T25	23163
all_values[17]	13763098	1			T21	82		T24	1		T25	23163
all_values[18]	13763098	1			T21	82		T24	1		T25	23163
all_values[19]	13763098	1			T21	82		T24	1		T25	23163
all_values[20]	13763098	1			T21	82		T24	1		T25	23163
all_values[21]	13763098	1			T21	82		T24	1		T25	23163
all_values[22]	13763098	1			T21	82		T24	1		T25	23163
all_values[23]	13763098	1			T21	82		T24	1		T25	23163
all_values[24]	13763098	1			T21	82		T24	1		T25	23163
all_values[25]	13763098	1			T21	82		T24	1		T25	23163
all_values[26]	13763098	1			T21	82		T24	1		T25	23163
all_values[27]	13763098	1			T21	82		T24	1		T25	23163
all_values[28]	13763098	1			T21	82		T24	1		T25	23163
all_values[29]	13763098	1			T21	82		T24	1		T25	23163
all_values[30]	13763098	1			T21	82		T24	1		T25	23163
all_values[31]	13763098	1			T21	82		T24	1		T25	23163

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

252983727

1

T21

1717

T24

32

T25

741216

auto[1]

187435409

1

T21

907

T1

2203

T12

109836

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101319306

1

T21

1485

T24

32

T25

741216

auto[1]

339099830

1

T21

1139

T1

4057

T12

199945

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

435648162

1

T21

2449

T24

32

T25

741216

auto[1]

4770974

1

T21

175

T1

162

T12

292617

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2606868	1			T21	21		T24	1		T25	23163
all_values[0]	auto[0]	auto[0]	auto[1]	5235136	1			T21	28		T1	31		T12	308650
all_values[0]	auto[0]	auto[1]	auto[0]	570784	1			T21	23		T1	39		T12	31964
all_values[0]	auto[0]	auto[1]	auto[1]	5201263	1			T21	4		T1	60		T12	307022
all_values[0]	auto[1]	auto[0]	auto[1]	74567	1			T21	3		T1	2		T12	4527
all_values[0]	auto[1]	auto[1]	auto[1]	74480	1			T21	3		T1	2		T12	4654
all_values[1]	auto[0]	auto[0]	auto[0]	2605764	1			T21	33		T24	1		T25	23163
all_values[1]	auto[0]	auto[0]	auto[1]	5229133	1			T21	17		T1	91		T12	313853
all_values[1]	auto[0]	auto[1]	auto[0]	566601	1			T21	18		T1	4		T12	30685
all_values[1]	auto[0]	auto[1]	auto[1]	5212499	1			T21	7		T1	29		T12	303302
all_values[1]	auto[1]	auto[0]	auto[1]	75034	1			T21	4		T1	3		T12	4596
all_values[1]	auto[1]	auto[1]	auto[1]	74067	1			T21	3		T1	4		T12	4509
all_values[2]	auto[0]	auto[0]	auto[0]	2607076	1			T21	39		T24	1		T25	23163
all_values[2]	auto[0]	auto[0]	auto[1]	5198708	1			T21	20		T1	98		T12	306122
all_values[2]	auto[0]	auto[1]	auto[0]	572645	1			T21	2		T1	7		T12	31342
all_values[2]	auto[0]	auto[1]	auto[1]	5235798	1			T21	15		T1	17		T12	311493
all_values[2]	auto[1]	auto[0]	auto[1]	74335	1			T21	4		T1	2		T12	4670
all_values[2]	auto[1]	auto[1]	auto[1]	74536	1			T21	2		T1	1		T12	4499
all_values[3]	auto[0]	auto[0]	auto[0]	2596197	1			T21	38		T24	1		T25	23163
all_values[3]	auto[0]	auto[0]	auto[1]	5245325	1			T21	28		T1	69		T12	305380
all_values[3]	auto[0]	auto[1]	auto[0]	565331	1			T21	11		T1	1		T12	32101
all_values[3]	auto[0]	auto[1]	auto[1]	5206949	1			T1	48		T12	310197		T13	50362
all_values[3]	auto[1]	auto[0]	auto[1]	75039	1			T21	5		T1	3		T12	4614
all_values[3]	auto[1]	auto[1]	auto[1]	74257	1			T1	4		T12	4596		T13	1000
all_values[4]	auto[0]	auto[0]	auto[0]	2594080	1			T21	30		T24	1		T25	23163
all_values[4]	auto[0]	auto[0]	auto[1]	5272580	1			T21	23		T1	84		T12	317079
all_values[4]	auto[0]	auto[1]	auto[0]	565883	1			T21	8		T1	3		T12	31218
all_values[4]	auto[0]	auto[1]	auto[1]	5181394	1			T21	14		T1	42		T12	299981
all_values[4]	auto[1]	auto[0]	auto[1]	74783	1			T21	4		T1	3		T12	4648
all_values[4]	auto[1]	auto[1]	auto[1]	74378	1			T21	3		T1	2		T12	4546
all_values[5]	auto[0]	auto[0]	auto[0]	2602970	1			T21	48		T24	1		T25	23163
all_values[5]	auto[0]	auto[0]	auto[1]	5222236	1			T21	10		T1	67		T12	310248
all_values[5]	auto[0]	auto[1]	auto[0]	557713	1			T21	1		T1	14		T12	33185
all_values[5]	auto[0]	auto[1]	auto[1]	5230856	1			T21	15		T1	42		T12	301963
all_values[5]	auto[1]	auto[0]	auto[1]	74606	1			T21	5		T1	6		T12	4675
all_values[5]	auto[1]	auto[1]	auto[1]	74717	1			T21	3		T1	1		T12	4475
all_values[6]	auto[0]	auto[0]	auto[0]	2600870	1			T21	42		T24	1		T25	23163
all_values[6]	auto[0]	auto[0]	auto[1]	5235876	1			T21	20		T1	62		T12	308442
all_values[6]	auto[0]	auto[1]	auto[0]	560749	1			T21	7		T1	9		T12	31743
all_values[6]	auto[0]	auto[1]	auto[1]	5216620	1			T21	8		T1	57		T12	309006
all_values[6]	auto[1]	auto[0]	auto[1]	74716	1			T21	5		T1	2		T12	4642
all_values[6]	auto[1]	auto[1]	auto[1]	74267	1			T1	3		T12	4541		T13	982
all_values[7]	auto[0]	auto[0]	auto[0]	2601533	1			T21	27		T24	1		T25	23163
all_values[7]	auto[0]	auto[0]	auto[1]	5218861	1			T21	20		T1	24		T12	309172
all_values[7]	auto[0]	auto[1]	auto[0]	564013	1			T21	16		T1	7		T12	32280
all_values[7]	auto[0]	auto[1]	auto[1]	5229651	1			T21	14		T1	105		T12	306180
all_values[7]	auto[1]	auto[0]	auto[1]	74616	1			T21	1		T1	2		T12	4526
all_values[7]	auto[1]	auto[1]	auto[1]	74424	1			T21	4		T1	3		T12	4526
all_values[8]	auto[0]	auto[0]	auto[0]	2607414	1			T21	28		T24	1		T25	23163
all_values[8]	auto[0]	auto[0]	auto[1]	5246908	1			T21	12		T1	57		T12	305141
all_values[8]	auto[0]	auto[1]	auto[0]	563043	1			T21	24		T12	31696		T13	5660
all_values[8]	auto[0]	auto[1]	auto[1]	5196768	1			T21	14		T1	79		T12	311006
all_values[8]	auto[1]	auto[0]	auto[1]	74720	1			T21	2		T1	1		T12	4507
all_values[8]	auto[1]	auto[1]	auto[1]	74245	1			T21	2		T1	3		T12	4501
all_values[9]	auto[0]	auto[0]	auto[0]	2604224	1			T21	41		T24	1		T25	23163
all_values[9]	auto[0]	auto[0]	auto[1]	5197529	1			T21	19		T1	82		T12	305844
all_values[9]	auto[0]	auto[1]	auto[0]	572484	1			T21	4		T1	7		T12	31895
all_values[9]	auto[0]	auto[1]	auto[1]	5239803	1			T21	13		T1	40		T12	308757
all_values[9]	auto[1]	auto[0]	auto[1]	74314	1			T21	2		T1	4		T12	4583
all_values[9]	auto[1]	auto[1]	auto[1]	74744	1			T21	3		T1	3		T12	4478
all_values[10]	auto[0]	auto[0]	auto[0]	2603377	1			T21	34		T24	1		T25	23163
all_values[10]	auto[0]	auto[0]	auto[1]	5236925	1			T21	8		T1	100		T12	306680
all_values[10]	auto[0]	auto[1]	auto[0]	560828	1			T21	11		T1	8		T12	33093
all_values[10]	auto[0]	auto[1]	auto[1]	5212924	1			T21	22		T1	20		T12	309488
all_values[10]	auto[1]	auto[0]	auto[1]	74496	1			T21	4		T1	5		T12	4583
all_values[10]	auto[1]	auto[1]	auto[1]	74548	1			T21	3		T1	1		T12	4556
all_values[11]	auto[0]	auto[0]	auto[0]	2605446	1			T21	30		T24	1		T25	23163
all_values[11]	auto[0]	auto[0]	auto[1]	5230416	1			T21	27		T1	48		T12	301451
all_values[11]	auto[0]	auto[1]	auto[0]	559342	1			T21	15		T12	32619		T13	5810
all_values[11]	auto[0]	auto[1]	auto[1]	5219022	1			T21	6		T1	87		T12	314588
all_values[11]	auto[1]	auto[0]	auto[1]	74655	1			T21	1		T1	2		T12	4607
all_values[11]	auto[1]	auto[1]	auto[1]	74217	1			T21	3		T1	2		T12	4509
all_values[12]	auto[0]	auto[0]	auto[0]	2610331	1			T21	22		T24	1		T25	23163
all_values[12]	auto[0]	auto[0]	auto[1]	5240295	1			T21	13		T1	65		T12	312326
all_values[12]	auto[0]	auto[1]	auto[0]	559683	1			T21	14		T12	33504		T13	5770
all_values[12]	auto[0]	auto[1]	auto[1]	5203999	1			T21	26		T1	71		T12	299342
all_values[12]	auto[1]	auto[0]	auto[1]	74617	1			T21	1		T1	3		T12	4672
all_values[12]	auto[1]	auto[1]	auto[1]	74173	1			T21	6		T1	1		T12	4446
all_values[13]	auto[0]	auto[0]	auto[0]	2597246	1			T21	35		T24	1		T25	23163
all_values[13]	auto[0]	auto[0]	auto[1]	5206041	1			T21	19		T1	54		T12	314372
all_values[13]	auto[0]	auto[1]	auto[0]	560106	1			T21	10		T1	1		T12	30684
all_values[13]	auto[0]	auto[1]	auto[1]	5250105	1			T21	11		T1	83		T12	304168
all_values[13]	auto[1]	auto[0]	auto[1]	74560	1			T21	3		T1	2		T12	4562
all_values[13]	auto[1]	auto[1]	auto[1]	75040	1			T21	4		T1	1		T12	4612
all_values[14]	auto[0]	auto[0]	auto[0]	2613284	1			T21	43		T24	1		T25	23163
all_values[14]	auto[0]	auto[0]	auto[1]	5236045	1			T21	21		T1	68		T12	306709
all_values[14]	auto[0]	auto[1]	auto[0]	563335	1			T21	8		T1	1		T12	31888
all_values[14]	auto[0]	auto[1]	auto[1]	5201245	1			T21	4		T1	59		T12	305926
all_values[14]	auto[1]	auto[0]	auto[1]	74851	1			T21	6		T1	4		T12	4485
all_values[14]	auto[1]	auto[1]	auto[1]	74338	1			T1	3		T12	4616		T13	1011
all_values[15]	auto[0]	auto[0]	auto[0]	2602048	1			T21	30		T24	1		T25	23163
all_values[15]	auto[0]	auto[0]	auto[1]	5186835	1			T21	13		T1	107		T12	308458
all_values[15]	auto[0]	auto[1]	auto[0]	564162	1			T21	21		T1	5		T12	33288
all_values[15]	auto[0]	auto[1]	auto[1]	5261436	1			T21	11		T1	19		T12	307890
all_values[15]	auto[1]	auto[0]	auto[1]	74550	1			T21	4		T1	7		T12	4478
all_values[15]	auto[1]	auto[1]	auto[1]	74067	1			T21	3		T1	1		T12	4591
all_values[16]	auto[0]	auto[0]	auto[0]	2601549	1			T21	33		T24	1		T25	23163
all_values[16]	auto[0]	auto[0]	auto[1]	5260883	1			T21	20		T1	73		T12	312317
all_values[16]	auto[0]	auto[1]	auto[0]	556942	1			T21	6		T1	4		T12	30949
all_values[16]	auto[0]	auto[1]	auto[1]	5194306	1			T21	17		T1	46		T12	305331
all_values[16]	auto[1]	auto[0]	auto[1]	75163	1			T21	2		T1	5		T12	4603
all_values[16]	auto[1]	auto[1]	auto[1]	74255	1			T21	4		T1	2		T12	4568
all_values[17]	auto[0]	auto[0]	auto[0]	2604865	1			T21	40		T24	1		T25	23163
all_values[17]	auto[0]	auto[0]	auto[1]	5249124	1			T21	11		T1	52		T12	314512
all_values[17]	auto[0]	auto[1]	auto[0]	571352	1			T21	16		T1	28		T12	33359
all_values[17]	auto[0]	auto[1]	auto[1]	5189070	1			T21	11		T1	50		T12	299955
all_values[17]	auto[1]	auto[0]	auto[1]	75026	1			T21	2		T1	2		T12	4570
all_values[17]	auto[1]	auto[1]	auto[1]	73661	1			T21	2		T1	1		T12	4625
all_values[18]	auto[0]	auto[0]	auto[0]	2594390	1			T21	28		T24	1		T25	23163
all_values[18]	auto[0]	auto[0]	auto[1]	5241893	1			T21	7		T1	19		T12	313291
all_values[18]	auto[0]	auto[1]	auto[0]	568072	1			T21	21		T1	1		T12	34430
all_values[18]	auto[0]	auto[1]	auto[1]	5209160	1			T21	19		T1	116		T12	300804
all_values[18]	auto[1]	auto[0]	auto[1]	74842	1			T21	2		T1	1		T12	4625
all_values[18]	auto[1]	auto[1]	auto[1]	74741	1			T21	5		T1	4		T12	4533
all_values[19]	auto[0]	auto[0]	auto[0]	2596859	1			T21	24		T24	1		T25	23163
all_values[19]	auto[0]	auto[0]	auto[1]	5231504	1			T21	14		T1	80		T12	310970
all_values[19]	auto[0]	auto[1]	auto[0]	562645	1			T21	17		T12	32561		T13	5614
all_values[19]	auto[0]	auto[1]	auto[1]	5223434	1			T21	23		T1	53		T12	301908
all_values[19]	auto[1]	auto[0]	auto[1]	74023	1			T1	4		T12	4467		T13	972
all_values[19]	auto[1]	auto[1]	auto[1]	74633	1			T21	4		T12	4534		T13	974
all_values[20]	auto[0]	auto[0]	auto[0]	2588522	1			T21	27		T24	1		T25	23163
all_values[20]	auto[0]	auto[0]	auto[1]	5230900	1			T21	16		T1	67		T12	301225
all_values[20]	auto[0]	auto[1]	auto[0]	564635	1			T21	21		T12	32855		T13	5964
all_values[20]	auto[0]	auto[1]	auto[1]	5229828	1			T21	13		T1	66		T12	314435
all_values[20]	auto[1]	auto[0]	auto[1]	74660	1			T21	3		T1	4		T12	4513
all_values[20]	auto[1]	auto[1]	auto[1]	74553	1			T21	2		T1	3		T12	4657
all_values[21]	auto[0]	auto[0]	auto[0]	2598585	1			T21	43		T24	1		T25	23163
all_values[21]	auto[0]	auto[0]	auto[1]	5210333	1			T21	4		T1	17		T12	314064
all_values[21]	auto[0]	auto[1]	auto[0]	568168	1			T21	21		T1	28		T12	32824
all_values[21]	auto[0]	auto[1]	auto[1]	5236948	1			T21	11		T1	81		T12	301380
all_values[21]	auto[1]	auto[0]	auto[1]	74342	1			T21	1		T1	1		T12	4686
all_values[21]	auto[1]	auto[1]	auto[1]	74722	1			T21	2		T1	5		T12	4521
all_values[22]	auto[0]	auto[0]	auto[0]	2604166	1			T21	39		T24	1		T25	23163
all_values[22]	auto[0]	auto[0]	auto[1]	5191236	1			T21	36		T1	59		T12	303331
all_values[22]	auto[0]	auto[1]	auto[0]	562210	1			T21	3		T1	1		T12	30444
all_values[22]	auto[0]	auto[1]	auto[1]	5256349	1			T21	1		T1	73		T12	315658
all_values[22]	auto[1]	auto[0]	auto[1]	74651	1			T21	2		T1	3		T12	4485
all_values[22]	auto[1]	auto[1]	auto[1]	74486	1			T21	1		T1	4		T12	4559
all_values[23]	auto[0]	auto[0]	auto[0]	2598885	1			T21	30		T24	1		T25	23163
all_values[23]	auto[0]	auto[0]	auto[1]	5230371	1			T21	14		T1	80		T12	314616
all_values[23]	auto[0]	auto[1]	auto[0]	561579	1			T21	13		T1	10		T12	35644
all_values[23]	auto[0]	auto[1]	auto[1]	5222648	1			T21	20		T1	44		T12	298765
all_values[23]	auto[1]	auto[0]	auto[1]	74936	1			T21	2		T1	4		T12	4584
all_values[23]	auto[1]	auto[1]	auto[1]	74679	1			T21	3		T1	2		T12	4494
all_values[24]	auto[0]	auto[0]	auto[0]	2606128	1			T21	31		T24	1		T25	23163
all_values[24]	auto[0]	auto[0]	auto[1]	5209091	1			T21	24		T1	114		T12	319835
all_values[24]	auto[0]	auto[1]	auto[0]	570349	1			T21	9		T1	3		T12	30664
all_values[24]	auto[0]	auto[1]	auto[1]	5228557	1			T21	12		T1	11		T12	296656
all_values[24]	auto[1]	auto[0]	auto[1]	74374	1			T21	3		T1	1		T12	4566
all_values[24]	auto[1]	auto[1]	auto[1]	74599	1			T21	3		T1	2		T12	4707
all_values[25]	auto[0]	auto[0]	auto[0]	2599969	1			T21	29		T24	1		T25	23163
all_values[25]	auto[0]	auto[0]	auto[1]	5234580	1			T21	15		T1	74		T12	306780
all_values[25]	auto[0]	auto[1]	auto[0]	568754	1			T21	13		T1	1		T12	32907
all_values[25]	auto[0]	auto[1]	auto[1]	5210415	1			T21	20		T1	61		T12	308664
all_values[25]	auto[1]	auto[0]	auto[1]	74924	1			T21	3		T1	4		T12	4584
all_values[25]	auto[1]	auto[1]	auto[1]	74456	1			T21	2		T1	1		T12	4685
all_values[26]	auto[0]	auto[0]	auto[0]	2599669	1			T21	34		T24	1		T25	23163
all_values[26]	auto[0]	auto[0]	auto[1]	5248363	1			T21	13		T1	19		T12	308334
all_values[26]	auto[0]	auto[1]	auto[0]	562647	1			T21	21		T1	1		T12	33469
all_values[26]	auto[0]	auto[1]	auto[1]	5203228	1			T21	10		T1	116		T12	307722
all_values[26]	auto[1]	auto[0]	auto[1]	74844	1			T21	2		T1	2		T12	4597
all_values[26]	auto[1]	auto[1]	auto[1]	74347	1			T21	2		T1	3		T12	4591
all_values[27]	auto[0]	auto[0]	auto[0]	2593305	1			T21	38		T24	1		T25	23163
all_values[27]	auto[0]	auto[0]	auto[1]	5244370	1			T21	11		T1	70		T12	307117
all_values[27]	auto[0]	auto[1]	auto[0]	568161	1			T21	14		T1	1		T12	33414
all_values[27]	auto[0]	auto[1]	auto[1]	5208394	1			T21	14		T1	64		T12	307794
all_values[27]	auto[1]	auto[0]	auto[1]	74673	1			T21	3		T12	4688		T13	1047
all_values[27]	auto[1]	auto[1]	auto[1]	74195	1			T21	2		T1	6		T12	4463
all_values[28]	auto[0]	auto[0]	auto[0]	2605723	1			T21	35		T24	1		T25	23163
all_values[28]	auto[0]	auto[0]	auto[1]	5223565	1			T21	14		T1	54		T12	310246
all_values[28]	auto[0]	auto[1]	auto[0]	562556	1			T21	16		T1	26		T12	32205
all_values[28]	auto[0]	auto[1]	auto[1]	5221916	1			T21	13		T1	50		T12	306130
all_values[28]	auto[1]	auto[0]	auto[1]	74930	1			T21	3		T1	3		T12	4620
all_values[28]	auto[1]	auto[1]	auto[1]	74408	1			T21	1		T1	1		T12	4650
all_values[29]	auto[0]	auto[0]	auto[0]	2599682	1			T21	35		T24	1		T25	23163
all_values[29]	auto[0]	auto[0]	auto[1]	5252447	1			T21	28		T1	37		T12	312366
all_values[29]	auto[0]	auto[1]	auto[0]	566199	1			T21	6		T1	7		T12	32412
all_values[29]	auto[0]	auto[1]	auto[1]	5195776	1			T21	8		T1	79		T12	304666
all_values[29]	auto[1]	auto[0]	auto[1]	74731	1			T21	3		T1	1		T12	4654
all_values[29]	auto[1]	auto[1]	auto[1]	74263	1			T21	2		T1	1		T12	4518
all_values[30]	auto[0]	auto[0]	auto[0]	2600140	1			T21	32		T24	1		T25	23163
all_values[30]	auto[0]	auto[0]	auto[1]	5241015	1			T21	18		T1	52		T12	307394
all_values[30]	auto[0]	auto[1]	auto[0]	564676	1			T21	9		T1	39		T12	32037
all_values[30]	auto[0]	auto[1]	auto[1]	5207969	1			T21	17		T1	37		T12	309912
all_values[30]	auto[1]	auto[0]	auto[1]	74790	1			T21	4		T1	1		T12	4541
all_values[30]	auto[1]	auto[1]	auto[1]	74508	1			T21	2		T1	3		T12	4662
all_values[31]	auto[0]	auto[0]	auto[0]	2600456	1			T21	30		T24	1		T25	23163
all_values[31]	auto[0]	auto[0]	auto[1]	5204077	1			T21	12		T1	62		T12	305541
all_values[31]	auto[0]	auto[1]	auto[0]	562038	1			T21	17		T1	13		T12	34376
all_values[31]	auto[0]	auto[1]	auto[1]	5247925	1			T21	16		T1	54		T12	310000
all_values[31]	auto[1]	auto[0]	auto[1]	74137	1			T21	4		T12	4590		T13	955
all_values[31]	auto[1]	auto[1]	auto[1]	74465	1			T21	3		T1	2		T12	4447

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal