Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[1]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[2]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[3]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[4]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[5]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[6]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[7]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[8]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[9]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[10]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[11]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[12]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[13]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[14]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[15]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[16]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[17]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[18]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[19]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[20]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[21]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[22]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[23]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[24]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[25]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[26]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[27]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[28]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[29]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[30]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[31]	13544545	1			T21	131		T24	1		T25	23163

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262655770

1

T21

2267

T24

32

T25

369315

auto[1]

170769670

1

T21

1925

T25

371901

T1

3633

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

348187873

1

T21

3970

T24

32

T25

741216

auto[1]

85237567

1

T21

222

T1

1818

T11

4067

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

322889319

1

T21

3222

T24

32

T25

741216

auto[1]

110536121

1

T21

970

T1

2264

T11

9011

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5119659	1			T21	60		T24	1		T25	10950
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3640108	1			T21	68		T25	12213		T1	89
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1339836	1			T21	3		T1	22		T11	69
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1760804	1			T11	203		T12	121472		T13	22697
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	361000	1			T1	24		T11	43		T12	8575
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1323138	1			T1	4		T11	72		T12	82128
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5098872	1			T21	66		T24	1		T25	11018
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3646880	1			T21	33		T25	12145		T1	29
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1341076	1			T21	2		T1	38		T11	61
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1770874	1			T21	5		T1	3		T11	202
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	361488	1			T21	10		T1	50		T11	36
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1325355	1			T21	15		T1	31		T11	41
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5097558	1			T21	47		T24	1		T25	12411
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3645860	1			T21	37		T25	10752		T1	36
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1340744	1			T21	1		T1	21		T11	82
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1768116	1			T21	32		T1	8		T11	166
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	361697	1			T21	8		T1	20		T11	20
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1330570	1			T21	6		T1	67		T11	51
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5108404	1			T21	65		T24	1		T25	12270
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3641303	1			T21	36		T25	10893		T1	23
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1338381	1			T21	2		T1	18		T11	67
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1764704	1			T21	25		T1	8		T11	237
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	360425	1			T21	3		T1	23		T11	27
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1331328	1			T1	78		T11	96		T12	82880
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5107487	1			T21	41		T24	1		T25	11575
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3650917	1			T21	54		T25	11588		T1	55
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1340823	1			T21	2		T1	28		T11	58
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1763165	1			T21	19		T1	4		T11	198
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	357468	1			T21	11		T1	49		T11	32
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1324685	1			T21	4		T1	8		T11	44
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5091583	1			T21	42		T24	1		T25	10718
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3653641	1			T21	38		T25	12445		T1	37
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1337864	1			T1	21		T11	101		T12	82474
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1771125	1			T21	28		T1	8		T11	219
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	361149	1			T21	14		T1	18		T11	38
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1329183	1			T21	9		T1	68		T11	65
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5093717	1			T21	44		T24	1		T25	12370
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3652608	1			T21	39		T25	10793		T1	32
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1342854	1			T21	8		T1	26		T11	73
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1766762	1			T21	15		T1	9		T11	204
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	360461	1			T21	19		T1	29		T11	27
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1328143	1			T21	6		T1	52		T11	83
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5099927	1			T21	48		T24	1		T25	11492
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3653236	1			T21	45		T25	11671		T1	37
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1342343	1			T1	8		T11	46		T12	84175
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1764447	1			T21	17		T1	4		T11	194
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	359768	1			T21	15		T1	71		T11	27
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1324824	1			T21	6		T1	35		T11	97
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5103792	1			T21	48		T24	1		T25	11620
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3644424	1			T21	52		T25	11543		T1	36
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1341167	1			T1	26		T11	60		T12	83082
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1764980	1			T21	1		T1	11		T11	177
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	359569	1			T21	16		T1	57		T11	25
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1330613	1			T21	14		T1	22		T11	33
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5096294	1			T21	44		T24	1		T25	12324
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3649479	1			T21	36		T25	10839		T1	30
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1339461	1			T1	54		T11	76		T12	83869
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1765413	1			T21	31		T1	8		T11	148
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	360646	1			T21	14		T1	24		T11	21
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1333252	1			T21	6		T1	34		T11	36
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5094987	1			T21	67		T24	1		T25	11775
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3650454	1			T21	29		T25	11388		T1	33
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1339045	1			T1	4		T11	63		T12	82985
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1762695	1			T21	22		T1	5		T11	160
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	361052	1			T21	2		T1	89		T11	18
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1336312	1			T21	11		T1	17		T11	69
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5095675	1			T21	80		T24	1		T25	10287
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3651955	1			T21	21		T25	12876		T1	49
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1335423	1			T21	1		T1	23		T11	75
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1770498	1			T21	24		T1	10		T11	180
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	360905	1			T21	1		T1	37		T11	36
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1330089	1			T21	4		T1	31		T11	60
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5099817	1			T21	46		T24	1		T25	11817
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3644833	1			T21	39		T25	11346		T1	75
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1343196	1			T21	3		T1	20		T11	50
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1766740	1			T21	25		T1	7		T11	250
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	360604	1			T21	11		T1	47		T11	37
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1329355	1			T21	7		T1	4		T11	57
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5100891	1			T21	70		T24	1		T25	10402
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3650992	1			T21	37		T25	12761		T1	57
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1345379	1			T21	2		T1	11		T11	73
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1763420	1			T21	16		T1	7		T11	225
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	357226	1			T21	4		T1	66		T11	50
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1326637	1			T21	2		T1	14		T11	30
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5100347	1			T21	62		T24	1		T25	10825
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3647955	1			T21	29		T25	12338		T1	76
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1340951	1			T21	3		T1	40		T11	89
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1767392	1			T21	21		T11	159		T12	122933
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	360861	1			T21	7		T1	10		T11	20
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1327039	1			T21	9		T1	19		T11	63
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5101345	1			T21	53		T24	1		T25	12600
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3651567	1			T21	51		T25	10563		T1	26
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1346626	1			T21	5		T1	22		T11	72
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1759975	1			T1	10		T11	134		T12	122081
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	354868	1			T21	15		T1	46		T11	21
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1330164	1			T21	7		T1	46		T11	54
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5104664	1			T21	19		T24	1		T25	11774
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3645932	1			T21	96		T25	11389		T1	42
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1339305	1			T21	2		T1	66		T11	84
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1769665	1			T21	5		T11	136		T12	123310
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	361051	1			T21	8		T1	15		T11	24
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1323928	1			T21	1		T1	20		T11	47
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5107382	1			T21	40		T24	1		T25	11703
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3646880	1			T21	53		T25	11460		T1	77
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1330481	1			T1	6		T11	59		T12	83143
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1773742	1			T21	18		T11	160		T12	124133
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	361245	1			T21	20		T1	44		T11	32
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1324815	1			T1	16		T11	89		T12	82252
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5094150	1			T21	76		T24	1		T25	11327
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3653988	1			T21	21		T25	11836		T1	64
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1335362	1			T21	2		T1	20		T11	49
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1775297	1			T21	20		T11	180		T12	123282
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	361801	1			T21	2		T1	36		T11	28
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1323947	1			T21	10		T1	13		T11	37
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5118350	1			T21	76		T24	1		T25	12563
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3647564	1			T21	32		T25	10600		T1	37
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1331645	1			T21	4		T1	57		T11	32
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1767656	1			T21	17		T1	2		T11	225
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	360673	1			T21	2		T1	31		T11	22
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1318657	1			T1	16		T11	54		T12	81950
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5109621	1			T21	47		T24	1		T25	11251
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3650512	1			T21	51		T25	11912		T1	37
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1339139	1			T21	2		T1	45		T11	44
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1764334	1			T21	14		T1	5		T11	223
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	357958	1			T21	17		T1	31		T11	37
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1322981	1			T1	24		T11	92		T12	83649
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5097774	1			T21	36		T24	1		T25	11195
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3663848	1			T21	63		T25	11968		T1	74
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1330508	1			T1	15		T11	44		T12	82334
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1770553	1			T21	21		T1	1		T11	207
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	358845	1			T21	9		T1	52		T11	38
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1323017	1			T21	2		T11	51		T12	84294
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5108244	1			T21	57		T24	1		T25	11875
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3646422	1			T21	35		T25	11288		T1	112
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1333089	1			T21	2		T1	17		T11	58
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1771382	1			T21	20		T11	134		T12	124071
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	362773	1			T21	6		T1	13		T11	26
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1322635	1			T21	11		T11	84		T12	81696
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5097718	1			T21	58		T24	1		T25	10597
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3655199	1			T21	63		T25	12566		T1	29
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1333860	1			T1	47		T11	76		T12	84161
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1771447	1			T21	5		T1	7		T11	152
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	360265	1			T21	4		T1	24		T11	27
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1326056	1			T21	1		T1	42		T11	32
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5112456	1			T21	76		T24	1		T25	11125
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3648742	1			T21	36		T25	12038		T1	41
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1334698	1			T21	2		T1	60		T11	64
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1767188	1			T21	11		T11	172		T12	122071
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	360008	1			T21	5		T1	16		T11	37
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1321453	1			T21	1		T1	23		T11	88
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5105954	1			T21	48		T24	1		T25	10930
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3651543	1			T21	32		T25	12233		T1	55
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1336140	1			T21	1		T1	10		T11	84
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1768917	1			T21	34		T11	243		T12	123132
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	362070	1			T21	14		T1	65		T11	48
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1319921	1			T21	2		T1	18		T11	57
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5099996	1			T21	68		T24	1		T25	11821
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3650446	1			T21	30		T25	11342		T1	40
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1334229	1			T1	43		T11	63		T12	82109
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1772704	1			T21	30		T1	1		T11	165
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	360799	1			T21	2		T1	31		T11	32
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1326371	1			T21	1		T1	22		T11	76
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5101958	1			T21	31		T24	1		T25	11823
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3652573	1			T21	82		T25	11340		T1	58
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1336607	1			T1	10		T11	46		T12	82686
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1768224	1			T21	3		T1	10		T11	186
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	361127	1			T21	10		T1	56		T11	36
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1324056	1			T21	5		T1	19		T11	70
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5098681	1			T21	65		T24	1		T25	11417
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3656032	1			T21	35		T25	11746		T1	19
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1338628	1			T21	3		T1	50		T11	88
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1769979	1			T21	24		T1	1		T11	162
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	360389	1			T21	3		T1	28		T11	33
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1320836	1			T21	1		T1	48		T11	63
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5099432	1			T21	32		T24	1		T25	12654
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3653675	1			T21	63		T25	10509		T1	30
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1332615	1			T21	3		T1	48		T11	36
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1774771	1			T21	9		T1	5		T11	206
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	360376	1			T21	20		T1	31		T11	39
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1323676	1			T21	4		T1	34		T11	55
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5103741	1			T21	40		T24	1		T25	12012
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3653811	1			T21	63		T25	11151		T1	60
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1331287	1			T21	2		T1	4		T11	66
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1770851	1			T21	1		T1	12		T11	238
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	359782	1			T21	12		T1	42		T11	37
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1325073	1			T21	13		T1	34		T11	90
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5101884	1			T21	41		T24	1		T25	10794
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3656435	1			T21	71		T25	12369		T1	33
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1334383	1			T21	4		T1	34		T11	66
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1768445	1			T21	2		T1	13		T11	172
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	361085	1			T21	8		T1	26		T11	27
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1322313	1			T21	5		T1	45		T11	57

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal