Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[1]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[2]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[3]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[4]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[5]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[6]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[7]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[8]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[9]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[10]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[11]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[12]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[13]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[14]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[15]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[16]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[17]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[18]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[19]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[20]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[21]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[22]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[23]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[24]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[25]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[26]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[27]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[28]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[29]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[30]	13544545	1			T21	131		T24	1		T25	23163
bins_for_gpio_bits[31]	13544545	1			T21	131		T24	1		T25	23163

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262655770

1

T21

2267

T24

32

T25

369315

auto[1]

170769670

1

T21

1925

T25

371901

T1

3633

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262645814

1

T21

2268

T24

32

T25

369315

auto[1]

170779626

1

T21

1924

T25

371901

T1

3633

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7982978	1			T21	63		T24	1		T25	10950
bins_for_gpio_bits[0]	auto[0]	auto[1]	237021	1			T1	5		T11	12		T12	14804
bins_for_gpio_bits[0]	auto[1]	auto[0]	237321	1			T1	5		T11	12		T12	14804
bins_for_gpio_bits[0]	auto[1]	auto[1]	5087225	1			T21	68		T25	12213		T1	112
bins_for_gpio_bits[1]	auto[0]	auto[0]	7973091	1			T21	73		T24	1		T25	11018
bins_for_gpio_bits[1]	auto[0]	auto[1]	237481	1			T1	4		T11	8		T12	14836
bins_for_gpio_bits[1]	auto[1]	auto[0]	237731	1			T1	4		T11	8		T12	14837
bins_for_gpio_bits[1]	auto[1]	auto[1]	5096242	1			T21	58		T25	12145		T1	106
bins_for_gpio_bits[2]	auto[0]	auto[0]	7968039	1			T21	80		T24	1		T25	12411
bins_for_gpio_bits[2]	auto[0]	auto[1]	238076	1			T1	4		T11	11		T12	14761
bins_for_gpio_bits[2]	auto[1]	auto[0]	238379	1			T1	4		T11	11		T12	14762
bins_for_gpio_bits[2]	auto[1]	auto[1]	5100051	1			T21	51		T25	10752		T1	119
bins_for_gpio_bits[3]	auto[0]	auto[0]	7972736	1			T21	92		T24	1		T25	12270
bins_for_gpio_bits[3]	auto[0]	auto[1]	238451	1			T1	4		T11	15		T12	14870
bins_for_gpio_bits[3]	auto[1]	auto[0]	238753	1			T1	4		T11	15		T12	14870
bins_for_gpio_bits[3]	auto[1]	auto[1]	5094605	1			T21	39		T25	10893		T1	120
bins_for_gpio_bits[4]	auto[0]	auto[0]	7973854	1			T21	62		T24	1		T25	11575
bins_for_gpio_bits[4]	auto[0]	auto[1]	237326	1			T1	2		T11	11		T12	14784
bins_for_gpio_bits[4]	auto[1]	auto[0]	237621	1			T1	2		T11	11		T12	14784
bins_for_gpio_bits[4]	auto[1]	auto[1]	5095744	1			T21	69		T25	11588		T1	110
bins_for_gpio_bits[5]	auto[0]	auto[0]	7962178	1			T21	70		T24	1		T25	10718
bins_for_gpio_bits[5]	auto[0]	auto[1]	238062	1			T1	5		T11	14		T12	14876
bins_for_gpio_bits[5]	auto[1]	auto[0]	238394	1			T1	5		T11	14		T12	14876
bins_for_gpio_bits[5]	auto[1]	auto[1]	5105911	1			T21	61		T25	12445		T1	118
bins_for_gpio_bits[6]	auto[0]	auto[0]	7965269	1			T21	67		T24	1		T25	12370
bins_for_gpio_bits[6]	auto[0]	auto[1]	237709	1			T1	5		T11	11		T12	14874
bins_for_gpio_bits[6]	auto[1]	auto[0]	238064	1			T1	5		T11	11		T12	14876
bins_for_gpio_bits[6]	auto[1]	auto[1]	5103503	1			T21	64		T25	10793		T1	108
bins_for_gpio_bits[7]	auto[0]	auto[0]	7968622	1			T21	65		T24	1		T25	11492
bins_for_gpio_bits[7]	auto[0]	auto[1]	237786	1			T1	2		T11	11		T12	14764
bins_for_gpio_bits[7]	auto[1]	auto[0]	238095	1			T1	2		T11	11		T12	14764
bins_for_gpio_bits[7]	auto[1]	auto[1]	5100042	1			T21	66		T25	11671		T1	141
bins_for_gpio_bits[8]	auto[0]	auto[0]	7971664	1			T21	49		T24	1		T25	11620
bins_for_gpio_bits[8]	auto[0]	auto[1]	237955	1			T1	5		T11	6		T12	14866
bins_for_gpio_bits[8]	auto[1]	auto[0]	238275	1			T1	5		T11	6		T12	14866
bins_for_gpio_bits[8]	auto[1]	auto[1]	5096651	1			T21	82		T25	11543		T1	110
bins_for_gpio_bits[9]	auto[0]	auto[0]	7962931	1			T21	75		T24	1		T25	12324
bins_for_gpio_bits[9]	auto[0]	auto[1]	237923	1			T1	5		T11	6		T12	14957
bins_for_gpio_bits[9]	auto[1]	auto[0]	238237	1			T1	5		T11	6		T12	14957
bins_for_gpio_bits[9]	auto[1]	auto[1]	5105454	1			T21	56		T25	10839		T1	83
bins_for_gpio_bits[10]	auto[0]	auto[0]	7958347	1			T21	89		T24	1		T25	11775
bins_for_gpio_bits[10]	auto[0]	auto[1]	238082	1			T1	2		T11	12		T12	14997
bins_for_gpio_bits[10]	auto[1]	auto[0]	238380	1			T1	2		T11	12		T12	14998
bins_for_gpio_bits[10]	auto[1]	auto[1]	5109736	1			T21	42		T25	11388		T1	137
bins_for_gpio_bits[11]	auto[0]	auto[0]	7963451	1			T21	105		T24	1		T25	10287
bins_for_gpio_bits[11]	auto[0]	auto[1]	237796	1			T1	3		T11	11		T12	14932
bins_for_gpio_bits[11]	auto[1]	auto[0]	238145	1			T1	3		T11	11		T12	14933
bins_for_gpio_bits[11]	auto[1]	auto[1]	5105153	1			T21	26		T25	12876		T1	114
bins_for_gpio_bits[12]	auto[0]	auto[0]	7971591	1			T21	74		T24	1		T25	11817
bins_for_gpio_bits[12]	auto[0]	auto[1]	237890	1			T1	2		T11	12		T12	14878
bins_for_gpio_bits[12]	auto[1]	auto[0]	238162	1			T1	2		T11	12		T12	14878
bins_for_gpio_bits[12]	auto[1]	auto[1]	5096902	1			T21	57		T25	11346		T1	124
bins_for_gpio_bits[13]	auto[0]	auto[0]	7971601	1			T21	88		T24	1		T25	10402
bins_for_gpio_bits[13]	auto[0]	auto[1]	237790	1			T1	1		T11	8		T12	15012
bins_for_gpio_bits[13]	auto[1]	auto[0]	238089	1			T1	1		T11	8		T12	15014
bins_for_gpio_bits[13]	auto[1]	auto[1]	5097065	1			T21	43		T25	12761		T1	136
bins_for_gpio_bits[14]	auto[0]	auto[0]	7970258	1			T21	86		T24	1		T25	10825
bins_for_gpio_bits[14]	auto[0]	auto[1]	238107	1			T1	5		T11	10		T12	14903
bins_for_gpio_bits[14]	auto[1]	auto[0]	238432	1			T1	5		T11	10		T12	14904
bins_for_gpio_bits[14]	auto[1]	auto[1]	5097748	1			T21	45		T25	12338		T1	100
bins_for_gpio_bits[15]	auto[0]	auto[0]	7969490	1			T21	58		T24	1		T25	12600
bins_for_gpio_bits[15]	auto[0]	auto[1]	238141	1			T1	3		T11	15		T12	14725
bins_for_gpio_bits[15]	auto[1]	auto[0]	238456	1			T1	3		T11	15		T12	14725
bins_for_gpio_bits[15]	auto[1]	auto[1]	5098458	1			T21	73		T25	10563		T1	115
bins_for_gpio_bits[16]	auto[0]	auto[0]	7975419	1			T21	26		T24	1		T25	11774
bins_for_gpio_bits[16]	auto[0]	auto[1]	237905	1			T1	5		T11	10		T12	14819
bins_for_gpio_bits[16]	auto[1]	auto[0]	238215	1			T1	5		T11	10		T12	14819
bins_for_gpio_bits[16]	auto[1]	auto[1]	5093006	1			T21	105		T25	11389		T1	72
bins_for_gpio_bits[17]	auto[0]	auto[0]	7973749	1			T21	58		T24	1		T25	11703
bins_for_gpio_bits[17]	auto[0]	auto[1]	237547	1			T1	1		T11	15		T12	14892
bins_for_gpio_bits[17]	auto[1]	auto[0]	237856	1			T1	1		T11	15		T12	14892
bins_for_gpio_bits[17]	auto[1]	auto[1]	5095393	1			T21	73		T25	11460		T1	136
bins_for_gpio_bits[18]	auto[0]	auto[0]	7966677	1			T21	98		T24	1		T25	11327
bins_for_gpio_bits[18]	auto[0]	auto[1]	237797	1			T21	1		T1	4		T11	8
bins_for_gpio_bits[18]	auto[1]	auto[0]	238132	1			T1	4		T11	8		T12	14871
bins_for_gpio_bits[18]	auto[1]	auto[1]	5101939	1			T21	32		T25	11836		T1	109
bins_for_gpio_bits[19]	auto[0]	auto[0]	7980614	1			T21	97		T24	1		T25	12563
bins_for_gpio_bits[19]	auto[0]	auto[1]	236755	1			T1	4		T11	7		T12	14798
bins_for_gpio_bits[19]	auto[1]	auto[0]	237037	1			T1	4		T11	7		T12	14798
bins_for_gpio_bits[19]	auto[1]	auto[1]	5090139	1			T21	34		T25	10600		T1	80
bins_for_gpio_bits[20]	auto[0]	auto[0]	7975073	1			T21	63		T24	1		T25	11251
bins_for_gpio_bits[20]	auto[0]	auto[1]	237695	1			T1	6		T11	13		T12	15002
bins_for_gpio_bits[20]	auto[1]	auto[0]	238021	1			T1	6		T11	13		T12	15002
bins_for_gpio_bits[20]	auto[1]	auto[1]	5093756	1			T21	68		T25	11912		T1	86
bins_for_gpio_bits[21]	auto[0]	auto[0]	7960839	1			T21	57		T24	1		T25	11195
bins_for_gpio_bits[21]	auto[0]	auto[1]	237705	1			T1	1		T11	10		T12	15046
bins_for_gpio_bits[21]	auto[1]	auto[0]	237996	1			T1	1		T11	10		T12	15047
bins_for_gpio_bits[21]	auto[1]	auto[1]	5108005	1			T21	74		T25	11968		T1	125
bins_for_gpio_bits[22]	auto[0]	auto[0]	7975335	1			T21	79		T24	1		T25	11875
bins_for_gpio_bits[22]	auto[0]	auto[1]	237071	1			T1	3		T11	11		T12	14813
bins_for_gpio_bits[22]	auto[1]	auto[0]	237380	1			T1	3		T11	11		T12	14813
bins_for_gpio_bits[22]	auto[1]	auto[1]	5094759	1			T21	52		T25	11288		T1	122
bins_for_gpio_bits[23]	auto[0]	auto[0]	7964810	1			T21	63		T24	1		T25	10597
bins_for_gpio_bits[23]	auto[0]	auto[1]	237883	1			T1	5		T11	7		T12	14971
bins_for_gpio_bits[23]	auto[1]	auto[0]	238215	1			T1	5		T11	7		T12	14972
bins_for_gpio_bits[23]	auto[1]	auto[1]	5103637	1			T21	68		T25	12566		T1	90
bins_for_gpio_bits[24]	auto[0]	auto[0]	7976448	1			T21	89		T24	1		T25	11125
bins_for_gpio_bits[24]	auto[0]	auto[1]	237605	1			T1	6		T11	14		T12	14773
bins_for_gpio_bits[24]	auto[1]	auto[0]	237894	1			T1	6		T11	14		T12	14773
bins_for_gpio_bits[24]	auto[1]	auto[1]	5092598	1			T21	42		T25	12038		T1	74
bins_for_gpio_bits[25]	auto[0]	auto[0]	7973303	1			T21	83		T24	1		T25	10930
bins_for_gpio_bits[25]	auto[0]	auto[1]	237353	1			T1	3		T11	15		T12	14927
bins_for_gpio_bits[25]	auto[1]	auto[0]	237708	1			T1	3		T11	15		T12	14928
bins_for_gpio_bits[25]	auto[1]	auto[1]	5096181	1			T21	48		T25	12233		T1	135
bins_for_gpio_bits[26]	auto[0]	auto[0]	7968693	1			T21	98		T24	1		T25	11821
bins_for_gpio_bits[26]	auto[0]	auto[1]	237899	1			T1	5		T11	10		T12	14925
bins_for_gpio_bits[26]	auto[1]	auto[0]	238236	1			T1	5		T11	10		T12	14926
bins_for_gpio_bits[26]	auto[1]	auto[1]	5099717	1			T21	33		T25	11342		T1	88
bins_for_gpio_bits[27]	auto[0]	auto[0]	7968915	1			T21	34		T24	1		T25	11823
bins_for_gpio_bits[27]	auto[0]	auto[1]	237572	1			T1	2		T11	12		T12	14716
bins_for_gpio_bits[27]	auto[1]	auto[0]	237874	1			T1	2		T11	12		T12	14717
bins_for_gpio_bits[27]	auto[1]	auto[1]	5100184	1			T21	97		T25	11340		T1	131
bins_for_gpio_bits[28]	auto[0]	auto[0]	7969895	1			T21	92		T24	1		T25	11417
bins_for_gpio_bits[28]	auto[0]	auto[1]	237122	1			T1	6		T11	11		T12	14797
bins_for_gpio_bits[28]	auto[1]	auto[0]	237393	1			T1	6		T11	11		T12	14797
bins_for_gpio_bits[28]	auto[1]	auto[1]	5100135	1			T21	39		T25	11746		T1	89
bins_for_gpio_bits[29]	auto[0]	auto[0]	7968987	1			T21	44		T24	1		T25	12654
bins_for_gpio_bits[29]	auto[0]	auto[1]	237481	1			T1	6		T11	14		T12	14705
bins_for_gpio_bits[29]	auto[1]	auto[0]	237831	1			T1	6		T11	14		T12	14705
bins_for_gpio_bits[29]	auto[1]	auto[1]	5100246	1			T21	87		T25	10509		T1	89
bins_for_gpio_bits[30]	auto[0]	auto[0]	7967609	1			T21	43		T24	1		T25	12012
bins_for_gpio_bits[30]	auto[0]	auto[1]	237988	1			T1	1		T11	17		T12	15015
bins_for_gpio_bits[30]	auto[1]	auto[0]	238270	1			T1	1		T11	17		T12	15016
bins_for_gpio_bits[30]	auto[1]	auto[1]	5100678	1			T21	88		T25	11151		T1	135
bins_for_gpio_bits[31]	auto[0]	auto[0]	7967515	1			T21	47		T24	1		T25	10794
bins_for_gpio_bits[31]	auto[0]	auto[1]	236859	1			T1	5		T11	12		T12	14931
bins_for_gpio_bits[31]	auto[1]	auto[0]	237197	1			T1	5		T11	12		T12	14932
bins_for_gpio_bits[31]	auto[1]	auto[1]	5102974	1			T21	84		T25	12369		T1	99