Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7916571 |
1 |
|
|
T21 |
52 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5846527 |
1 |
|
|
T21 |
30 |
|
T1 |
101 |
|
T12 |
343640 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13009883 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
753215 |
1 |
|
|
T21 |
1 |
|
T1 |
8 |
|
T12 |
43955 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7897527 |
1 |
|
|
T21 |
69 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5865571 |
1 |
|
|
T21 |
13 |
|
T1 |
84 |
|
T12 |
349905 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2556037 |
1 |
|
|
T21 |
12 |
|
T1 |
23 |
|
T12 |
151732 |
| auto[1] |
auto[0] |
auto[1] |
376537 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T12 |
21671 |
| auto[1] |
auto[1] |
auto[0] |
2556319 |
1 |
|
|
T1 |
53 |
|
T12 |
154218 |
|
T13 |
24680 |
| auto[1] |
auto[1] |
auto[1] |
376678 |
1 |
|
|
T1 |
6 |
|
T12 |
22284 |
|
T13 |
3154 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7909931 |
1 |
|
|
T21 |
54 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5853167 |
1 |
|
|
T21 |
28 |
|
T1 |
37 |
|
T12 |
338496 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13014472 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
748626 |
1 |
|
|
T21 |
1 |
|
T1 |
7 |
|
T12 |
43338 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7935053 |
1 |
|
|
T21 |
63 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5828045 |
1 |
|
|
T21 |
19 |
|
T1 |
90 |
|
T12 |
348183 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2549360 |
1 |
|
|
T21 |
14 |
|
T1 |
64 |
|
T12 |
158658 |
| auto[1] |
auto[0] |
auto[1] |
377107 |
1 |
|
|
T21 |
1 |
|
T1 |
6 |
|
T12 |
23011 |
| auto[1] |
auto[1] |
auto[0] |
2530059 |
1 |
|
|
T21 |
4 |
|
T1 |
19 |
|
T12 |
146187 |
| auto[1] |
auto[1] |
auto[1] |
371519 |
1 |
|
|
T1 |
1 |
|
T12 |
20327 |
|
T13 |
2972 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7914798 |
1 |
|
|
T21 |
46 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5848300 |
1 |
|
|
T21 |
36 |
|
T1 |
29 |
|
T12 |
347137 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13013818 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
749280 |
1 |
|
|
T21 |
1 |
|
T1 |
4 |
|
T12 |
42120 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7926305 |
1 |
|
|
T21 |
62 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5836793 |
1 |
|
|
T21 |
20 |
|
T1 |
64 |
|
T12 |
341998 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2556875 |
1 |
|
|
T21 |
6 |
|
T1 |
56 |
|
T12 |
151696 |
| auto[1] |
auto[0] |
auto[1] |
378035 |
1 |
|
|
T1 |
4 |
|
T12 |
21515 |
|
T13 |
3105 |
| auto[1] |
auto[1] |
auto[0] |
2530638 |
1 |
|
|
T21 |
13 |
|
T1 |
4 |
|
T12 |
148182 |
| auto[1] |
auto[1] |
auto[1] |
371245 |
1 |
|
|
T21 |
1 |
|
T12 |
20605 |
|
T13 |
3334 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7910517 |
1 |
|
|
T21 |
58 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5852581 |
1 |
|
|
T21 |
24 |
|
T1 |
89 |
|
T12 |
351716 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13011304 |
1 |
|
|
T21 |
82 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
751794 |
1 |
|
|
T1 |
6 |
|
T12 |
43531 |
|
T13 |
6474 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7917930 |
1 |
|
|
T21 |
69 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5845168 |
1 |
|
|
T21 |
13 |
|
T1 |
65 |
|
T12 |
346859 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2549380 |
1 |
|
|
T21 |
13 |
|
T1 |
14 |
|
T12 |
150012 |
| auto[1] |
auto[0] |
auto[1] |
376364 |
1 |
|
|
T1 |
1 |
|
T12 |
21444 |
|
T13 |
3153 |
| auto[1] |
auto[1] |
auto[0] |
2543994 |
1 |
|
|
T1 |
45 |
|
T12 |
153316 |
|
T13 |
25539 |
| auto[1] |
auto[1] |
auto[1] |
375430 |
1 |
|
|
T1 |
5 |
|
T12 |
22087 |
|
T13 |
3321 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7925243 |
1 |
|
|
T21 |
36 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5837855 |
1 |
|
|
T21 |
46 |
|
T1 |
72 |
|
T12 |
337292 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13010366 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
752732 |
1 |
|
|
T21 |
1 |
|
T1 |
3 |
|
T12 |
43404 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7906088 |
1 |
|
|
T21 |
65 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5857010 |
1 |
|
|
T21 |
17 |
|
T1 |
40 |
|
T12 |
346967 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2562757 |
1 |
|
|
T21 |
8 |
|
T1 |
4 |
|
T12 |
152339 |
| auto[1] |
auto[0] |
auto[1] |
378730 |
1 |
|
|
T12 |
21783 |
|
T13 |
3176 |
|
T15 |
17940 |
| auto[1] |
auto[1] |
auto[0] |
2541521 |
1 |
|
|
T21 |
8 |
|
T1 |
33 |
|
T12 |
151224 |
| auto[1] |
auto[1] |
auto[1] |
374002 |
1 |
|
|
T21 |
1 |
|
T1 |
3 |
|
T12 |
21621 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7877847 |
1 |
|
|
T21 |
57 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5885251 |
1 |
|
|
T21 |
25 |
|
T1 |
85 |
|
T12 |
339464 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13011816 |
1 |
|
|
T21 |
80 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
751282 |
1 |
|
|
T21 |
2 |
|
T1 |
3 |
|
T12 |
42473 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7921778 |
1 |
|
|
T21 |
60 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5841320 |
1 |
|
|
T21 |
22 |
|
T1 |
73 |
|
T12 |
340927 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2535566 |
1 |
|
|
T21 |
16 |
|
T1 |
36 |
|
T12 |
153161 |
| auto[1] |
auto[0] |
auto[1] |
374117 |
1 |
|
|
T21 |
2 |
|
T1 |
2 |
|
T12 |
21899 |
| auto[1] |
auto[1] |
auto[0] |
2554472 |
1 |
|
|
T21 |
4 |
|
T1 |
34 |
|
T12 |
145293 |
| auto[1] |
auto[1] |
auto[1] |
377165 |
1 |
|
|
T1 |
1 |
|
T12 |
20574 |
|
T13 |
3071 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7924180 |
1 |
|
|
T21 |
70 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5838918 |
1 |
|
|
T21 |
12 |
|
T1 |
63 |
|
T12 |
342430 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13011658 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
751440 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T12 |
43275 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7922065 |
1 |
|
|
T21 |
68 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5841033 |
1 |
|
|
T21 |
14 |
|
T1 |
41 |
|
T12 |
346171 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2547613 |
1 |
|
|
T21 |
9 |
|
T1 |
33 |
|
T12 |
151581 |
| auto[1] |
auto[0] |
auto[1] |
376406 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T12 |
21905 |
| auto[1] |
auto[1] |
auto[0] |
2541980 |
1 |
|
|
T21 |
4 |
|
T1 |
7 |
|
T12 |
151315 |
| auto[1] |
auto[1] |
auto[1] |
375034 |
1 |
|
|
T12 |
21370 |
|
T13 |
2992 |
|
T15 |
16988 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7863433 |
1 |
|
|
T21 |
47 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5899665 |
1 |
|
|
T21 |
35 |
|
T1 |
25 |
|
T12 |
345769 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13006659 |
1 |
|
|
T21 |
82 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
756439 |
1 |
|
|
T1 |
4 |
|
T12 |
43556 |
|
T13 |
6242 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7890007 |
1 |
|
|
T21 |
76 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5873091 |
1 |
|
|
T21 |
6 |
|
T1 |
47 |
|
T12 |
348298 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2536562 |
1 |
|
|
T1 |
41 |
|
T12 |
153715 |
|
T13 |
25236 |
| auto[1] |
auto[0] |
auto[1] |
373242 |
1 |
|
|
T1 |
4 |
|
T12 |
21845 |
|
T13 |
3182 |
| auto[1] |
auto[1] |
auto[0] |
2580090 |
1 |
|
|
T21 |
6 |
|
T1 |
2 |
|
T12 |
151027 |
| auto[1] |
auto[1] |
auto[1] |
383197 |
1 |
|
|
T12 |
21711 |
|
T13 |
3060 |
|
T15 |
17918 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7937595 |
1 |
|
|
T21 |
55 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5825503 |
1 |
|
|
T21 |
27 |
|
T1 |
52 |
|
T12 |
340848 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13004786 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
758312 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T12 |
43172 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7885290 |
1 |
|
|
T21 |
63 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5877808 |
1 |
|
|
T21 |
19 |
|
T1 |
77 |
|
T12 |
347704 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2576853 |
1 |
|
|
T21 |
14 |
|
T1 |
48 |
|
T12 |
158412 |
| auto[1] |
auto[0] |
auto[1] |
382618 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T12 |
22609 |
| auto[1] |
auto[1] |
auto[0] |
2542643 |
1 |
|
|
T21 |
4 |
|
T1 |
27 |
|
T12 |
146120 |
| auto[1] |
auto[1] |
auto[1] |
375694 |
1 |
|
|
T1 |
1 |
|
T12 |
20563 |
|
T13 |
3260 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7929015 |
1 |
|
|
T21 |
53 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5834083 |
1 |
|
|
T21 |
29 |
|
T1 |
79 |
|
T12 |
337939 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13011004 |
1 |
|
|
T21 |
80 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
752094 |
1 |
|
|
T21 |
2 |
|
T1 |
3 |
|
T12 |
41623 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7912145 |
1 |
|
|
T21 |
61 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5850953 |
1 |
|
|
T21 |
21 |
|
T1 |
90 |
|
T12 |
338743 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2555600 |
1 |
|
|
T21 |
10 |
|
T1 |
32 |
|
T12 |
149221 |
| auto[1] |
auto[0] |
auto[1] |
376923 |
1 |
|
|
T1 |
3 |
|
T12 |
20896 |
|
T13 |
3134 |
| auto[1] |
auto[1] |
auto[0] |
2543259 |
1 |
|
|
T21 |
9 |
|
T1 |
55 |
|
T12 |
147899 |
| auto[1] |
auto[1] |
auto[1] |
375171 |
1 |
|
|
T21 |
2 |
|
T12 |
20727 |
|
T13 |
2977 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7911125 |
1 |
|
|
T21 |
37 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5851973 |
1 |
|
|
T21 |
45 |
|
T1 |
121 |
|
T12 |
339767 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13011683 |
1 |
|
|
T21 |
82 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
751415 |
1 |
|
|
T1 |
4 |
|
T12 |
43698 |
|
T13 |
6741 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7918973 |
1 |
|
|
T21 |
69 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5844125 |
1 |
|
|
T21 |
13 |
|
T1 |
73 |
|
T12 |
348727 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2554642 |
1 |
|
|
T21 |
3 |
|
T12 |
156830 |
|
T13 |
27104 |
| auto[1] |
auto[0] |
auto[1] |
378586 |
1 |
|
|
T12 |
22794 |
|
T13 |
3577 |
|
T15 |
17357 |
| auto[1] |
auto[1] |
auto[0] |
2538068 |
1 |
|
|
T21 |
10 |
|
T1 |
69 |
|
T12 |
148199 |
| auto[1] |
auto[1] |
auto[1] |
372829 |
1 |
|
|
T1 |
4 |
|
T12 |
20904 |
|
T13 |
3164 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7902386 |
1 |
|
|
T21 |
38 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5860712 |
1 |
|
|
T21 |
44 |
|
T1 |
53 |
|
T12 |
339003 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13010237 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
752861 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T12 |
43459 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7902386 |
1 |
|
|
T21 |
69 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5860712 |
1 |
|
|
T21 |
13 |
|
T1 |
44 |
|
T12 |
345498 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2562709 |
1 |
|
|
T21 |
8 |
|
T1 |
29 |
|
T12 |
150887 |
| auto[1] |
auto[0] |
auto[1] |
377953 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T12 |
21945 |
| auto[1] |
auto[1] |
auto[0] |
2545142 |
1 |
|
|
T21 |
4 |
|
T1 |
14 |
|
T12 |
151152 |
| auto[1] |
auto[1] |
auto[1] |
374908 |
1 |
|
|
T12 |
21514 |
|
T13 |
3126 |
|
T15 |
17496 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7880119 |
1 |
|
|
T21 |
63 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5882979 |
1 |
|
|
T21 |
19 |
|
T1 |
25 |
|
T12 |
347334 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13006100 |
1 |
|
|
T21 |
82 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
756998 |
1 |
|
|
T1 |
5 |
|
T12 |
43385 |
|
T13 |
6451 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7891626 |
1 |
|
|
T21 |
69 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5871472 |
1 |
|
|
T21 |
13 |
|
T1 |
85 |
|
T12 |
349905 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2543036 |
1 |
|
|
T21 |
7 |
|
T1 |
72 |
|
T12 |
151651 |
| auto[1] |
auto[0] |
auto[1] |
376128 |
1 |
|
|
T1 |
5 |
|
T12 |
21101 |
|
T13 |
3268 |
| auto[1] |
auto[1] |
auto[0] |
2571438 |
1 |
|
|
T21 |
6 |
|
T1 |
8 |
|
T12 |
154869 |
| auto[1] |
auto[1] |
auto[1] |
380870 |
1 |
|
|
T12 |
22284 |
|
T13 |
3183 |
|
T15 |
18338 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7894082 |
1 |
|
|
T21 |
46 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5869016 |
1 |
|
|
T21 |
36 |
|
T1 |
69 |
|
T12 |
351947 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13002097 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
761001 |
1 |
|
|
T21 |
1 |
|
T1 |
8 |
|
T12 |
43208 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7857532 |
1 |
|
|
T21 |
65 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5905566 |
1 |
|
|
T21 |
17 |
|
T1 |
89 |
|
T12 |
345466 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2565727 |
1 |
|
|
T21 |
7 |
|
T1 |
36 |
|
T12 |
147900 |
| auto[1] |
auto[0] |
auto[1] |
379193 |
1 |
|
|
T1 |
5 |
|
T12 |
20884 |
|
T13 |
3300 |
| auto[1] |
auto[1] |
auto[0] |
2578838 |
1 |
|
|
T21 |
9 |
|
T1 |
45 |
|
T12 |
154358 |
| auto[1] |
auto[1] |
auto[1] |
381808 |
1 |
|
|
T21 |
1 |
|
T1 |
3 |
|
T12 |
22324 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7883260 |
1 |
|
|
T21 |
48 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5879838 |
1 |
|
|
T21 |
34 |
|
T1 |
114 |
|
T12 |
338725 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13011282 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
751816 |
1 |
|
|
T21 |
1 |
|
T1 |
5 |
|
T12 |
42808 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7919617 |
1 |
|
|
T21 |
64 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5843481 |
1 |
|
|
T21 |
18 |
|
T1 |
123 |
|
T12 |
342766 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2531532 |
1 |
|
|
T21 |
3 |
|
T1 |
24 |
|
T12 |
148991 |
| auto[1] |
auto[0] |
auto[1] |
373519 |
1 |
|
|
T1 |
1 |
|
T12 |
21228 |
|
T13 |
2981 |
| auto[1] |
auto[1] |
auto[0] |
2560133 |
1 |
|
|
T21 |
14 |
|
T1 |
94 |
|
T12 |
150967 |
| auto[1] |
auto[1] |
auto[1] |
378297 |
1 |
|
|
T21 |
1 |
|
T1 |
4 |
|
T12 |
21580 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7870053 |
1 |
|
|
T21 |
77 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5893045 |
1 |
|
|
T21 |
5 |
|
T1 |
78 |
|
T12 |
350661 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13004592 |
1 |
|
|
T21 |
82 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
758506 |
1 |
|
|
T1 |
3 |
|
T12 |
44039 |
|
T13 |
6343 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7880265 |
1 |
|
|
T21 |
70 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5882833 |
1 |
|
|
T21 |
12 |
|
T1 |
63 |
|
T12 |
351033 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2551241 |
1 |
|
|
T21 |
12 |
|
T1 |
44 |
|
T12 |
147163 |
| auto[1] |
auto[0] |
auto[1] |
377391 |
1 |
|
|
T1 |
3 |
|
T12 |
20852 |
|
T13 |
3293 |
| auto[1] |
auto[1] |
auto[0] |
2573086 |
1 |
|
|
T1 |
16 |
|
T12 |
159831 |
|
T13 |
23669 |
| auto[1] |
auto[1] |
auto[1] |
381115 |
1 |
|
|
T12 |
23187 |
|
T13 |
3050 |
|
T15 |
17444 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7904192 |
1 |
|
|
T21 |
46 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5858906 |
1 |
|
|
T21 |
36 |
|
T1 |
56 |
|
T12 |
338903 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13011428 |
1 |
|
|
T21 |
82 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
751670 |
1 |
|
|
T1 |
2 |
|
T12 |
42290 |
|
T13 |
6198 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7924774 |
1 |
|
|
T21 |
70 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5838324 |
1 |
|
|
T21 |
12 |
|
T1 |
62 |
|
T12 |
338826 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2548370 |
1 |
|
|
T21 |
7 |
|
T1 |
28 |
|
T12 |
153902 |
| auto[1] |
auto[0] |
auto[1] |
376401 |
1 |
|
|
T1 |
1 |
|
T12 |
22140 |
|
T13 |
3175 |
| auto[1] |
auto[1] |
auto[0] |
2538284 |
1 |
|
|
T21 |
5 |
|
T1 |
32 |
|
T12 |
142634 |
| auto[1] |
auto[1] |
auto[1] |
375269 |
1 |
|
|
T1 |
1 |
|
T12 |
20150 |
|
T13 |
3023 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889593 |
1 |
|
|
T21 |
58 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5873505 |
1 |
|
|
T21 |
24 |
|
T1 |
16 |
|
T12 |
332027 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13008660 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
754438 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T12 |
43449 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7915408 |
1 |
|
|
T21 |
67 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5847690 |
1 |
|
|
T21 |
15 |
|
T1 |
52 |
|
T12 |
347741 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2530954 |
1 |
|
|
T21 |
9 |
|
T1 |
44 |
|
T12 |
153627 |
| auto[1] |
auto[0] |
auto[1] |
374948 |
1 |
|
|
T1 |
1 |
|
T12 |
21856 |
|
T13 |
3298 |
| auto[1] |
auto[1] |
auto[0] |
2562298 |
1 |
|
|
T21 |
5 |
|
T1 |
6 |
|
T12 |
150665 |
| auto[1] |
auto[1] |
auto[1] |
379490 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T12 |
21593 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7909473 |
1 |
|
|
T21 |
47 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5853625 |
1 |
|
|
T21 |
35 |
|
T1 |
63 |
|
T12 |
346256 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13013129 |
1 |
|
|
T21 |
82 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
749969 |
1 |
|
|
T1 |
1 |
|
T12 |
42485 |
|
T13 |
5929 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7926882 |
1 |
|
|
T21 |
68 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5836216 |
1 |
|
|
T21 |
14 |
|
T1 |
65 |
|
T12 |
341763 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2547635 |
1 |
|
|
T21 |
7 |
|
T1 |
56 |
|
T12 |
153794 |
| auto[1] |
auto[0] |
auto[1] |
375933 |
1 |
|
|
T1 |
1 |
|
T12 |
22182 |
|
T13 |
2892 |
| auto[1] |
auto[1] |
auto[0] |
2538612 |
1 |
|
|
T21 |
7 |
|
T1 |
8 |
|
T12 |
145484 |
| auto[1] |
auto[1] |
auto[1] |
374036 |
1 |
|
|
T12 |
20303 |
|
T13 |
3037 |
|
T15 |
17615 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7922876 |
1 |
|
|
T21 |
49 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5840222 |
1 |
|
|
T21 |
33 |
|
T1 |
120 |
|
T12 |
345782 |