Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7899812 |
1 |
|
|
T21 |
63 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5863286 |
1 |
|
|
T21 |
19 |
|
T1 |
57 |
|
T12 |
339623 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13009883 |
1 |
|
|
T21 |
82 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
753215 |
1 |
|
|
T1 |
9 |
|
T12 |
41931 |
|
T13 |
6378 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7907172 |
1 |
|
|
T21 |
71 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5855926 |
1 |
|
|
T21 |
11 |
|
T1 |
106 |
|
T12 |
337805 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2559905 |
1 |
|
|
T21 |
3 |
|
T1 |
52 |
|
T12 |
149999 |
| auto[1] |
auto[0] |
auto[1] |
377916 |
1 |
|
|
T1 |
4 |
|
T12 |
21244 |
|
T13 |
3074 |
| auto[1] |
auto[1] |
auto[0] |
2542806 |
1 |
|
|
T21 |
8 |
|
T1 |
45 |
|
T12 |
145875 |
| auto[1] |
auto[1] |
auto[1] |
375299 |
1 |
|
|
T1 |
5 |
|
T12 |
20687 |
|
T13 |
3304 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |