Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7911462 |
1 |
|
|
T21 |
67 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5851636 |
1 |
|
|
T21 |
15 |
|
T1 |
69 |
|
T12 |
345290 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13006659 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
756439 |
1 |
|
|
T21 |
1 |
|
T1 |
7 |
|
T12 |
44855 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7898206 |
1 |
|
|
T21 |
68 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5864892 |
1 |
|
|
T21 |
14 |
|
T1 |
87 |
|
T12 |
355182 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2557252 |
1 |
|
|
T21 |
13 |
|
T1 |
34 |
|
T12 |
154106 |
| auto[1] |
auto[0] |
auto[1] |
379380 |
1 |
|
|
T21 |
1 |
|
T1 |
4 |
|
T12 |
22324 |
| auto[1] |
auto[1] |
auto[0] |
2551201 |
1 |
|
|
T1 |
46 |
|
T12 |
156221 |
|
T13 |
24560 |
| auto[1] |
auto[1] |
auto[1] |
377059 |
1 |
|
|
T1 |
3 |
|
T12 |
22531 |
|
T13 |
3277 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |