Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7895010 |
1 |
|
|
T21 |
48 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5868088 |
1 |
|
|
T21 |
34 |
|
T1 |
115 |
|
T12 |
342986 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13011200 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
751898 |
1 |
|
|
T21 |
1 |
|
T1 |
3 |
|
T12 |
43196 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7913329 |
1 |
|
|
T21 |
61 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5849769 |
1 |
|
|
T21 |
21 |
|
T1 |
96 |
|
T12 |
346310 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2548898 |
1 |
|
|
T21 |
10 |
|
T1 |
23 |
|
T12 |
152807 |
| auto[1] |
auto[0] |
auto[1] |
375925 |
1 |
|
|
T12 |
21949 |
|
T13 |
2968 |
|
T15 |
18130 |
| auto[1] |
auto[1] |
auto[0] |
2548973 |
1 |
|
|
T21 |
10 |
|
T1 |
70 |
|
T12 |
150307 |
| auto[1] |
auto[1] |
auto[1] |
375973 |
1 |
|
|
T21 |
1 |
|
T1 |
3 |
|
T12 |
21247 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |