Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7929042 |
1 |
|
|
T21 |
42 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5834056 |
1 |
|
|
T21 |
40 |
|
T1 |
82 |
|
T12 |
347203 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13008638 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
754460 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T12 |
42033 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7895802 |
1 |
|
|
T21 |
62 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5867296 |
1 |
|
|
T21 |
20 |
|
T1 |
33 |
|
T12 |
339341 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2563201 |
1 |
|
|
T21 |
3 |
|
T1 |
14 |
|
T12 |
145110 |
| auto[1] |
auto[0] |
auto[1] |
378463 |
1 |
|
|
T1 |
1 |
|
T12 |
20474 |
|
T13 |
3080 |
| auto[1] |
auto[1] |
auto[0] |
2549635 |
1 |
|
|
T21 |
16 |
|
T1 |
18 |
|
T12 |
152198 |
| auto[1] |
auto[1] |
auto[1] |
375997 |
1 |
|
|
T21 |
1 |
|
T12 |
21559 |
|
T13 |
3114 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |