Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7876067 |
1 |
|
|
T21 |
62 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5887031 |
1 |
|
|
T21 |
20 |
|
T1 |
50 |
|
T12 |
345130 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13009112 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
753986 |
1 |
|
|
T21 |
1 |
|
T1 |
8 |
|
T12 |
43150 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7909851 |
1 |
|
|
T21 |
68 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5853247 |
1 |
|
|
T21 |
14 |
|
T1 |
116 |
|
T12 |
346278 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2539831 |
1 |
|
|
T21 |
9 |
|
T1 |
71 |
|
T12 |
145064 |
| auto[1] |
auto[0] |
auto[1] |
375969 |
1 |
|
|
T1 |
4 |
|
T12 |
20421 |
|
T13 |
3382 |
| auto[1] |
auto[1] |
auto[0] |
2559430 |
1 |
|
|
T21 |
4 |
|
T1 |
37 |
|
T12 |
158064 |
| auto[1] |
auto[1] |
auto[1] |
378017 |
1 |
|
|
T21 |
1 |
|
T1 |
4 |
|
T12 |
22729 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |