Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7916571 |
1 |
|
|
T21 |
52 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5846527 |
1 |
|
|
T21 |
30 |
|
T1 |
101 |
|
T12 |
343640 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11387754 |
1 |
|
|
T21 |
74 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2375344 |
1 |
|
|
T21 |
8 |
|
T1 |
8 |
|
T12 |
125363 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7935533 |
1 |
|
|
T21 |
61 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5827565 |
1 |
|
|
T21 |
21 |
|
T1 |
15 |
|
T12 |
341948 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1733387 |
1 |
|
|
T21 |
5 |
|
T12 |
106840 |
|
T13 |
16785 |
| auto[1] |
auto[0] |
auto[1] |
1193908 |
1 |
|
|
T21 |
8 |
|
T12 |
62142 |
|
T13 |
9604 |
| auto[1] |
auto[1] |
auto[0] |
1718834 |
1 |
|
|
T21 |
8 |
|
T1 |
7 |
|
T12 |
109745 |
| auto[1] |
auto[1] |
auto[1] |
1181436 |
1 |
|
|
T1 |
8 |
|
T12 |
63221 |
|
T13 |
10123 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |