Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7909931 |
1 |
|
|
T21 |
54 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5853167 |
1 |
|
|
T21 |
28 |
|
T1 |
37 |
|
T12 |
338496 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11376719 |
1 |
|
|
T21 |
77 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2386379 |
1 |
|
|
T21 |
5 |
|
T1 |
44 |
|
T12 |
127509 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7884722 |
1 |
|
|
T21 |
68 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5878376 |
1 |
|
|
T21 |
14 |
|
T1 |
51 |
|
T12 |
346109 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1754403 |
1 |
|
|
T21 |
5 |
|
T1 |
5 |
|
T12 |
110537 |
| auto[1] |
auto[0] |
auto[1] |
1201787 |
1 |
|
|
T21 |
2 |
|
T1 |
37 |
|
T12 |
65967 |
| auto[1] |
auto[1] |
auto[0] |
1737594 |
1 |
|
|
T21 |
4 |
|
T1 |
2 |
|
T12 |
108063 |
| auto[1] |
auto[1] |
auto[1] |
1184592 |
1 |
|
|
T21 |
3 |
|
T1 |
7 |
|
T12 |
61542 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |