Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7914798 |
1 |
|
|
T21 |
46 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5848300 |
1 |
|
|
T21 |
36 |
|
T1 |
29 |
|
T12 |
347137 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11376223 |
1 |
|
|
T21 |
74 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2386875 |
1 |
|
|
T21 |
8 |
|
T1 |
70 |
|
T12 |
127771 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7894066 |
1 |
|
|
T21 |
59 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5869032 |
1 |
|
|
T21 |
23 |
|
T1 |
74 |
|
T12 |
350016 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1746356 |
1 |
|
|
T21 |
5 |
|
T1 |
4 |
|
T12 |
108646 |
| auto[1] |
auto[0] |
auto[1] |
1194261 |
1 |
|
|
T21 |
6 |
|
T1 |
57 |
|
T12 |
62360 |
| auto[1] |
auto[1] |
auto[0] |
1735801 |
1 |
|
|
T21 |
10 |
|
T12 |
113599 |
|
T13 |
19029 |
| auto[1] |
auto[1] |
auto[1] |
1192614 |
1 |
|
|
T21 |
2 |
|
T1 |
13 |
|
T12 |
65411 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |