Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7910517 |
1 |
|
|
T21 |
58 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5852581 |
1 |
|
|
T21 |
24 |
|
T1 |
89 |
|
T12 |
351716 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11371108 |
1 |
|
|
T21 |
70 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2391990 |
1 |
|
|
T21 |
12 |
|
T1 |
80 |
|
T12 |
128110 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7879564 |
1 |
|
|
T21 |
65 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5883534 |
1 |
|
|
T21 |
17 |
|
T1 |
102 |
|
T12 |
348244 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1758544 |
1 |
|
|
T21 |
3 |
|
T1 |
9 |
|
T12 |
106937 |
| auto[1] |
auto[0] |
auto[1] |
1200293 |
1 |
|
|
T21 |
7 |
|
T1 |
27 |
|
T12 |
62773 |
| auto[1] |
auto[1] |
auto[0] |
1733000 |
1 |
|
|
T21 |
2 |
|
T1 |
13 |
|
T12 |
113197 |
| auto[1] |
auto[1] |
auto[1] |
1191697 |
1 |
|
|
T21 |
5 |
|
T1 |
53 |
|
T12 |
65337 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |