Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7925243 |
1 |
|
|
T21 |
36 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5837855 |
1 |
|
|
T21 |
46 |
|
T1 |
72 |
|
T12 |
337292 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11391779 |
1 |
|
|
T21 |
71 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2371319 |
1 |
|
|
T21 |
11 |
|
T1 |
104 |
|
T12 |
126811 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7944190 |
1 |
|
|
T21 |
63 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5818908 |
1 |
|
|
T21 |
19 |
|
T1 |
127 |
|
T12 |
343675 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1715010 |
1 |
|
|
T21 |
1 |
|
T1 |
16 |
|
T12 |
110268 |
| auto[1] |
auto[0] |
auto[1] |
1181380 |
1 |
|
|
T21 |
6 |
|
T1 |
52 |
|
T12 |
64447 |
| auto[1] |
auto[1] |
auto[0] |
1732579 |
1 |
|
|
T21 |
7 |
|
T1 |
7 |
|
T12 |
106596 |
| auto[1] |
auto[1] |
auto[1] |
1189939 |
1 |
|
|
T21 |
5 |
|
T1 |
52 |
|
T12 |
62364 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |