Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13006193 |
1 |
|
|
T21 |
82 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
756905 |
1 |
|
|
T1 |
1 |
|
T12 |
43289 |
|
T13 |
6153 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7895740 |
1 |
|
|
T21 |
75 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5867358 |
1 |
|
|
T21 |
7 |
|
T1 |
18 |
|
T12 |
346649 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2565259 |
1 |
|
|
T21 |
7 |
|
T1 |
1 |
|
T12 |
151561 |
| auto[1] |
auto[0] |
auto[1] |
380989 |
1 |
|
|
T12 |
21533 |
|
T13 |
3254 |
|
T15 |
18922 |
| auto[1] |
auto[1] |
auto[0] |
2545194 |
1 |
|
|
T1 |
16 |
|
T12 |
151799 |
|
T13 |
24031 |
| auto[1] |
auto[1] |
auto[1] |
375916 |
1 |
|
|
T1 |
1 |
|
T12 |
21756 |
|
T13 |
2899 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |