Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7877847 |
1 |
|
|
T21 |
57 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5885251 |
1 |
|
|
T21 |
25 |
|
T1 |
85 |
|
T12 |
339464 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11380231 |
1 |
|
|
T21 |
80 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2382867 |
1 |
|
|
T21 |
2 |
|
T1 |
82 |
|
T12 |
127421 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7911836 |
1 |
|
|
T21 |
72 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5851262 |
1 |
|
|
T21 |
10 |
|
T1 |
94 |
|
T12 |
342854 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1712920 |
1 |
|
|
T21 |
5 |
|
T1 |
3 |
|
T12 |
108960 |
| auto[1] |
auto[0] |
auto[1] |
1186438 |
1 |
|
|
T21 |
2 |
|
T1 |
47 |
|
T12 |
64528 |
| auto[1] |
auto[1] |
auto[0] |
1755475 |
1 |
|
|
T21 |
3 |
|
T1 |
9 |
|
T12 |
106473 |
| auto[1] |
auto[1] |
auto[1] |
1196429 |
1 |
|
|
T1 |
35 |
|
T12 |
62893 |
|
T13 |
10789 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |