Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7924180 |
1 |
|
|
T21 |
70 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5838918 |
1 |
|
|
T21 |
12 |
|
T1 |
63 |
|
T12 |
342430 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11389118 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2373980 |
1 |
|
|
T21 |
1 |
|
T1 |
47 |
|
T12 |
122267 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7921298 |
1 |
|
|
T21 |
70 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5841800 |
1 |
|
|
T21 |
12 |
|
T1 |
82 |
|
T12 |
335410 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1745783 |
1 |
|
|
T21 |
11 |
|
T1 |
9 |
|
T12 |
106780 |
| auto[1] |
auto[0] |
auto[1] |
1192497 |
1 |
|
|
T21 |
1 |
|
T1 |
20 |
|
T12 |
61961 |
| auto[1] |
auto[1] |
auto[0] |
1722037 |
1 |
|
|
T1 |
26 |
|
T12 |
106363 |
|
T13 |
17238 |
| auto[1] |
auto[1] |
auto[1] |
1181483 |
1 |
|
|
T1 |
27 |
|
T12 |
60306 |
|
T13 |
9680 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |