Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7863433 |
1 |
|
|
T21 |
47 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5899665 |
1 |
|
|
T21 |
35 |
|
T1 |
25 |
|
T12 |
345769 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11368591 |
1 |
|
|
T21 |
77 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2394507 |
1 |
|
|
T21 |
5 |
|
T1 |
64 |
|
T12 |
127003 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7877446 |
1 |
|
|
T21 |
62 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5885652 |
1 |
|
|
T21 |
20 |
|
T1 |
64 |
|
T12 |
344489 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1735178 |
1 |
|
|
T21 |
4 |
|
T12 |
109345 |
|
T13 |
17653 |
| auto[1] |
auto[0] |
auto[1] |
1196282 |
1 |
|
|
T21 |
5 |
|
T1 |
64 |
|
T12 |
63736 |
| auto[1] |
auto[1] |
auto[0] |
1755967 |
1 |
|
|
T21 |
11 |
|
T12 |
108141 |
|
T13 |
17132 |
| auto[1] |
auto[1] |
auto[1] |
1198225 |
1 |
|
|
T12 |
63267 |
|
T13 |
9706 |
|
T15 |
52325 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |