Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7937595 |
1 |
|
|
T21 |
55 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5825503 |
1 |
|
|
T21 |
27 |
|
T1 |
52 |
|
T12 |
340848 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11381126 |
1 |
|
|
T21 |
67 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2381972 |
1 |
|
|
T21 |
15 |
|
T1 |
18 |
|
T12 |
129357 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7906123 |
1 |
|
|
T21 |
65 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5856975 |
1 |
|
|
T21 |
17 |
|
T1 |
63 |
|
T12 |
351028 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1754179 |
1 |
|
|
T21 |
2 |
|
T1 |
16 |
|
T12 |
115377 |
| auto[1] |
auto[0] |
auto[1] |
1198196 |
1 |
|
|
T21 |
8 |
|
T1 |
10 |
|
T12 |
65621 |
| auto[1] |
auto[1] |
auto[0] |
1720824 |
1 |
|
|
T1 |
29 |
|
T12 |
106294 |
|
T13 |
17721 |
| auto[1] |
auto[1] |
auto[1] |
1183776 |
1 |
|
|
T21 |
7 |
|
T1 |
8 |
|
T12 |
63736 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |