Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7929015 |
1 |
|
|
T21 |
53 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5834083 |
1 |
|
|
T21 |
29 |
|
T1 |
79 |
|
T12 |
337939 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11393002 |
1 |
|
|
T21 |
75 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2370096 |
1 |
|
|
T21 |
7 |
|
T1 |
13 |
|
T12 |
126068 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7941013 |
1 |
|
|
T21 |
70 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5822085 |
1 |
|
|
T21 |
12 |
|
T1 |
13 |
|
T12 |
344337 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1728172 |
1 |
|
|
T21 |
5 |
|
T12 |
108811 |
|
T13 |
16694 |
| auto[1] |
auto[0] |
auto[1] |
1185794 |
1 |
|
|
T21 |
4 |
|
T12 |
63620 |
|
T13 |
9368 |
| auto[1] |
auto[1] |
auto[0] |
1723817 |
1 |
|
|
T12 |
109458 |
|
T13 |
17314 |
|
T15 |
88065 |
| auto[1] |
auto[1] |
auto[1] |
1184302 |
1 |
|
|
T21 |
3 |
|
T1 |
13 |
|
T12 |
62448 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |