Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7911125 |
1 |
|
|
T21 |
37 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5851973 |
1 |
|
|
T21 |
45 |
|
T1 |
121 |
|
T12 |
339767 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11381912 |
1 |
|
|
T21 |
69 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2381186 |
1 |
|
|
T21 |
13 |
|
T1 |
107 |
|
T12 |
125773 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7898592 |
1 |
|
|
T21 |
63 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5864506 |
1 |
|
|
T21 |
19 |
|
T1 |
138 |
|
T12 |
342227 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1744411 |
1 |
|
|
T21 |
2 |
|
T12 |
109144 |
|
T13 |
17253 |
| auto[1] |
auto[0] |
auto[1] |
1194704 |
1 |
|
|
T21 |
1 |
|
T1 |
20 |
|
T12 |
63204 |
| auto[1] |
auto[1] |
auto[0] |
1738909 |
1 |
|
|
T21 |
4 |
|
T1 |
31 |
|
T12 |
107310 |
| auto[1] |
auto[1] |
auto[1] |
1186482 |
1 |
|
|
T21 |
12 |
|
T1 |
87 |
|
T12 |
62569 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |