Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7902386 |
1 |
|
|
T21 |
38 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5860712 |
1 |
|
|
T21 |
44 |
|
T1 |
53 |
|
T12 |
339003 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11384529 |
1 |
|
|
T21 |
77 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2378569 |
1 |
|
|
T21 |
5 |
|
T1 |
41 |
|
T12 |
128337 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7902674 |
1 |
|
|
T21 |
59 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5860424 |
1 |
|
|
T21 |
23 |
|
T1 |
72 |
|
T12 |
348905 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1747875 |
1 |
|
|
T21 |
1 |
|
T1 |
12 |
|
T12 |
111416 |
| auto[1] |
auto[0] |
auto[1] |
1193255 |
1 |
|
|
T21 |
2 |
|
T1 |
20 |
|
T12 |
65197 |
| auto[1] |
auto[1] |
auto[0] |
1733980 |
1 |
|
|
T21 |
17 |
|
T1 |
19 |
|
T12 |
109152 |
| auto[1] |
auto[1] |
auto[1] |
1185314 |
1 |
|
|
T21 |
3 |
|
T1 |
21 |
|
T12 |
63140 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |