Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7880119 |
1 |
|
|
T21 |
63 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5882979 |
1 |
|
|
T21 |
19 |
|
T1 |
25 |
|
T12 |
347334 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11380618 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2382480 |
1 |
|
|
T21 |
1 |
|
T1 |
39 |
|
T12 |
127889 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7891114 |
1 |
|
|
T21 |
74 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5871984 |
1 |
|
|
T21 |
8 |
|
T1 |
63 |
|
T12 |
350485 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1736699 |
1 |
|
|
T21 |
7 |
|
T1 |
15 |
|
T12 |
110264 |
| auto[1] |
auto[0] |
auto[1] |
1188296 |
1 |
|
|
T21 |
1 |
|
T1 |
27 |
|
T12 |
62500 |
| auto[1] |
auto[1] |
auto[0] |
1752805 |
1 |
|
|
T1 |
9 |
|
T12 |
112332 |
|
T13 |
17290 |
| auto[1] |
auto[1] |
auto[1] |
1194184 |
1 |
|
|
T1 |
12 |
|
T12 |
65389 |
|
T13 |
10427 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |