Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7894082 |
1 |
|
|
T21 |
46 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5869016 |
1 |
|
|
T21 |
36 |
|
T1 |
69 |
|
T12 |
351947 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11378025 |
1 |
|
|
T21 |
75 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2385073 |
1 |
|
|
T21 |
7 |
|
T1 |
44 |
|
T12 |
129321 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7882440 |
1 |
|
|
T21 |
72 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5880658 |
1 |
|
|
T21 |
10 |
|
T1 |
59 |
|
T12 |
353637 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1734230 |
1 |
|
|
T21 |
3 |
|
T1 |
4 |
|
T12 |
104325 |
| auto[1] |
auto[0] |
auto[1] |
1185716 |
1 |
|
|
T21 |
3 |
|
T1 |
20 |
|
T12 |
61333 |
| auto[1] |
auto[1] |
auto[0] |
1761355 |
1 |
|
|
T1 |
11 |
|
T12 |
119991 |
|
T13 |
17953 |
| auto[1] |
auto[1] |
auto[1] |
1199357 |
1 |
|
|
T21 |
4 |
|
T1 |
24 |
|
T12 |
67988 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |