Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7883260 |
1 |
|
|
T21 |
48 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5879838 |
1 |
|
|
T21 |
34 |
|
T1 |
114 |
|
T12 |
338725 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11366903 |
1 |
|
|
T21 |
77 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2396195 |
1 |
|
|
T21 |
5 |
|
T1 |
57 |
|
T12 |
130379 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7869395 |
1 |
|
|
T21 |
73 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5893703 |
1 |
|
|
T21 |
9 |
|
T1 |
83 |
|
T12 |
350893 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1736738 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T12 |
111484 |
| auto[1] |
auto[0] |
auto[1] |
1194296 |
1 |
|
|
T21 |
2 |
|
T1 |
10 |
|
T12 |
66150 |
| auto[1] |
auto[1] |
auto[0] |
1760770 |
1 |
|
|
T21 |
3 |
|
T1 |
24 |
|
T12 |
109030 |
| auto[1] |
auto[1] |
auto[1] |
1201899 |
1 |
|
|
T21 |
3 |
|
T1 |
47 |
|
T12 |
64229 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |