Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7912348 |
1 |
|
|
T21 |
52 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5850750 |
1 |
|
|
T21 |
30 |
|
T1 |
71 |
|
T12 |
345671 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13008132 |
1 |
|
|
T21 |
82 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
754966 |
1 |
|
|
T1 |
4 |
|
T12 |
41679 |
|
T13 |
6401 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7906744 |
1 |
|
|
T21 |
65 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5856354 |
1 |
|
|
T21 |
17 |
|
T1 |
114 |
|
T12 |
339318 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2545004 |
1 |
|
|
T21 |
10 |
|
T1 |
46 |
|
T12 |
143430 |
| auto[1] |
auto[0] |
auto[1] |
376219 |
1 |
|
|
T1 |
1 |
|
T12 |
19883 |
|
T13 |
3258 |
| auto[1] |
auto[1] |
auto[0] |
2556384 |
1 |
|
|
T21 |
7 |
|
T1 |
64 |
|
T12 |
154209 |
| auto[1] |
auto[1] |
auto[1] |
378747 |
1 |
|
|
T1 |
3 |
|
T12 |
21796 |
|
T13 |
3143 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |