Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7870053 |
1 |
|
|
T21 |
77 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5893045 |
1 |
|
|
T21 |
5 |
|
T1 |
78 |
|
T12 |
350661 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11378606 |
1 |
|
|
T21 |
69 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2384492 |
1 |
|
|
T21 |
13 |
|
T1 |
81 |
|
T12 |
129053 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7905296 |
1 |
|
|
T21 |
60 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5857802 |
1 |
|
|
T21 |
22 |
|
T1 |
100 |
|
T12 |
351771 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1719693 |
1 |
|
|
T21 |
9 |
|
T1 |
8 |
|
T12 |
107010 |
| auto[1] |
auto[0] |
auto[1] |
1186050 |
1 |
|
|
T21 |
13 |
|
T1 |
28 |
|
T12 |
62209 |
| auto[1] |
auto[1] |
auto[0] |
1753617 |
1 |
|
|
T1 |
11 |
|
T12 |
115708 |
|
T13 |
17460 |
| auto[1] |
auto[1] |
auto[1] |
1198442 |
1 |
|
|
T1 |
53 |
|
T12 |
66844 |
|
T13 |
9621 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |