Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7889593 |
1 |
|
|
T21 |
58 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5873505 |
1 |
|
|
T21 |
24 |
|
T1 |
16 |
|
T12 |
332027 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11385169 |
1 |
|
|
T21 |
79 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
2377929 |
1 |
|
|
T21 |
3 |
|
T1 |
13 |
|
T12 |
128643 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7922589 |
1 |
|
|
T21 |
59 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5840509 |
1 |
|
|
T21 |
23 |
|
T1 |
13 |
|
T12 |
350640 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1722884 |
1 |
|
|
T21 |
14 |
|
T12 |
116543 |
|
T13 |
17746 |
| auto[1] |
auto[0] |
auto[1] |
1186378 |
1 |
|
|
T21 |
3 |
|
T1 |
13 |
|
T12 |
66847 |
| auto[1] |
auto[1] |
auto[0] |
1739696 |
1 |
|
|
T21 |
6 |
|
T12 |
105454 |
|
T13 |
17897 |
| auto[1] |
auto[1] |
auto[1] |
1191551 |
1 |
|
|
T12 |
61796 |
|
T13 |
9824 |
|
T15 |
51242 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |