Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7926860 |
1 |
|
|
T21 |
66 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5836238 |
1 |
|
|
T21 |
16 |
|
T1 |
87 |
|
T12 |
341596 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13013001 |
1 |
|
|
T21 |
82 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
750097 |
1 |
|
|
T1 |
7 |
|
T12 |
42676 |
|
T13 |
6164 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7922230 |
1 |
|
|
T21 |
61 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5840868 |
1 |
|
|
T21 |
21 |
|
T1 |
92 |
|
T12 |
342616 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2564804 |
1 |
|
|
T21 |
15 |
|
T1 |
48 |
|
T12 |
154406 |
| auto[1] |
auto[0] |
auto[1] |
377310 |
1 |
|
|
T1 |
2 |
|
T12 |
21949 |
|
T13 |
2918 |
| auto[1] |
auto[1] |
auto[0] |
2525967 |
1 |
|
|
T21 |
6 |
|
T1 |
37 |
|
T12 |
145534 |
| auto[1] |
auto[1] |
auto[1] |
372787 |
1 |
|
|
T1 |
5 |
|
T12 |
20727 |
|
T13 |
3246 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |