Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7916561 |
1 |
|
|
T21 |
71 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5846537 |
1 |
|
|
T21 |
11 |
|
T1 |
53 |
|
T12 |
346894 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13010993 |
1 |
|
|
T21 |
82 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
752105 |
1 |
|
|
T1 |
1 |
|
T12 |
42687 |
|
T13 |
6171 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7929053 |
1 |
|
|
T21 |
77 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5834045 |
1 |
|
|
T21 |
5 |
|
T1 |
66 |
|
T12 |
341826 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2553889 |
1 |
|
|
T21 |
5 |
|
T1 |
38 |
|
T12 |
152515 |
| auto[1] |
auto[0] |
auto[1] |
378075 |
1 |
|
|
T12 |
21973 |
|
T13 |
2748 |
|
T15 |
17069 |
| auto[1] |
auto[1] |
auto[0] |
2528051 |
1 |
|
|
T1 |
27 |
|
T12 |
146624 |
|
T13 |
25236 |
| auto[1] |
auto[1] |
auto[1] |
374030 |
1 |
|
|
T1 |
1 |
|
T12 |
20714 |
|
T13 |
3423 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |