Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7915945 |
1 |
|
|
T21 |
54 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5847153 |
1 |
|
|
T21 |
28 |
|
T1 |
79 |
|
T12 |
346611 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13004111 |
1 |
|
|
T21 |
82 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
758987 |
1 |
|
|
T1 |
4 |
|
T12 |
43757 |
|
T13 |
6116 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7879972 |
1 |
|
|
T21 |
67 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5883126 |
1 |
|
|
T21 |
15 |
|
T1 |
38 |
|
T12 |
348395 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2575766 |
1 |
|
|
T21 |
6 |
|
T1 |
17 |
|
T12 |
153152 |
| auto[1] |
auto[0] |
auto[1] |
382309 |
1 |
|
|
T1 |
3 |
|
T12 |
21977 |
|
T13 |
2852 |
| auto[1] |
auto[1] |
auto[0] |
2548373 |
1 |
|
|
T21 |
9 |
|
T1 |
17 |
|
T12 |
151486 |
| auto[1] |
auto[1] |
auto[1] |
376678 |
1 |
|
|
T1 |
1 |
|
T12 |
21780 |
|
T13 |
3264 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |