Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7878670 |
1 |
|
|
T21 |
46 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5884428 |
1 |
|
|
T21 |
36 |
|
T1 |
69 |
|
T12 |
348823 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13011798 |
1 |
|
|
T21 |
82 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
751300 |
1 |
|
|
T1 |
8 |
|
T12 |
43536 |
|
T13 |
6541 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7926714 |
1 |
|
|
T21 |
68 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5836384 |
1 |
|
|
T21 |
14 |
|
T1 |
77 |
|
T12 |
350453 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2546301 |
1 |
|
|
T21 |
3 |
|
T1 |
32 |
|
T12 |
150481 |
| auto[1] |
auto[0] |
auto[1] |
376305 |
1 |
|
|
T1 |
6 |
|
T12 |
21181 |
|
T13 |
3388 |
| auto[1] |
auto[1] |
auto[0] |
2538783 |
1 |
|
|
T21 |
11 |
|
T1 |
37 |
|
T12 |
156436 |
| auto[1] |
auto[1] |
auto[1] |
374995 |
1 |
|
|
T1 |
2 |
|
T12 |
22355 |
|
T13 |
3153 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |