Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7941443 |
1 |
|
|
T21 |
57 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5821655 |
1 |
|
|
T21 |
25 |
|
T1 |
47 |
|
T12 |
335745 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13011872 |
1 |
|
|
T21 |
81 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
751226 |
1 |
|
|
T21 |
1 |
|
T1 |
4 |
|
T12 |
42036 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7917292 |
1 |
|
|
T21 |
72 |
|
T24 |
1 |
|
T25 |
23163 |
| auto[1] |
5845806 |
1 |
|
|
T21 |
10 |
|
T1 |
83 |
|
T12 |
339651 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2578241 |
1 |
|
|
T21 |
9 |
|
T1 |
59 |
|
T12 |
154988 |
| auto[1] |
auto[0] |
auto[1] |
381030 |
1 |
|
|
T21 |
1 |
|
T1 |
4 |
|
T12 |
22096 |
| auto[1] |
auto[1] |
auto[0] |
2516339 |
1 |
|
|
T1 |
20 |
|
T12 |
142627 |
|
T13 |
22045 |
| auto[1] |
auto[1] |
auto[1] |
370196 |
1 |
|
|
T12 |
19940 |
|
T13 |
2817 |
|
T15 |
18251 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |