Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 941
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T75 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.4135068848 Mar 03 03:06:54 PM PST 24 Mar 03 03:06:55 PM PST 24 41769890 ps
T766 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2230218410 Mar 03 03:06:52 PM PST 24 Mar 03 03:06:52 PM PST 24 11413052 ps
T767 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3438244824 Mar 03 03:07:01 PM PST 24 Mar 03 03:07:02 PM PST 24 115759478 ps
T768 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1241264454 Mar 03 03:06:51 PM PST 24 Mar 03 03:06:52 PM PST 24 34311636 ps
T769 /workspace/coverage/cover_reg_top/2.gpio_intr_test.5447819 Mar 03 03:06:52 PM PST 24 Mar 03 03:06:53 PM PST 24 83441181 ps
T770 /workspace/coverage/cover_reg_top/11.gpio_intr_test.3059388528 Mar 03 03:07:01 PM PST 24 Mar 03 03:07:01 PM PST 24 14053812 ps
T771 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2227204019 Mar 03 03:07:12 PM PST 24 Mar 03 03:07:12 PM PST 24 47791925 ps
T772 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.798404902 Mar 03 03:06:49 PM PST 24 Mar 03 03:06:50 PM PST 24 106266820 ps
T773 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.634267175 Mar 03 03:06:57 PM PST 24 Mar 03 03:06:58 PM PST 24 232567430 ps
T76 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1786010026 Mar 03 03:06:52 PM PST 24 Mar 03 03:06:53 PM PST 24 63739982 ps
T38 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.118716444 Mar 03 03:06:58 PM PST 24 Mar 03 03:07:00 PM PST 24 181346294 ps
T774 /workspace/coverage/cover_reg_top/43.gpio_intr_test.1570224989 Mar 03 03:07:14 PM PST 24 Mar 03 03:07:14 PM PST 24 47255162 ps
T775 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2634303764 Mar 03 03:06:56 PM PST 24 Mar 03 03:06:57 PM PST 24 58064210 ps
T77 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.379321995 Mar 03 03:06:54 PM PST 24 Mar 03 03:06:55 PM PST 24 144604454 ps
T776 /workspace/coverage/cover_reg_top/1.gpio_intr_test.790487268 Mar 03 03:06:51 PM PST 24 Mar 03 03:06:52 PM PST 24 12182235 ps
T777 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2150743275 Mar 03 03:07:15 PM PST 24 Mar 03 03:07:15 PM PST 24 27260300 ps
T778 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.731049678 Mar 03 03:07:03 PM PST 24 Mar 03 03:07:05 PM PST 24 85551945 ps
T78 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1864769265 Mar 03 03:06:54 PM PST 24 Mar 03 03:06:55 PM PST 24 29553289 ps
T779 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2256000111 Mar 03 03:06:52 PM PST 24 Mar 03 03:06:54 PM PST 24 241871775 ps
T780 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1256632804 Mar 03 03:06:54 PM PST 24 Mar 03 03:06:56 PM PST 24 105631482 ps
T781 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2795175655 Mar 03 03:07:16 PM PST 24 Mar 03 03:07:18 PM PST 24 33122330 ps
T782 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1125365201 Mar 03 03:06:51 PM PST 24 Mar 03 03:06:54 PM PST 24 135738058 ps
T783 /workspace/coverage/cover_reg_top/5.gpio_intr_test.3890720814 Mar 03 03:06:50 PM PST 24 Mar 03 03:06:51 PM PST 24 14877751 ps
T784 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1237122946 Mar 03 03:07:09 PM PST 24 Mar 03 03:07:10 PM PST 24 40509953 ps
T785 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.300283702 Mar 03 03:07:04 PM PST 24 Mar 03 03:07:07 PM PST 24 460120479 ps
T786 /workspace/coverage/cover_reg_top/28.gpio_intr_test.2018601820 Mar 03 03:07:26 PM PST 24 Mar 03 03:07:27 PM PST 24 78550171 ps
T79 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2136597673 Mar 03 03:07:00 PM PST 24 Mar 03 03:07:01 PM PST 24 14282786 ps
T93 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.432363706 Mar 03 03:06:52 PM PST 24 Mar 03 03:06:53 PM PST 24 78613809 ps
T787 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1221985142 Mar 03 03:06:50 PM PST 24 Mar 03 03:06:51 PM PST 24 31496108 ps
T788 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1899359102 Mar 03 03:06:51 PM PST 24 Mar 03 03:06:53 PM PST 24 71719183 ps
T789 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3561589397 Mar 03 03:06:51 PM PST 24 Mar 03 03:06:52 PM PST 24 31276409 ps
T790 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3601006657 Mar 03 03:07:03 PM PST 24 Mar 03 03:07:04 PM PST 24 17824528 ps
T791 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.589381903 Mar 03 03:07:06 PM PST 24 Mar 03 03:07:07 PM PST 24 319265300 ps
T792 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2562845030 Mar 03 03:07:05 PM PST 24 Mar 03 03:07:06 PM PST 24 13169279 ps
T793 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1820537387 Mar 03 03:07:04 PM PST 24 Mar 03 03:07:07 PM PST 24 92066071 ps
T794 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.483980705 Mar 03 03:06:57 PM PST 24 Mar 03 03:06:57 PM PST 24 59721623 ps
T795 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.143048734 Mar 03 03:06:51 PM PST 24 Mar 03 03:06:52 PM PST 24 26012985 ps
T84 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3223704509 Mar 03 03:07:07 PM PST 24 Mar 03 03:07:08 PM PST 24 11388825 ps
T41 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2885020134 Mar 03 03:06:50 PM PST 24 Mar 03 03:06:51 PM PST 24 901345879 ps
T796 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1501453517 Mar 03 03:07:16 PM PST 24 Mar 03 03:07:17 PM PST 24 66120777 ps
T797 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2418224130 Mar 03 03:06:52 PM PST 24 Mar 03 03:06:53 PM PST 24 14348845 ps
T798 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1916370463 Mar 03 03:06:58 PM PST 24 Mar 03 03:06:59 PM PST 24 29377250 ps
T82 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2551908354 Mar 03 03:07:03 PM PST 24 Mar 03 03:07:04 PM PST 24 34734237 ps
T799 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.28418032 Mar 03 03:07:00 PM PST 24 Mar 03 03:07:01 PM PST 24 24337422 ps
T800 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2688475980 Mar 03 03:07:02 PM PST 24 Mar 03 03:07:03 PM PST 24 285633918 ps
T801 /workspace/coverage/cover_reg_top/15.gpio_intr_test.4153268536 Mar 03 03:07:09 PM PST 24 Mar 03 03:07:10 PM PST 24 12285717 ps
T802 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3164521559 Mar 03 03:06:52 PM PST 24 Mar 03 03:06:52 PM PST 24 11737983 ps
T803 /workspace/coverage/cover_reg_top/41.gpio_intr_test.397075326 Mar 03 03:07:17 PM PST 24 Mar 03 03:07:18 PM PST 24 36522249 ps
T804 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2292801226 Mar 03 03:06:53 PM PST 24 Mar 03 03:06:54 PM PST 24 34313777 ps
T805 /workspace/coverage/cover_reg_top/9.gpio_intr_test.3740885879 Mar 03 03:06:57 PM PST 24 Mar 03 03:06:58 PM PST 24 14977855 ps
T806 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3314122527 Mar 03 03:07:03 PM PST 24 Mar 03 03:07:04 PM PST 24 19594461 ps
T807 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3390875839 Mar 03 03:06:51 PM PST 24 Mar 03 03:06:52 PM PST 24 370705763 ps
T808 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1654709631 Mar 03 03:06:45 PM PST 24 Mar 03 03:06:46 PM PST 24 33472802 ps
T809 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1128941691 Mar 03 03:07:13 PM PST 24 Mar 03 03:07:14 PM PST 24 14988902 ps
T810 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3184915585 Mar 03 03:07:00 PM PST 24 Mar 03 03:07:03 PM PST 24 93393334 ps
T42 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3418777024 Mar 03 03:07:00 PM PST 24 Mar 03 03:07:02 PM PST 24 1510581980 ps
T811 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1885601334 Mar 03 03:07:11 PM PST 24 Mar 03 03:07:12 PM PST 24 26063365 ps
T812 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3746066792 Mar 03 03:07:04 PM PST 24 Mar 03 03:07:06 PM PST 24 434847390 ps
T813 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2328255364 Mar 03 03:06:57 PM PST 24 Mar 03 03:06:58 PM PST 24 166674717 ps
T814 /workspace/coverage/cover_reg_top/25.gpio_intr_test.384858686 Mar 03 03:07:13 PM PST 24 Mar 03 03:07:14 PM PST 24 11712620 ps
T815 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.683135943 Mar 03 03:07:06 PM PST 24 Mar 03 03:07:07 PM PST 24 24712778 ps
T44 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2650911866 Mar 03 03:06:53 PM PST 24 Mar 03 03:06:55 PM PST 24 130191861 ps
T816 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3940253082 Mar 03 03:07:08 PM PST 24 Mar 03 03:07:08 PM PST 24 12812355 ps
T817 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3876565582 Mar 03 03:06:52 PM PST 24 Mar 03 03:06:52 PM PST 24 50237983 ps
T83 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.68822725 Mar 03 03:07:09 PM PST 24 Mar 03 03:07:10 PM PST 24 49831326 ps
T818 /workspace/coverage/cover_reg_top/22.gpio_intr_test.3506083039 Mar 03 03:07:12 PM PST 24 Mar 03 03:07:13 PM PST 24 46905832 ps
T39 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3126405570 Mar 03 03:06:52 PM PST 24 Mar 03 03:06:54 PM PST 24 585752100 ps
T819 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2745533088 Mar 03 03:07:07 PM PST 24 Mar 03 03:07:07 PM PST 24 32786043 ps
T820 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2896093725 Mar 03 03:07:14 PM PST 24 Mar 03 03:07:15 PM PST 24 42563096 ps
T821 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.767594559 Mar 03 03:07:06 PM PST 24 Mar 03 03:07:08 PM PST 24 86026307 ps
T822 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2552289159 Mar 03 03:06:50 PM PST 24 Mar 03 03:06:52 PM PST 24 151938899 ps
T823 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.723781683 Mar 03 03:07:01 PM PST 24 Mar 03 03:07:02 PM PST 24 83205019 ps
T824 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1425553558 Mar 03 03:07:07 PM PST 24 Mar 03 03:07:08 PM PST 24 33310224 ps
T80 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1678553725 Mar 03 03:07:06 PM PST 24 Mar 03 03:07:07 PM PST 24 16333397 ps
T825 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2849652893 Mar 03 03:07:03 PM PST 24 Mar 03 03:07:04 PM PST 24 21978022 ps
T826 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.423606657 Mar 03 03:06:50 PM PST 24 Mar 03 03:06:51 PM PST 24 116559321 ps
T827 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3816486481 Mar 03 03:07:07 PM PST 24 Mar 03 03:07:08 PM PST 24 23981593 ps
T828 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2411914029 Mar 03 03:06:56 PM PST 24 Mar 03 03:06:57 PM PST 24 18062011 ps
T829 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.143501155 Mar 03 03:06:58 PM PST 24 Mar 03 03:06:59 PM PST 24 17220857 ps
T830 /workspace/coverage/cover_reg_top/4.gpio_intr_test.327355848 Mar 03 03:06:53 PM PST 24 Mar 03 03:06:53 PM PST 24 33430045 ps
T831 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2887079745 Mar 03 03:06:57 PM PST 24 Mar 03 03:06:58 PM PST 24 125824820 ps
T832 /workspace/coverage/cover_reg_top/31.gpio_intr_test.1184913193 Mar 03 03:07:16 PM PST 24 Mar 03 03:07:17 PM PST 24 39422522 ps
T833 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.715506655 Mar 03 03:07:04 PM PST 24 Mar 03 03:07:07 PM PST 24 116662592 ps
T834 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3975785770 Mar 03 03:07:05 PM PST 24 Mar 03 03:07:08 PM PST 24 974878141 ps
T835 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.737761351 Mar 03 03:07:06 PM PST 24 Mar 03 03:07:07 PM PST 24 37424379 ps
T836 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1839299710 Mar 03 03:07:00 PM PST 24 Mar 03 03:07:01 PM PST 24 166216270 ps
T837 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2971519027 Mar 03 03:06:50 PM PST 24 Mar 03 03:06:52 PM PST 24 122636915 ps
T838 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3090104615 Mar 03 03:07:11 PM PST 24 Mar 03 03:07:12 PM PST 24 101906606 ps
T839 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4000407046 Mar 03 03:06:55 PM PST 24 Mar 03 03:06:57 PM PST 24 178859051 ps
T840 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2507737623 Mar 03 03:07:04 PM PST 24 Mar 03 03:07:06 PM PST 24 44721712 ps
T841 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1111508983 Mar 03 03:06:51 PM PST 24 Mar 03 03:06:53 PM PST 24 609473712 ps
T842 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1375842455 Mar 03 12:42:45 PM PST 24 Mar 03 12:42:48 PM PST 24 82232317 ps
T843 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2726379591 Mar 03 12:42:35 PM PST 24 Mar 03 12:42:37 PM PST 24 173360042 ps
T844 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3685647234 Mar 03 12:42:32 PM PST 24 Mar 03 12:42:33 PM PST 24 24721196 ps
T845 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.773097292 Mar 03 12:42:44 PM PST 24 Mar 03 12:42:45 PM PST 24 28269507 ps
T846 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2195607568 Mar 03 12:42:53 PM PST 24 Mar 03 12:42:55 PM PST 24 82171794 ps
T847 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3328663716 Mar 03 12:42:44 PM PST 24 Mar 03 12:42:45 PM PST 24 192938766 ps
T848 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3071416043 Mar 03 12:42:54 PM PST 24 Mar 03 12:42:56 PM PST 24 78006031 ps
T849 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4179928933 Mar 03 12:42:54 PM PST 24 Mar 03 12:42:55 PM PST 24 25178926 ps
T850 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.39068089 Mar 03 12:42:29 PM PST 24 Mar 03 12:42:30 PM PST 24 108866931 ps
T851 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3373169018 Mar 03 12:42:34 PM PST 24 Mar 03 12:42:35 PM PST 24 134750263 ps
T852 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2100510557 Mar 03 12:42:55 PM PST 24 Mar 03 12:42:57 PM PST 24 126743037 ps
T853 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3124263743 Mar 03 12:42:54 PM PST 24 Mar 03 12:42:57 PM PST 24 195780224 ps
T854 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3742649048 Mar 03 12:42:56 PM PST 24 Mar 03 12:42:58 PM PST 24 73094008 ps
T855 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.171072754 Mar 03 12:42:44 PM PST 24 Mar 03 12:42:46 PM PST 24 154148793 ps
T856 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1723000345 Mar 03 12:42:55 PM PST 24 Mar 03 12:42:57 PM PST 24 71192530 ps
T857 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1625860107 Mar 03 12:42:35 PM PST 24 Mar 03 12:42:37 PM PST 24 63885184 ps
T858 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1248064098 Mar 03 12:42:42 PM PST 24 Mar 03 12:42:44 PM PST 24 124698476 ps
T859 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1767762535 Mar 03 12:42:53 PM PST 24 Mar 03 12:42:55 PM PST 24 158923681 ps
T860 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2013144403 Mar 03 12:42:39 PM PST 24 Mar 03 12:42:40 PM PST 24 35979813 ps
T861 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.904811382 Mar 03 12:42:35 PM PST 24 Mar 03 12:42:37 PM PST 24 133468840 ps
T862 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3528817927 Mar 03 12:42:53 PM PST 24 Mar 03 12:42:55 PM PST 24 185863716 ps
T863 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2076919453 Mar 03 12:42:36 PM PST 24 Mar 03 12:42:37 PM PST 24 192865172 ps
T864 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3881788624 Mar 03 12:42:34 PM PST 24 Mar 03 12:42:35 PM PST 24 208309392 ps
T865 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.268890518 Mar 03 12:42:35 PM PST 24 Mar 03 12:42:36 PM PST 24 130635597 ps
T866 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2407513421 Mar 03 12:42:28 PM PST 24 Mar 03 12:42:30 PM PST 24 204582475 ps
T867 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3436125056 Mar 03 12:42:43 PM PST 24 Mar 03 12:42:45 PM PST 24 113307507 ps
T868 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4131730126 Mar 03 12:42:28 PM PST 24 Mar 03 12:42:29 PM PST 24 51657222 ps
T869 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.117551625 Mar 03 12:42:54 PM PST 24 Mar 03 12:42:55 PM PST 24 84010795 ps
T870 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3163065061 Mar 03 12:42:46 PM PST 24 Mar 03 12:42:48 PM PST 24 63247646 ps
T871 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4151507395 Mar 03 12:42:46 PM PST 24 Mar 03 12:42:49 PM PST 24 58755937 ps
T872 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3800320241 Mar 03 12:42:37 PM PST 24 Mar 03 12:42:39 PM PST 24 175352490 ps
T873 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1534284509 Mar 03 12:42:34 PM PST 24 Mar 03 12:42:36 PM PST 24 50144043 ps
T874 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.987112630 Mar 03 12:42:35 PM PST 24 Mar 03 12:42:36 PM PST 24 83292567 ps
T875 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.529448070 Mar 03 12:42:37 PM PST 24 Mar 03 12:42:39 PM PST 24 205671702 ps
T876 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.422352136 Mar 03 12:42:45 PM PST 24 Mar 03 12:42:47 PM PST 24 28262316 ps
T877 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2625254126 Mar 03 12:42:43 PM PST 24 Mar 03 12:42:45 PM PST 24 70512513 ps
T878 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3539819493 Mar 03 12:42:36 PM PST 24 Mar 03 12:42:37 PM PST 24 95811611 ps
T879 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.449361248 Mar 03 12:42:35 PM PST 24 Mar 03 12:42:35 PM PST 24 52912085 ps
T880 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.148429154 Mar 03 12:42:53 PM PST 24 Mar 03 12:42:55 PM PST 24 223767240 ps
T881 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1035378119 Mar 03 12:42:54 PM PST 24 Mar 03 12:42:56 PM PST 24 86782381 ps
T882 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3058997081 Mar 03 12:42:43 PM PST 24 Mar 03 12:42:45 PM PST 24 131952197 ps
T883 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1045137291 Mar 03 12:42:55 PM PST 24 Mar 03 12:42:56 PM PST 24 113158392 ps
T884 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3753184514 Mar 03 12:42:56 PM PST 24 Mar 03 12:42:58 PM PST 24 55922433 ps
T885 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2845796855 Mar 03 12:42:45 PM PST 24 Mar 03 12:42:48 PM PST 24 46544650 ps
T886 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3632431506 Mar 03 12:42:46 PM PST 24 Mar 03 12:42:48 PM PST 24 277067900 ps
T887 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3787998891 Mar 03 12:42:34 PM PST 24 Mar 03 12:42:35 PM PST 24 226433492 ps
T888 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.587467741 Mar 03 12:42:45 PM PST 24 Mar 03 12:42:47 PM PST 24 148911384 ps
T889 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.49710211 Mar 03 12:42:54 PM PST 24 Mar 03 12:42:56 PM PST 24 329828993 ps
T890 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1459643151 Mar 03 12:42:55 PM PST 24 Mar 03 12:42:56 PM PST 24 156274552 ps
T891 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3641761489 Mar 03 12:42:43 PM PST 24 Mar 03 12:42:44 PM PST 24 219677837 ps
T892 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1923932201 Mar 03 12:42:34 PM PST 24 Mar 03 12:42:35 PM PST 24 35139951 ps
T893 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2950129638 Mar 03 12:42:55 PM PST 24 Mar 03 12:42:56 PM PST 24 290774206 ps
T894 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2726641348 Mar 03 12:42:27 PM PST 24 Mar 03 12:42:28 PM PST 24 54539320 ps
T895 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2183959436 Mar 03 12:42:45 PM PST 24 Mar 03 12:42:48 PM PST 24 195900831 ps
T896 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4262419242 Mar 03 12:42:34 PM PST 24 Mar 03 12:42:36 PM PST 24 257134411 ps
T897 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1241499583 Mar 03 12:42:44 PM PST 24 Mar 03 12:42:46 PM PST 24 37031012 ps
T898 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.749753147 Mar 03 12:42:55 PM PST 24 Mar 03 12:42:57 PM PST 24 54916060 ps
T899 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3380729419 Mar 03 12:42:51 PM PST 24 Mar 03 12:42:53 PM PST 24 90818259 ps
T900 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4008501815 Mar 03 12:42:52 PM PST 24 Mar 03 12:42:54 PM PST 24 575095332 ps
T901 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.755007335 Mar 03 12:42:29 PM PST 24 Mar 03 12:42:30 PM PST 24 144634599 ps
T902 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3952145734 Mar 03 12:42:36 PM PST 24 Mar 03 12:42:37 PM PST 24 47414584 ps
T903 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.202565907 Mar 03 12:42:28 PM PST 24 Mar 03 12:42:29 PM PST 24 100578765 ps
T904 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.253087694 Mar 03 12:42:52 PM PST 24 Mar 03 12:42:53 PM PST 24 108271406 ps
T905 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3220019575 Mar 03 12:42:35 PM PST 24 Mar 03 12:42:37 PM PST 24 172710860 ps
T906 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.593614572 Mar 03 12:42:54 PM PST 24 Mar 03 12:42:56 PM PST 24 51997006 ps
T907 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3332514625 Mar 03 12:42:36 PM PST 24 Mar 03 12:42:37 PM PST 24 32968300 ps
T908 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.121732627 Mar 03 12:42:27 PM PST 24 Mar 03 12:42:29 PM PST 24 298105387 ps
T909 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2511218000 Mar 03 12:42:35 PM PST 24 Mar 03 12:42:36 PM PST 24 96253985 ps
T910 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2610155772 Mar 03 12:42:54 PM PST 24 Mar 03 12:42:56 PM PST 24 121617217 ps
T911 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4054992153 Mar 03 12:42:34 PM PST 24 Mar 03 12:42:36 PM PST 24 95445243 ps
T912 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2209225261 Mar 03 12:42:27 PM PST 24 Mar 03 12:42:29 PM PST 24 859592157 ps
T913 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.413679320 Mar 03 12:42:32 PM PST 24 Mar 03 12:42:33 PM PST 24 214646516 ps
T914 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1334968631 Mar 03 12:42:45 PM PST 24 Mar 03 12:42:48 PM PST 24 182146562 ps
T915 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1351236552 Mar 03 12:42:53 PM PST 24 Mar 03 12:42:55 PM PST 24 61700344 ps
T916 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1998002610 Mar 03 12:42:36 PM PST 24 Mar 03 12:42:38 PM PST 24 283035471 ps
T917 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4265109326 Mar 03 12:42:52 PM PST 24 Mar 03 12:42:53 PM PST 24 195729838 ps
T918 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.306111219 Mar 03 12:42:47 PM PST 24 Mar 03 12:42:50 PM PST 24 218221638 ps
T919 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4083781642 Mar 03 12:42:44 PM PST 24 Mar 03 12:42:45 PM PST 24 168463619 ps
T920 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2634019382 Mar 03 12:42:44 PM PST 24 Mar 03 12:42:45 PM PST 24 36903776 ps
T921 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2103055600 Mar 03 12:42:44 PM PST 24 Mar 03 12:42:45 PM PST 24 151226256 ps
T922 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.662768887 Mar 03 12:42:36 PM PST 24 Mar 03 12:42:38 PM PST 24 44096785 ps
T923 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1269885889 Mar 03 12:42:45 PM PST 24 Mar 03 12:42:47 PM PST 24 81094900 ps
T924 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.977804765 Mar 03 12:42:45 PM PST 24 Mar 03 12:42:48 PM PST 24 307012374 ps
T925 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2049417290 Mar 03 12:42:54 PM PST 24 Mar 03 12:42:56 PM PST 24 87546648 ps
T926 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3676967269 Mar 03 12:42:31 PM PST 24 Mar 03 12:42:32 PM PST 24 91063536 ps
T927 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2281268714 Mar 03 12:42:37 PM PST 24 Mar 03 12:42:38 PM PST 24 71637034 ps
T928 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2000395601 Mar 03 12:42:44 PM PST 24 Mar 03 12:42:46 PM PST 24 68938159 ps
T929 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3260396272 Mar 03 12:42:45 PM PST 24 Mar 03 12:42:48 PM PST 24 57419725 ps
T930 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2271344801 Mar 03 12:42:34 PM PST 24 Mar 03 12:42:35 PM PST 24 42386850 ps
T931 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4053343436 Mar 03 12:42:46 PM PST 24 Mar 03 12:42:48 PM PST 24 48208613 ps
T932 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2145007022 Mar 03 12:42:53 PM PST 24 Mar 03 12:42:55 PM PST 24 132961533 ps
T933 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.858439749 Mar 03 12:42:30 PM PST 24 Mar 03 12:42:31 PM PST 24 104242251 ps
T934 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3068535159 Mar 03 12:42:32 PM PST 24 Mar 03 12:42:34 PM PST 24 52115013 ps
T935 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.322611098 Mar 03 12:42:29 PM PST 24 Mar 03 12:42:30 PM PST 24 53226145 ps
T936 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.575402105 Mar 03 12:42:35 PM PST 24 Mar 03 12:42:37 PM PST 24 87379400 ps
T937 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.464493153 Mar 03 12:42:27 PM PST 24 Mar 03 12:42:29 PM PST 24 312845053 ps
T938 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.772330046 Mar 03 12:42:43 PM PST 24 Mar 03 12:42:43 PM PST 24 59059310 ps
T939 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2576379054 Mar 03 12:42:44 PM PST 24 Mar 03 12:42:45 PM PST 24 36042647 ps
T940 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1177592719 Mar 03 12:42:43 PM PST 24 Mar 03 12:42:44 PM PST 24 35151828 ps
T941 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1571111657 Mar 03 12:42:56 PM PST 24 Mar 03 12:42:58 PM PST 24 646511738 ps

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.1033881500
Short name T15
Test name
Test status
Simulation time 714277741885 ps
CPU time 1601.29 seconds
Started Mar 03 12:40:19 PM PST 24
Finished Mar 03 01:07:01 PM PST 24
Peak memory 198408 kb
Host smart-68db52b3-5efc-4e40-816a-0515b17e7fa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1033881500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.1033881500
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3594558516
Short name T19
Test name
Test status
Simulation time 55691230 ps
CPU time 2.23 seconds
Started Mar 03 12:39:09 PM PST 24
Finished Mar 03 12:39:12 PM PST 24
Peak memory 198080 kb
Host smart-9a7a266e-ae78-4f10-af29-1aa96a000674
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594558516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3594558516
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.402883568
Short name T32
Test name
Test status
Simulation time 150544574 ps
CPU time 0.78 seconds
Started Mar 03 12:39:02 PM PST 24
Finished Mar 03 12:39:03 PM PST 24
Peak memory 213824 kb
Host smart-32f1335c-0a7d-4268-9dda-69c6b18e7a16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402883568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.402883568
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.973258268
Short name T1
Test name
Test status
Simulation time 69896691 ps
CPU time 0.88 seconds
Started Mar 03 12:39:57 PM PST 24
Finished Mar 03 12:39:58 PM PST 24
Peak memory 197840 kb
Host smart-db46196d-9d2e-4a6f-a514-f5237f8b4289
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973258268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.973258268
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1864769265
Short name T78
Test name
Test status
Simulation time 29553289 ps
CPU time 0.74 seconds
Started Mar 03 03:06:54 PM PST 24
Finished Mar 03 03:06:55 PM PST 24
Peak memory 196504 kb
Host smart-835dd0fc-95a8-408e-8eb5-7ef1c146e566
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864769265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1864769265
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.468939734
Short name T28
Test name
Test status
Simulation time 420388558 ps
CPU time 1.55 seconds
Started Mar 03 03:07:00 PM PST 24
Finished Mar 03 03:07:02 PM PST 24
Peak memory 198616 kb
Host smart-e42c78c6-7bb7-4740-83d0-3683ef2e6af0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468939734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.468939734
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2677823996
Short name T64
Test name
Test status
Simulation time 69178852 ps
CPU time 0.66 seconds
Started Mar 03 03:06:56 PM PST 24
Finished Mar 03 03:06:57 PM PST 24
Peak memory 195936 kb
Host smart-ceefad52-170c-4eab-9c51-f8b38a056ee6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677823996 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2677823996
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2791464585
Short name T218
Test name
Test status
Simulation time 70125940 ps
CPU time 0.58 seconds
Started Mar 03 12:38:59 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 194240 kb
Host smart-0c941d57-1461-4ade-9435-8043ea39058b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791464585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2791464585
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3126405570
Short name T39
Test name
Test status
Simulation time 585752100 ps
CPU time 1.37 seconds
Started Mar 03 03:06:52 PM PST 24
Finished Mar 03 03:06:54 PM PST 24
Peak memory 198640 kb
Host smart-6a7822d9-40d6-426f-9594-66ce170b7394
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126405570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3126405570
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2650911866
Short name T44
Test name
Test status
Simulation time 130191861 ps
CPU time 1.5 seconds
Started Mar 03 03:06:53 PM PST 24
Finished Mar 03 03:06:55 PM PST 24
Peak memory 198592 kb
Host smart-fc65a550-1bad-4200-8644-53f2f5d9e782
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650911866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2650911866
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3600015752
Short name T71
Test name
Test status
Simulation time 38784829 ps
CPU time 0.68 seconds
Started Mar 03 03:06:56 PM PST 24
Finished Mar 03 03:06:57 PM PST 24
Peak memory 195840 kb
Host smart-5acec790-4f95-4c8b-ab85-e3ae9f277b3c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600015752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3600015752
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1368169721
Short name T754
Test name
Test status
Simulation time 853603255 ps
CPU time 2.92 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:54 PM PST 24
Peak memory 197684 kb
Host smart-7f84e65d-738a-4426-b696-bed8179f8f1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368169721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1368169721
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3052943447
Short name T91
Test name
Test status
Simulation time 59721940 ps
CPU time 0.64 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:52 PM PST 24
Peak memory 194960 kb
Host smart-dd8c07c3-ffb4-4726-b7e5-622f8ccb0e82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052943447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3052943447
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.143048734
Short name T795
Test name
Test status
Simulation time 26012985 ps
CPU time 0.86 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:52 PM PST 24
Peak memory 198464 kb
Host smart-ca407908-01f0-4938-8454-bb58ace9ed04
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143048734 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.143048734
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1654709631
Short name T808
Test name
Test status
Simulation time 33472802 ps
CPU time 0.62 seconds
Started Mar 03 03:06:45 PM PST 24
Finished Mar 03 03:06:46 PM PST 24
Peak memory 195244 kb
Host smart-542d0e6c-115d-40ef-848f-885c7e553321
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654709631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1654709631
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3164521559
Short name T802
Test name
Test status
Simulation time 11737983 ps
CPU time 0.6 seconds
Started Mar 03 03:06:52 PM PST 24
Finished Mar 03 03:06:52 PM PST 24
Peak memory 194136 kb
Host smart-51f78267-e24d-4a32-84b0-be8d034ed12c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164521559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3164521559
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.2292801226
Short name T804
Test name
Test status
Simulation time 34313777 ps
CPU time 0.65 seconds
Started Mar 03 03:06:53 PM PST 24
Finished Mar 03 03:06:54 PM PST 24
Peak memory 195204 kb
Host smart-3327ecd4-fd62-4d94-85f7-20393df6a077
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292801226 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.2292801226
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1486999533
Short name T749
Test name
Test status
Simulation time 23960426 ps
CPU time 1.32 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:52 PM PST 24
Peak memory 198556 kb
Host smart-81bd8356-15b6-4c51-a44d-f402b51c86ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486999533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1486999533
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2887079745
Short name T831
Test name
Test status
Simulation time 125824820 ps
CPU time 0.84 seconds
Started Mar 03 03:06:57 PM PST 24
Finished Mar 03 03:06:58 PM PST 24
Peak memory 196080 kb
Host smart-91787ae6-9cb0-4d21-870b-38ecb0124da4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887079745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2887079745
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1315006571
Short name T81
Test name
Test status
Simulation time 265699299 ps
CPU time 1.56 seconds
Started Mar 03 03:06:55 PM PST 24
Finished Mar 03 03:06:57 PM PST 24
Peak memory 197564 kb
Host smart-f3d66c17-a463-45b0-ad2f-72faef55a252
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315006571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1315006571
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.631832808
Short name T735
Test name
Test status
Simulation time 51639822 ps
CPU time 0.64 seconds
Started Mar 03 03:06:48 PM PST 24
Finished Mar 03 03:06:49 PM PST 24
Peak memory 195968 kb
Host smart-991b809c-a177-4aba-b7a4-cbd2d3050d18
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631832808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.631832808
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.423606657
Short name T826
Test name
Test status
Simulation time 116559321 ps
CPU time 1.51 seconds
Started Mar 03 03:06:50 PM PST 24
Finished Mar 03 03:06:51 PM PST 24
Peak memory 198668 kb
Host smart-43d04238-fe19-461b-913d-b5d5d6bb2591
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423606657 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.423606657
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1221985142
Short name T787
Test name
Test status
Simulation time 31496108 ps
CPU time 0.6 seconds
Started Mar 03 03:06:50 PM PST 24
Finished Mar 03 03:06:51 PM PST 24
Peak memory 195748 kb
Host smart-db553b13-cc59-49cf-9c09-a86d33ddd663
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221985142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1221985142
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.790487268
Short name T776
Test name
Test status
Simulation time 12182235 ps
CPU time 0.59 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:52 PM PST 24
Peak memory 194172 kb
Host smart-908ec71c-94b8-4695-9c81-15e841404cc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790487268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.790487268
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.4209033956
Short name T87
Test name
Test status
Simulation time 20711583 ps
CPU time 0.7 seconds
Started Mar 03 03:06:53 PM PST 24
Finished Mar 03 03:06:53 PM PST 24
Peak memory 196252 kb
Host smart-a7b8079f-c9c0-4218-beab-f3f4ceefc44b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209033956 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.4209033956
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.996888444
Short name T723
Test name
Test status
Simulation time 59538474 ps
CPU time 2.88 seconds
Started Mar 03 03:06:52 PM PST 24
Finished Mar 03 03:06:56 PM PST 24
Peak memory 198516 kb
Host smart-0ff346d0-135b-44dc-8c82-3612d44ea7f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996888444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.996888444
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.432363706
Short name T93
Test name
Test status
Simulation time 78613809 ps
CPU time 1.14 seconds
Started Mar 03 03:06:52 PM PST 24
Finished Mar 03 03:06:53 PM PST 24
Peak memory 198540 kb
Host smart-dfe24a02-8a07-4206-b397-5d3cf87b34c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432363706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.432363706
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1653023615
Short name T762
Test name
Test status
Simulation time 19434558 ps
CPU time 0.84 seconds
Started Mar 03 03:07:03 PM PST 24
Finished Mar 03 03:07:04 PM PST 24
Peak memory 198308 kb
Host smart-88a360ff-2968-4237-a83a-a09f81ec65a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653023615 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1653023615
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2974989314
Short name T70
Test name
Test status
Simulation time 45807681 ps
CPU time 0.58 seconds
Started Mar 03 03:07:06 PM PST 24
Finished Mar 03 03:07:07 PM PST 24
Peak memory 195760 kb
Host smart-3e5dfa2e-4077-45ab-9ae9-1cdbb367e803
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974989314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2974989314
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2676803580
Short name T731
Test name
Test status
Simulation time 15649494 ps
CPU time 0.63 seconds
Started Mar 03 03:07:00 PM PST 24
Finished Mar 03 03:07:00 PM PST 24
Peak memory 194192 kb
Host smart-eb186faa-1707-45ff-93ca-f18cc275bbcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676803580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2676803580
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1916370463
Short name T798
Test name
Test status
Simulation time 29377250 ps
CPU time 0.8 seconds
Started Mar 03 03:06:58 PM PST 24
Finished Mar 03 03:06:59 PM PST 24
Peak memory 197220 kb
Host smart-550652ad-958e-4359-907f-26bef8c48b5c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916370463 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1916370463
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3184915585
Short name T810
Test name
Test status
Simulation time 93393334 ps
CPU time 2.58 seconds
Started Mar 03 03:07:00 PM PST 24
Finished Mar 03 03:07:03 PM PST 24
Peak memory 198560 kb
Host smart-c76f7c7d-3f55-484c-aa5c-f81f7ee33942
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184915585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3184915585
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2328255364
Short name T813
Test name
Test status
Simulation time 166674717 ps
CPU time 1.1 seconds
Started Mar 03 03:06:57 PM PST 24
Finished Mar 03 03:06:58 PM PST 24
Peak memory 198472 kb
Host smart-d384df53-2380-47a3-bbdd-9e925d7592fe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328255364 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2328255364
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.143501155
Short name T829
Test name
Test status
Simulation time 17220857 ps
CPU time 0.63 seconds
Started Mar 03 03:06:58 PM PST 24
Finished Mar 03 03:06:59 PM PST 24
Peak memory 195072 kb
Host smart-c2276da5-7f9b-462e-9664-be2856cb95dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143501155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.143501155
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3059388528
Short name T770
Test name
Test status
Simulation time 14053812 ps
CPU time 0.61 seconds
Started Mar 03 03:07:01 PM PST 24
Finished Mar 03 03:07:01 PM PST 24
Peak memory 194252 kb
Host smart-5637447d-5e81-4b60-b47b-1c0b52095c90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059388528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3059388528
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3510664002
Short name T89
Test name
Test status
Simulation time 424402113 ps
CPU time 0.91 seconds
Started Mar 03 03:07:05 PM PST 24
Finished Mar 03 03:07:07 PM PST 24
Peak memory 197052 kb
Host smart-67f8bc50-74db-44f6-a6de-ae119c7e923e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510664002 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3510664002
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3762214082
Short name T763
Test name
Test status
Simulation time 94357203 ps
CPU time 1.86 seconds
Started Mar 03 03:07:03 PM PST 24
Finished Mar 03 03:07:05 PM PST 24
Peak memory 198476 kb
Host smart-d27f45b8-ed3a-4c4f-9544-07c324416280
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762214082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3762214082
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.723781683
Short name T823
Test name
Test status
Simulation time 83205019 ps
CPU time 0.91 seconds
Started Mar 03 03:07:01 PM PST 24
Finished Mar 03 03:07:02 PM PST 24
Peak memory 198336 kb
Host smart-11ed1b83-bcc3-44ab-833d-05482edcf5cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723781683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.723781683
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.737761351
Short name T835
Test name
Test status
Simulation time 37424379 ps
CPU time 0.93 seconds
Started Mar 03 03:07:06 PM PST 24
Finished Mar 03 03:07:07 PM PST 24
Peak memory 198472 kb
Host smart-64ea4c8e-3a0d-4746-9c2a-9f06e69c5e09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737761351 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.737761351
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2551908354
Short name T82
Test name
Test status
Simulation time 34734237 ps
CPU time 0.64 seconds
Started Mar 03 03:07:03 PM PST 24
Finished Mar 03 03:07:04 PM PST 24
Peak memory 194816 kb
Host smart-a8384049-9b0a-413b-b0ec-1440582f3897
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551908354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2551908354
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3816486481
Short name T827
Test name
Test status
Simulation time 23981593 ps
CPU time 0.59 seconds
Started Mar 03 03:07:07 PM PST 24
Finished Mar 03 03:07:08 PM PST 24
Peak memory 194816 kb
Host smart-b866df74-ade4-420b-8b3c-d8593ce9bcf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816486481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3816486481
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1784420221
Short name T752
Test name
Test status
Simulation time 42226446 ps
CPU time 2.16 seconds
Started Mar 03 03:07:06 PM PST 24
Finished Mar 03 03:07:08 PM PST 24
Peak memory 198468 kb
Host smart-597a3601-c39d-483b-bced-b33bf2a282ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784420221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1784420221
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2414322250
Short name T37
Test name
Test status
Simulation time 118581678 ps
CPU time 1.48 seconds
Started Mar 03 03:06:58 PM PST 24
Finished Mar 03 03:07:00 PM PST 24
Peak memory 198588 kb
Host smart-121c1482-f27b-4739-9e28-d8d80d66a7a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414322250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2414322250
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3601006657
Short name T790
Test name
Test status
Simulation time 17824528 ps
CPU time 0.7 seconds
Started Mar 03 03:07:03 PM PST 24
Finished Mar 03 03:07:04 PM PST 24
Peak memory 197676 kb
Host smart-81b3cc90-1df8-40e1-82c4-692ea3cd3cbe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601006657 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3601006657
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2507737623
Short name T840
Test name
Test status
Simulation time 44721712 ps
CPU time 0.63 seconds
Started Mar 03 03:07:04 PM PST 24
Finished Mar 03 03:07:06 PM PST 24
Peak memory 195224 kb
Host smart-214854cd-95c0-4c0f-a152-8ae04db9b7b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507737623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2507737623
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2562845030
Short name T792
Test name
Test status
Simulation time 13169279 ps
CPU time 0.62 seconds
Started Mar 03 03:07:05 PM PST 24
Finished Mar 03 03:07:06 PM PST 24
Peak memory 194820 kb
Host smart-c11d5a92-b8f5-4e6a-b9d0-2096d47a93ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562845030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2562845030
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3314122527
Short name T806
Test name
Test status
Simulation time 19594461 ps
CPU time 0.65 seconds
Started Mar 03 03:07:03 PM PST 24
Finished Mar 03 03:07:04 PM PST 24
Peak memory 195208 kb
Host smart-3c150e39-f5ac-412c-b8c1-4d27ebc7f77d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314122527 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3314122527
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3746066792
Short name T812
Test name
Test status
Simulation time 434847390 ps
CPU time 1.9 seconds
Started Mar 03 03:07:04 PM PST 24
Finished Mar 03 03:07:06 PM PST 24
Peak memory 198524 kb
Host smart-a1a336ea-8e75-4cf7-b684-4aa98d77a7e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746066792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3746066792
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.4019738897
Short name T30
Test name
Test status
Simulation time 347342800 ps
CPU time 0.88 seconds
Started Mar 03 03:07:02 PM PST 24
Finished Mar 03 03:07:03 PM PST 24
Peak memory 197792 kb
Host smart-28bd8a90-2889-4a39-bf58-44ac7e92e17b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019738897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.4019738897
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2103321294
Short name T736
Test name
Test status
Simulation time 62408050 ps
CPU time 0.99 seconds
Started Mar 03 03:07:09 PM PST 24
Finished Mar 03 03:07:10 PM PST 24
Peak memory 198476 kb
Host smart-ce620244-f1b1-45ab-9313-5fa7cdc94edd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103321294 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2103321294
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1678553725
Short name T80
Test name
Test status
Simulation time 16333397 ps
CPU time 0.67 seconds
Started Mar 03 03:07:06 PM PST 24
Finished Mar 03 03:07:07 PM PST 24
Peak memory 195168 kb
Host smart-0f34e8c3-088b-4ebb-94c2-17dfa31c7d15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678553725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1678553725
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1728119255
Short name T738
Test name
Test status
Simulation time 38619608 ps
CPU time 0.64 seconds
Started Mar 03 03:07:04 PM PST 24
Finished Mar 03 03:07:06 PM PST 24
Peak memory 194284 kb
Host smart-8ad27c14-81bd-482f-963c-8d8d713b2f79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728119255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1728119255
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1894004395
Short name T67
Test name
Test status
Simulation time 32559064 ps
CPU time 0.85 seconds
Started Mar 03 03:07:06 PM PST 24
Finished Mar 03 03:07:07 PM PST 24
Peak memory 197528 kb
Host smart-cf1d9b63-1b56-4961-aee4-7fe41c2dd4a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894004395 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1894004395
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.767594559
Short name T821
Test name
Test status
Simulation time 86026307 ps
CPU time 1.35 seconds
Started Mar 03 03:07:06 PM PST 24
Finished Mar 03 03:07:08 PM PST 24
Peak memory 198568 kb
Host smart-1c877326-7714-4735-b324-0aa97243b8b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767594559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.767594559
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.715506655
Short name T833
Test name
Test status
Simulation time 116662592 ps
CPU time 1.45 seconds
Started Mar 03 03:07:04 PM PST 24
Finished Mar 03 03:07:07 PM PST 24
Peak memory 198620 kb
Host smart-a1117236-65ba-4c9d-a884-d66c747f408c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715506655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.715506655
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.589381903
Short name T791
Test name
Test status
Simulation time 319265300 ps
CPU time 0.76 seconds
Started Mar 03 03:07:06 PM PST 24
Finished Mar 03 03:07:07 PM PST 24
Peak memory 198096 kb
Host smart-e0535575-1ad3-4530-9e3b-f0ceae0eda00
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589381903 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.589381903
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1942349436
Short name T68
Test name
Test status
Simulation time 21838227 ps
CPU time 0.64 seconds
Started Mar 03 03:07:07 PM PST 24
Finished Mar 03 03:07:08 PM PST 24
Peak memory 195276 kb
Host smart-70e8fe90-1bb0-4c11-b0d7-c3df00045951
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942349436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1942349436
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.4153268536
Short name T801
Test name
Test status
Simulation time 12285717 ps
CPU time 0.66 seconds
Started Mar 03 03:07:09 PM PST 24
Finished Mar 03 03:07:10 PM PST 24
Peak memory 194156 kb
Host smart-3ef66a1a-bb76-4e40-9418-d33962acfbc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153268536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.4153268536
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2849652893
Short name T825
Test name
Test status
Simulation time 21978022 ps
CPU time 0.65 seconds
Started Mar 03 03:07:03 PM PST 24
Finished Mar 03 03:07:04 PM PST 24
Peak memory 195256 kb
Host smart-a4d28443-20d2-4584-bdcd-d0d48836e286
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849652893 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2849652893
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.570739300
Short name T722
Test name
Test status
Simulation time 24665558 ps
CPU time 1.13 seconds
Started Mar 03 03:07:07 PM PST 24
Finished Mar 03 03:07:08 PM PST 24
Peak memory 198552 kb
Host smart-9f9c9c03-2d86-4232-b7f5-8e3f50fbf4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570739300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.570739300
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.300283702
Short name T785
Test name
Test status
Simulation time 460120479 ps
CPU time 0.91 seconds
Started Mar 03 03:07:04 PM PST 24
Finished Mar 03 03:07:07 PM PST 24
Peak memory 198368 kb
Host smart-6419b2b6-8926-45dd-a008-daf203951f07
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300283702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.300283702
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1447972139
Short name T746
Test name
Test status
Simulation time 33132205 ps
CPU time 1 seconds
Started Mar 03 03:07:06 PM PST 24
Finished Mar 03 03:07:07 PM PST 24
Peak memory 198396 kb
Host smart-937be423-d03e-4f00-9ed7-bc4139e1282d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447972139 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1447972139
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3714053481
Short name T72
Test name
Test status
Simulation time 15271965 ps
CPU time 0.62 seconds
Started Mar 03 03:07:06 PM PST 24
Finished Mar 03 03:07:07 PM PST 24
Peak memory 195864 kb
Host smart-a0170d92-640c-45ff-a0a7-a6813d3c0a93
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714053481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3714053481
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3940253082
Short name T816
Test name
Test status
Simulation time 12812355 ps
CPU time 0.62 seconds
Started Mar 03 03:07:08 PM PST 24
Finished Mar 03 03:07:08 PM PST 24
Peak memory 194232 kb
Host smart-1b5942ab-a39e-4000-8f4e-fe28e47ca272
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940253082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3940253082
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.683135943
Short name T815
Test name
Test status
Simulation time 24712778 ps
CPU time 0.68 seconds
Started Mar 03 03:07:06 PM PST 24
Finished Mar 03 03:07:07 PM PST 24
Peak memory 194920 kb
Host smart-a49647ce-806c-471b-8669-4ee899410744
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683135943 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.683135943
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3048390777
Short name T760
Test name
Test status
Simulation time 138082402 ps
CPU time 1.34 seconds
Started Mar 03 03:07:08 PM PST 24
Finished Mar 03 03:07:10 PM PST 24
Peak memory 198536 kb
Host smart-667ce38a-1303-40d5-8d5d-4e83967291c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048390777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3048390777
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2060228815
Short name T36
Test name
Test status
Simulation time 354868095 ps
CPU time 1.18 seconds
Started Mar 03 03:07:02 PM PST 24
Finished Mar 03 03:07:03 PM PST 24
Peak memory 198540 kb
Host smart-0f6b9609-341c-4bb5-b6d1-ada17c9b7633
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060228815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2060228815
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1425553558
Short name T824
Test name
Test status
Simulation time 33310224 ps
CPU time 0.72 seconds
Started Mar 03 03:07:07 PM PST 24
Finished Mar 03 03:07:08 PM PST 24
Peak memory 198472 kb
Host smart-53e10962-f9ca-42ab-bccb-31fca44cb2ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425553558 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1425553558
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1024618180
Short name T62
Test name
Test status
Simulation time 20123132 ps
CPU time 0.68 seconds
Started Mar 03 03:07:09 PM PST 24
Finished Mar 03 03:07:10 PM PST 24
Peak memory 195244 kb
Host smart-cc5aa43d-2cec-443b-a514-e3e21a651881
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024618180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.1024618180
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2866475677
Short name T753
Test name
Test status
Simulation time 14201477 ps
CPU time 0.6 seconds
Started Mar 03 03:07:07 PM PST 24
Finished Mar 03 03:07:07 PM PST 24
Peak memory 194156 kb
Host smart-be8edc05-214c-4d0c-b550-2e617ec91f82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866475677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2866475677
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1595212838
Short name T85
Test name
Test status
Simulation time 308481426 ps
CPU time 0.63 seconds
Started Mar 03 03:07:05 PM PST 24
Finished Mar 03 03:07:06 PM PST 24
Peak memory 195320 kb
Host smart-1605e879-18e0-4191-aac2-7810037bdedf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595212838 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1595212838
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2688475980
Short name T800
Test name
Test status
Simulation time 285633918 ps
CPU time 1.3 seconds
Started Mar 03 03:07:02 PM PST 24
Finished Mar 03 03:07:03 PM PST 24
Peak memory 198568 kb
Host smart-162dda62-b4e5-40dd-b071-e1fe409936e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688475980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2688475980
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3090104615
Short name T838
Test name
Test status
Simulation time 101906606 ps
CPU time 1.39 seconds
Started Mar 03 03:07:11 PM PST 24
Finished Mar 03 03:07:12 PM PST 24
Peak memory 198436 kb
Host smart-59ccf790-5f4e-4008-9425-8fd8c5579ea9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090104615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3090104615
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1820537387
Short name T793
Test name
Test status
Simulation time 92066071 ps
CPU time 1.09 seconds
Started Mar 03 03:07:04 PM PST 24
Finished Mar 03 03:07:07 PM PST 24
Peak memory 198452 kb
Host smart-b03d860d-1c7e-4715-80f4-461c68884e72
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820537387 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1820537387
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3223704509
Short name T84
Test name
Test status
Simulation time 11388825 ps
CPU time 0.61 seconds
Started Mar 03 03:07:07 PM PST 24
Finished Mar 03 03:07:08 PM PST 24
Peak memory 195400 kb
Host smart-cab58409-861e-41fa-b50f-9088ddcda2b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223704509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3223704509
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2745533088
Short name T819
Test name
Test status
Simulation time 32786043 ps
CPU time 0.57 seconds
Started Mar 03 03:07:07 PM PST 24
Finished Mar 03 03:07:07 PM PST 24
Peak memory 194260 kb
Host smart-61de08b9-2107-4654-82b3-a7189b9c6506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745533088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2745533088
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1237122946
Short name T784
Test name
Test status
Simulation time 40509953 ps
CPU time 0.94 seconds
Started Mar 03 03:07:09 PM PST 24
Finished Mar 03 03:07:10 PM PST 24
Peak memory 197668 kb
Host smart-90a55d10-9feb-4585-84cf-efc5ea835846
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237122946 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1237122946
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3975785770
Short name T834
Test name
Test status
Simulation time 974878141 ps
CPU time 1.71 seconds
Started Mar 03 03:07:05 PM PST 24
Finished Mar 03 03:07:08 PM PST 24
Peak memory 198568 kb
Host smart-eeed11c9-f4f0-4a1a-8892-f054b5df9b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975785770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3975785770
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2119296907
Short name T40
Test name
Test status
Simulation time 222945665 ps
CPU time 1.19 seconds
Started Mar 03 03:07:09 PM PST 24
Finished Mar 03 03:07:10 PM PST 24
Peak memory 198484 kb
Host smart-87abe90f-ef2d-48c5-8af7-29fd0b34abcf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119296907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2119296907
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3032202725
Short name T737
Test name
Test status
Simulation time 127859462 ps
CPU time 0.91 seconds
Started Mar 03 03:07:11 PM PST 24
Finished Mar 03 03:07:12 PM PST 24
Peak memory 198392 kb
Host smart-2dafd310-97ac-4af3-9d59-e82541976d44
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032202725 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3032202725
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.68822725
Short name T83
Test name
Test status
Simulation time 49831326 ps
CPU time 0.6 seconds
Started Mar 03 03:07:09 PM PST 24
Finished Mar 03 03:07:10 PM PST 24
Peak memory 195256 kb
Host smart-a2814683-dc83-489f-b5cc-197f8ea23530
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68822725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_
csr_rw.68822725
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.540532730
Short name T745
Test name
Test status
Simulation time 26474280 ps
CPU time 0.58 seconds
Started Mar 03 03:07:17 PM PST 24
Finished Mar 03 03:07:18 PM PST 24
Peak memory 194824 kb
Host smart-98fff021-2bd7-418d-8b30-797ac3e91927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540532730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.540532730
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1885601334
Short name T811
Test name
Test status
Simulation time 26063365 ps
CPU time 0.68 seconds
Started Mar 03 03:07:11 PM PST 24
Finished Mar 03 03:07:12 PM PST 24
Peak memory 195380 kb
Host smart-cd32d703-6aaa-4806-bc4c-86cf578a4123
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885601334 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1885601334
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.142259782
Short name T758
Test name
Test status
Simulation time 81026210 ps
CPU time 1.11 seconds
Started Mar 03 03:07:15 PM PST 24
Finished Mar 03 03:07:17 PM PST 24
Peak memory 198592 kb
Host smart-ed2fdf9b-deef-41d7-b2cd-693175a0efcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142259782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.142259782
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.145661597
Short name T43
Test name
Test status
Simulation time 529381591 ps
CPU time 1.51 seconds
Started Mar 03 03:07:17 PM PST 24
Finished Mar 03 03:07:19 PM PST 24
Peak memory 198584 kb
Host smart-53f2c2b9-9d5c-4006-a1ea-f631bf6b92e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145661597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.145661597
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1111508983
Short name T841
Test name
Test status
Simulation time 609473712 ps
CPU time 2.45 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:53 PM PST 24
Peak memory 197632 kb
Host smart-b524f2e4-b7f2-45d4-97c7-1e7ea13cf4eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111508983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1111508983
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1478201668
Short name T65
Test name
Test status
Simulation time 16921315 ps
CPU time 0.65 seconds
Started Mar 03 03:06:52 PM PST 24
Finished Mar 03 03:06:53 PM PST 24
Peak memory 196024 kb
Host smart-8bf19214-0e9a-4dda-92d4-9d56e795b008
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478201668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1478201668
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.695144752
Short name T743
Test name
Test status
Simulation time 27810716 ps
CPU time 0.85 seconds
Started Mar 03 03:06:54 PM PST 24
Finished Mar 03 03:06:55 PM PST 24
Peak memory 198428 kb
Host smart-fe59ffe1-3163-4d67-b02e-2a7602a24a0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695144752 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.695144752
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.851068637
Short name T73
Test name
Test status
Simulation time 13409414 ps
CPU time 0.61 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:52 PM PST 24
Peak memory 195372 kb
Host smart-58adf47e-3d2e-4a31-a18a-15d4d79ee21a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851068637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.851068637
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.5447819
Short name T769
Test name
Test status
Simulation time 83441181 ps
CPU time 0.65 seconds
Started Mar 03 03:06:52 PM PST 24
Finished Mar 03 03:06:53 PM PST 24
Peak memory 194316 kb
Host smart-eb216db4-46f4-4ad2-bdde-b9dbfa83cb12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5447819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.5447819
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.798404902
Short name T772
Test name
Test status
Simulation time 106266820 ps
CPU time 0.83 seconds
Started Mar 03 03:06:49 PM PST 24
Finished Mar 03 03:06:50 PM PST 24
Peak memory 196832 kb
Host smart-ffad236e-939d-4932-950d-e2440e131367
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798404902 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.798404902
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2218424546
Short name T748
Test name
Test status
Simulation time 316291083 ps
CPU time 1.39 seconds
Started Mar 03 03:06:57 PM PST 24
Finished Mar 03 03:06:58 PM PST 24
Peak memory 198568 kb
Host smart-99bf5109-3313-47f3-b419-b1b99f388b61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218424546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2218424546
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3390875839
Short name T807
Test name
Test status
Simulation time 370705763 ps
CPU time 1.36 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:52 PM PST 24
Peak memory 198616 kb
Host smart-7dba2137-de22-4110-89f7-41858ec7216d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390875839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3390875839
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3953090353
Short name T739
Test name
Test status
Simulation time 60282182 ps
CPU time 0.61 seconds
Started Mar 03 03:07:13 PM PST 24
Finished Mar 03 03:07:13 PM PST 24
Peak memory 194236 kb
Host smart-22f90ac7-04a4-47c4-8b19-4b36916b9a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953090353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3953090353
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2671599563
Short name T730
Test name
Test status
Simulation time 70609641 ps
CPU time 0.61 seconds
Started Mar 03 03:07:14 PM PST 24
Finished Mar 03 03:07:15 PM PST 24
Peak memory 194888 kb
Host smart-d6cad87e-ac3a-47ee-9f4f-95e5a31c7c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671599563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2671599563
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3506083039
Short name T818
Test name
Test status
Simulation time 46905832 ps
CPU time 0.59 seconds
Started Mar 03 03:07:12 PM PST 24
Finished Mar 03 03:07:13 PM PST 24
Peak memory 194184 kb
Host smart-b8946451-a60f-42eb-9309-e9607f8fb7b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506083039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3506083039
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1344812322
Short name T761
Test name
Test status
Simulation time 17367144 ps
CPU time 0.58 seconds
Started Mar 03 03:07:19 PM PST 24
Finished Mar 03 03:07:20 PM PST 24
Peak memory 194316 kb
Host smart-223d1ec9-775f-4c28-8387-a4b6d07384ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344812322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1344812322
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2726135316
Short name T740
Test name
Test status
Simulation time 53415937 ps
CPU time 0.56 seconds
Started Mar 03 03:07:11 PM PST 24
Finished Mar 03 03:07:11 PM PST 24
Peak memory 194168 kb
Host smart-edbb7e4c-296d-4b7d-8c7d-83249be384a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726135316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2726135316
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.384858686
Short name T814
Test name
Test status
Simulation time 11712620 ps
CPU time 0.6 seconds
Started Mar 03 03:07:13 PM PST 24
Finished Mar 03 03:07:14 PM PST 24
Peak memory 194836 kb
Host smart-9d852cb6-514e-4e0c-b0d7-20ca69839a25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384858686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.384858686
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2824345788
Short name T721
Test name
Test status
Simulation time 54980997 ps
CPU time 0.6 seconds
Started Mar 03 03:07:14 PM PST 24
Finished Mar 03 03:07:15 PM PST 24
Peak memory 194228 kb
Host smart-a00eb79f-eecc-4cda-b865-babcfcfb1a99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824345788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2824345788
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3785132729
Short name T747
Test name
Test status
Simulation time 17651726 ps
CPU time 0.6 seconds
Started Mar 03 03:07:16 PM PST 24
Finished Mar 03 03:07:17 PM PST 24
Peak memory 194228 kb
Host smart-8de80812-e2ec-4e47-92d5-95d700be6e26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785132729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3785132729
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2018601820
Short name T786
Test name
Test status
Simulation time 78550171 ps
CPU time 0.6 seconds
Started Mar 03 03:07:26 PM PST 24
Finished Mar 03 03:07:27 PM PST 24
Peak memory 194184 kb
Host smart-f7a4386a-b2f0-4d8a-9dcd-7f7f2ea3135b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018601820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2018601820
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2795175655
Short name T781
Test name
Test status
Simulation time 33122330 ps
CPU time 0.64 seconds
Started Mar 03 03:07:16 PM PST 24
Finished Mar 03 03:07:18 PM PST 24
Peak memory 194928 kb
Host smart-b4507547-61b2-4fad-8662-86829d212273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795175655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2795175655
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1786010026
Short name T76
Test name
Test status
Simulation time 63739982 ps
CPU time 0.84 seconds
Started Mar 03 03:06:52 PM PST 24
Finished Mar 03 03:06:53 PM PST 24
Peak memory 196416 kb
Host smart-3a685f5d-f64d-4169-908d-2586cc565732
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786010026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1786010026
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2256000111
Short name T779
Test name
Test status
Simulation time 241871775 ps
CPU time 2.12 seconds
Started Mar 03 03:06:52 PM PST 24
Finished Mar 03 03:06:54 PM PST 24
Peak memory 197792 kb
Host smart-2710b4e8-ffdd-4946-b78f-c6ceefbd7a18
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256000111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2256000111
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2804003676
Short name T74
Test name
Test status
Simulation time 58783301 ps
CPU time 0.64 seconds
Started Mar 03 03:06:53 PM PST 24
Finished Mar 03 03:06:54 PM PST 24
Peak memory 195404 kb
Host smart-e5825632-2105-4a7e-8f00-afc0c5f22c0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804003676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2804003676
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3371990660
Short name T732
Test name
Test status
Simulation time 45173225 ps
CPU time 0.99 seconds
Started Mar 03 03:06:48 PM PST 24
Finished Mar 03 03:06:49 PM PST 24
Peak memory 198440 kb
Host smart-5e0f71b0-9f96-4b55-8fac-6a81188608e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371990660 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3371990660
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3227596184
Short name T66
Test name
Test status
Simulation time 14333068 ps
CPU time 0.63 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:52 PM PST 24
Peak memory 195292 kb
Host smart-e7173c6f-1627-48a6-b161-363da8bef422
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227596184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3227596184
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2230218410
Short name T766
Test name
Test status
Simulation time 11413052 ps
CPU time 0.63 seconds
Started Mar 03 03:06:52 PM PST 24
Finished Mar 03 03:06:52 PM PST 24
Peak memory 194948 kb
Host smart-6356b290-9752-4e54-95ef-518652413335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230218410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2230218410
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3876565582
Short name T817
Test name
Test status
Simulation time 50237983 ps
CPU time 0.75 seconds
Started Mar 03 03:06:52 PM PST 24
Finished Mar 03 03:06:52 PM PST 24
Peak memory 196400 kb
Host smart-8e5c084a-c403-48ac-b531-45202e9a74b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876565582 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3876565582
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2552289159
Short name T822
Test name
Test status
Simulation time 151938899 ps
CPU time 1.63 seconds
Started Mar 03 03:06:50 PM PST 24
Finished Mar 03 03:06:52 PM PST 24
Peak memory 198572 kb
Host smart-17503449-a65b-4ec0-9eac-84438b1032ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552289159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2552289159
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2053444927
Short name T756
Test name
Test status
Simulation time 12792446 ps
CPU time 0.62 seconds
Started Mar 03 03:07:14 PM PST 24
Finished Mar 03 03:07:15 PM PST 24
Peak memory 194204 kb
Host smart-99566401-2b5e-4d56-9f75-b7eafac984b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053444927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2053444927
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1184913193
Short name T832
Test name
Test status
Simulation time 39422522 ps
CPU time 0.59 seconds
Started Mar 03 03:07:16 PM PST 24
Finished Mar 03 03:07:17 PM PST 24
Peak memory 194812 kb
Host smart-90cb2260-07fc-4d4d-874c-42347febff8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184913193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1184913193
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.4126976834
Short name T725
Test name
Test status
Simulation time 11996888 ps
CPU time 0.59 seconds
Started Mar 03 03:07:13 PM PST 24
Finished Mar 03 03:07:14 PM PST 24
Peak memory 194232 kb
Host smart-5c48b709-b8b3-4437-aa13-9d78e466e1ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126976834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.4126976834
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3509913500
Short name T734
Test name
Test status
Simulation time 52332371 ps
CPU time 0.62 seconds
Started Mar 03 03:07:17 PM PST 24
Finished Mar 03 03:07:18 PM PST 24
Peak memory 194872 kb
Host smart-66a12ad1-acb4-4dd1-81d5-0d13c43149bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509913500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3509913500
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.202072738
Short name T742
Test name
Test status
Simulation time 77183959 ps
CPU time 0.63 seconds
Started Mar 03 03:07:16 PM PST 24
Finished Mar 03 03:07:18 PM PST 24
Peak memory 194140 kb
Host smart-3a47a286-c2f3-4383-9fea-3979e1891673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202072738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.202072738
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1128941691
Short name T809
Test name
Test status
Simulation time 14988902 ps
CPU time 0.59 seconds
Started Mar 03 03:07:13 PM PST 24
Finished Mar 03 03:07:14 PM PST 24
Peak memory 194156 kb
Host smart-56932036-6b85-45fe-9178-0a9b8474d351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128941691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1128941691
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1482818814
Short name T755
Test name
Test status
Simulation time 12026671 ps
CPU time 0.61 seconds
Started Mar 03 03:07:19 PM PST 24
Finished Mar 03 03:07:20 PM PST 24
Peak memory 194236 kb
Host smart-7bffeb18-6143-4256-af73-82cfd8906add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482818814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1482818814
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2763914775
Short name T744
Test name
Test status
Simulation time 15316053 ps
CPU time 0.61 seconds
Started Mar 03 03:07:19 PM PST 24
Finished Mar 03 03:07:20 PM PST 24
Peak memory 194912 kb
Host smart-2b005385-dd6f-4b84-bf2e-0739fd363aeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763914775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2763914775
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1408537406
Short name T750
Test name
Test status
Simulation time 20339980 ps
CPU time 0.64 seconds
Started Mar 03 03:07:11 PM PST 24
Finished Mar 03 03:07:12 PM PST 24
Peak memory 194280 kb
Host smart-d48a6942-ee6c-4a5e-85d0-07ca20e72207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408537406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1408537406
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2896093725
Short name T820
Test name
Test status
Simulation time 42563096 ps
CPU time 0.58 seconds
Started Mar 03 03:07:14 PM PST 24
Finished Mar 03 03:07:15 PM PST 24
Peak memory 194856 kb
Host smart-d2f4b820-5433-4e79-836b-520f2c5de071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896093725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2896093725
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.379321995
Short name T77
Test name
Test status
Simulation time 144604454 ps
CPU time 0.91 seconds
Started Mar 03 03:06:54 PM PST 24
Finished Mar 03 03:06:55 PM PST 24
Peak memory 196528 kb
Host smart-4e666049-8e70-45bb-9ca9-348208a04251
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379321995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.379321995
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4000407046
Short name T839
Test name
Test status
Simulation time 178859051 ps
CPU time 2.44 seconds
Started Mar 03 03:06:55 PM PST 24
Finished Mar 03 03:06:57 PM PST 24
Peak memory 197612 kb
Host smart-b798f309-8728-4000-bce4-d84ebb004ad4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000407046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4000407046
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.483980705
Short name T794
Test name
Test status
Simulation time 59721623 ps
CPU time 0.64 seconds
Started Mar 03 03:06:57 PM PST 24
Finished Mar 03 03:06:57 PM PST 24
Peak memory 195264 kb
Host smart-3bf5939e-72c4-4d56-9a67-e33559ee9dc0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483980705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.483980705
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.285959407
Short name T728
Test name
Test status
Simulation time 160721015 ps
CPU time 0.94 seconds
Started Mar 03 03:06:52 PM PST 24
Finished Mar 03 03:06:53 PM PST 24
Peak memory 198452 kb
Host smart-e2c74717-cd23-47e8-8e0a-1bc78a84c050
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285959407 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.285959407
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1941987933
Short name T92
Test name
Test status
Simulation time 15857529 ps
CPU time 0.61 seconds
Started Mar 03 03:06:49 PM PST 24
Finished Mar 03 03:06:50 PM PST 24
Peak memory 195428 kb
Host smart-2fc052e8-b3d0-4cf8-8f27-b13b815513b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941987933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1941987933
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.327355848
Short name T830
Test name
Test status
Simulation time 33430045 ps
CPU time 0.64 seconds
Started Mar 03 03:06:53 PM PST 24
Finished Mar 03 03:06:53 PM PST 24
Peak memory 194172 kb
Host smart-30fe851c-3564-4f74-bbb8-3aac1c89115a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327355848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.327355848
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.319588197
Short name T88
Test name
Test status
Simulation time 219693210 ps
CPU time 0.78 seconds
Started Mar 03 03:06:49 PM PST 24
Finished Mar 03 03:06:50 PM PST 24
Peak memory 196552 kb
Host smart-1cba2db6-0302-4ded-8ced-fca83a2ff737
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319588197 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.319588197
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1125365201
Short name T782
Test name
Test status
Simulation time 135738058 ps
CPU time 2.41 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:54 PM PST 24
Peak memory 198576 kb
Host smart-71557833-ba1e-4cf4-a2c9-71f0925020b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125365201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1125365201
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2885020134
Short name T41
Test name
Test status
Simulation time 901345879 ps
CPU time 1.18 seconds
Started Mar 03 03:06:50 PM PST 24
Finished Mar 03 03:06:51 PM PST 24
Peak memory 198584 kb
Host smart-e79981a0-e1e0-41f5-9785-e92fe74c4f5a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885020134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2885020134
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1755471561
Short name T751
Test name
Test status
Simulation time 29030021 ps
CPU time 0.62 seconds
Started Mar 03 03:07:15 PM PST 24
Finished Mar 03 03:07:16 PM PST 24
Peak memory 194240 kb
Host smart-848b0fef-0c67-47b8-b47f-827412481434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755471561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1755471561
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.397075326
Short name T803
Test name
Test status
Simulation time 36522249 ps
CPU time 0.58 seconds
Started Mar 03 03:07:17 PM PST 24
Finished Mar 03 03:07:18 PM PST 24
Peak memory 194096 kb
Host smart-340142b8-97f4-4c63-93b2-aab932451855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397075326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.397075326
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3107207560
Short name T765
Test name
Test status
Simulation time 23477492 ps
CPU time 0.62 seconds
Started Mar 03 03:07:17 PM PST 24
Finished Mar 03 03:07:18 PM PST 24
Peak memory 194248 kb
Host smart-32d1a031-4b6f-42a9-a9a8-a5aac148ecf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107207560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3107207560
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1570224989
Short name T774
Test name
Test status
Simulation time 47255162 ps
CPU time 0.58 seconds
Started Mar 03 03:07:14 PM PST 24
Finished Mar 03 03:07:14 PM PST 24
Peak memory 194160 kb
Host smart-f752fe9c-9fb0-43a4-bd53-40248dfe0733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570224989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1570224989
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1501453517
Short name T796
Test name
Test status
Simulation time 66120777 ps
CPU time 0.63 seconds
Started Mar 03 03:07:16 PM PST 24
Finished Mar 03 03:07:17 PM PST 24
Peak memory 194220 kb
Host smart-d3106893-a935-4e5f-b61d-ee60139d0b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501453517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1501453517
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2227204019
Short name T771
Test name
Test status
Simulation time 47791925 ps
CPU time 0.62 seconds
Started Mar 03 03:07:12 PM PST 24
Finished Mar 03 03:07:12 PM PST 24
Peak memory 194848 kb
Host smart-778363c7-34fa-4926-b1ba-ad10459f94ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227204019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2227204019
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.554847545
Short name T724
Test name
Test status
Simulation time 45155992 ps
CPU time 0.58 seconds
Started Mar 03 03:07:11 PM PST 24
Finished Mar 03 03:07:12 PM PST 24
Peak memory 194252 kb
Host smart-382ce378-5ac5-4f0d-868d-997698041e29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554847545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.554847545
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2150743275
Short name T777
Test name
Test status
Simulation time 27260300 ps
CPU time 0.64 seconds
Started Mar 03 03:07:15 PM PST 24
Finished Mar 03 03:07:15 PM PST 24
Peak memory 194272 kb
Host smart-d44829a9-032f-46d1-996b-d3293f8a9a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150743275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2150743275
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1133928554
Short name T733
Test name
Test status
Simulation time 13231593 ps
CPU time 0.64 seconds
Started Mar 03 03:07:17 PM PST 24
Finished Mar 03 03:07:18 PM PST 24
Peak memory 194240 kb
Host smart-5a07ef3f-9afa-4b55-aa9e-0d0d87f9f435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133928554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1133928554
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2303078505
Short name T764
Test name
Test status
Simulation time 52489596 ps
CPU time 0.61 seconds
Started Mar 03 03:07:10 PM PST 24
Finished Mar 03 03:07:11 PM PST 24
Peak memory 194236 kb
Host smart-b7ee7027-d87f-4d9b-9d2d-c3663a6fbd62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303078505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2303078505
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.142598081
Short name T727
Test name
Test status
Simulation time 18781780 ps
CPU time 0.71 seconds
Started Mar 03 03:06:55 PM PST 24
Finished Mar 03 03:06:56 PM PST 24
Peak memory 198372 kb
Host smart-fee9b4d6-50a2-41ae-956e-d754670404a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142598081 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.142598081
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1241264454
Short name T768
Test name
Test status
Simulation time 34311636 ps
CPU time 0.62 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:52 PM PST 24
Peak memory 195188 kb
Host smart-339b6f76-6949-4cc3-b3a2-41fe0878adeb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241264454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1241264454
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3890720814
Short name T783
Test name
Test status
Simulation time 14877751 ps
CPU time 0.56 seconds
Started Mar 03 03:06:50 PM PST 24
Finished Mar 03 03:06:51 PM PST 24
Peak memory 194856 kb
Host smart-2732392a-4d9e-4c90-b554-ef2eb6d8394f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890720814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3890720814
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1708359850
Short name T86
Test name
Test status
Simulation time 19490106 ps
CPU time 0.69 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:51 PM PST 24
Peak memory 195404 kb
Host smart-ad6eb613-68df-4b21-820d-d6d3faae3de3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708359850 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1708359850
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1256632804
Short name T780
Test name
Test status
Simulation time 105631482 ps
CPU time 2.07 seconds
Started Mar 03 03:06:54 PM PST 24
Finished Mar 03 03:06:56 PM PST 24
Peak memory 198584 kb
Host smart-10e0753f-4dd8-4313-9167-9ce11993f149
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256632804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1256632804
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.634267175
Short name T773
Test name
Test status
Simulation time 232567430 ps
CPU time 0.86 seconds
Started Mar 03 03:06:57 PM PST 24
Finished Mar 03 03:06:58 PM PST 24
Peak memory 197776 kb
Host smart-c4612234-780b-4195-be4f-62027b8b267c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634267175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.634267175
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1899359102
Short name T788
Test name
Test status
Simulation time 71719183 ps
CPU time 1.52 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:53 PM PST 24
Peak memory 198660 kb
Host smart-4e155abb-ccfe-468e-9997-59e4bc53025c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899359102 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1899359102
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2579929448
Short name T741
Test name
Test status
Simulation time 37018833 ps
CPU time 0.62 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:51 PM PST 24
Peak memory 195164 kb
Host smart-89320e7c-c161-4315-b5b6-bfb172cbc712
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579929448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2579929448
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2418224130
Short name T797
Test name
Test status
Simulation time 14348845 ps
CPU time 0.63 seconds
Started Mar 03 03:06:52 PM PST 24
Finished Mar 03 03:06:53 PM PST 24
Peak memory 194956 kb
Host smart-3513e3e0-152b-47d5-bd99-659de28ce102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418224130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2418224130
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2268133151
Short name T63
Test name
Test status
Simulation time 58685243 ps
CPU time 0.77 seconds
Started Mar 03 03:06:54 PM PST 24
Finished Mar 03 03:06:55 PM PST 24
Peak memory 196932 kb
Host smart-41977630-79ca-4b04-92db-457f0f4ee873
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268133151 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2268133151
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2971519027
Short name T837
Test name
Test status
Simulation time 122636915 ps
CPU time 1.65 seconds
Started Mar 03 03:06:50 PM PST 24
Finished Mar 03 03:06:52 PM PST 24
Peak memory 198560 kb
Host smart-dd47564e-6905-42df-8fae-5bd16dc0076d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971519027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2971519027
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3928517636
Short name T759
Test name
Test status
Simulation time 45804905 ps
CPU time 0.91 seconds
Started Mar 03 03:06:52 PM PST 24
Finished Mar 03 03:06:53 PM PST 24
Peak memory 198324 kb
Host smart-75fe06e3-af5e-4e88-b08e-6983e9e9e74a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928517636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3928517636
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.28418032
Short name T799
Test name
Test status
Simulation time 24337422 ps
CPU time 1.16 seconds
Started Mar 03 03:07:00 PM PST 24
Finished Mar 03 03:07:01 PM PST 24
Peak memory 198584 kb
Host smart-d1325582-1a37-4118-8124-00273e6fe43d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28418032 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.28418032
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3916663361
Short name T757
Test name
Test status
Simulation time 14643507 ps
CPU time 0.58 seconds
Started Mar 03 03:06:54 PM PST 24
Finished Mar 03 03:06:55 PM PST 24
Peak memory 193776 kb
Host smart-cda19aa4-6b71-44a4-bd7f-3c94c87cd7e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916663361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3916663361
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2634303764
Short name T775
Test name
Test status
Simulation time 58064210 ps
CPU time 0.65 seconds
Started Mar 03 03:06:56 PM PST 24
Finished Mar 03 03:06:57 PM PST 24
Peak memory 194860 kb
Host smart-756971c4-7758-4d7c-b725-6e1ffe0a1527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634303764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2634303764
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3561589397
Short name T789
Test name
Test status
Simulation time 31276409 ps
CPU time 0.82 seconds
Started Mar 03 03:06:51 PM PST 24
Finished Mar 03 03:06:52 PM PST 24
Peak memory 196908 kb
Host smart-882d7fc5-a044-4300-888f-1619cab96802
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561589397 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3561589397
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2997311511
Short name T726
Test name
Test status
Simulation time 77578155 ps
CPU time 1.71 seconds
Started Mar 03 03:06:56 PM PST 24
Finished Mar 03 03:06:58 PM PST 24
Peak memory 198564 kb
Host smart-a9dcb4dd-84ad-47b0-bfd5-6d60986889a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997311511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2997311511
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.118716444
Short name T38
Test name
Test status
Simulation time 181346294 ps
CPU time 1.16 seconds
Started Mar 03 03:06:58 PM PST 24
Finished Mar 03 03:07:00 PM PST 24
Peak memory 198540 kb
Host smart-02c40123-b08f-405e-9795-fe67c8712105
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118716444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.118716444
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2414878232
Short name T729
Test name
Test status
Simulation time 71654867 ps
CPU time 0.72 seconds
Started Mar 03 03:07:00 PM PST 24
Finished Mar 03 03:07:01 PM PST 24
Peak memory 197920 kb
Host smart-6fdd9a65-589f-4cec-8aed-070e4418e4c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414878232 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2414878232
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.4135068848
Short name T75
Test name
Test status
Simulation time 41769890 ps
CPU time 0.56 seconds
Started Mar 03 03:06:54 PM PST 24
Finished Mar 03 03:06:55 PM PST 24
Peak memory 195068 kb
Host smart-222739b2-08e3-4693-a97d-694744649668
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135068848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.4135068848
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2411914029
Short name T828
Test name
Test status
Simulation time 18062011 ps
CPU time 0.61 seconds
Started Mar 03 03:06:56 PM PST 24
Finished Mar 03 03:06:57 PM PST 24
Peak memory 194236 kb
Host smart-f441a19b-bd31-4405-aa89-7277c9dd303b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411914029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2411914029
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3651913377
Short name T90
Test name
Test status
Simulation time 58742993 ps
CPU time 0.76 seconds
Started Mar 03 03:06:57 PM PST 24
Finished Mar 03 03:06:58 PM PST 24
Peak memory 195588 kb
Host smart-04b32e47-1f7f-4765-b8e4-2920806509a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651913377 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3651913377
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.731049678
Short name T778
Test name
Test status
Simulation time 85551945 ps
CPU time 1.36 seconds
Started Mar 03 03:07:03 PM PST 24
Finished Mar 03 03:07:05 PM PST 24
Peak memory 198488 kb
Host smart-1ec66699-492a-48ad-868f-5067fc42769e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731049678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.731049678
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3418777024
Short name T42
Test name
Test status
Simulation time 1510581980 ps
CPU time 1.86 seconds
Started Mar 03 03:07:00 PM PST 24
Finished Mar 03 03:07:02 PM PST 24
Peak memory 198608 kb
Host smart-6cc1f4f1-c770-4938-b6c9-734fd98c0ed2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418777024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3418777024
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3438244824
Short name T767
Test name
Test status
Simulation time 115759478 ps
CPU time 0.87 seconds
Started Mar 03 03:07:01 PM PST 24
Finished Mar 03 03:07:02 PM PST 24
Peak memory 198424 kb
Host smart-f1bd37e1-3e55-4039-92c6-6132af6b4407
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438244824 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3438244824
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2136597673
Short name T79
Test name
Test status
Simulation time 14282786 ps
CPU time 0.62 seconds
Started Mar 03 03:07:00 PM PST 24
Finished Mar 03 03:07:01 PM PST 24
Peak memory 195380 kb
Host smart-1536e2d6-d11a-4299-ae92-bf7cded75b3b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136597673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2136597673
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3740885879
Short name T805
Test name
Test status
Simulation time 14977855 ps
CPU time 0.62 seconds
Started Mar 03 03:06:57 PM PST 24
Finished Mar 03 03:06:58 PM PST 24
Peak memory 194856 kb
Host smart-0188a7da-0e28-4d03-9f87-6551bc8aca79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740885879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3740885879
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.4232343020
Short name T69
Test name
Test status
Simulation time 20175855 ps
CPU time 0.9 seconds
Started Mar 03 03:07:01 PM PST 24
Finished Mar 03 03:07:02 PM PST 24
Peak memory 197728 kb
Host smart-c821d22e-bd93-485b-8b9b-5266c65e0032
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232343020 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.4232343020
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1839299710
Short name T836
Test name
Test status
Simulation time 166216270 ps
CPU time 1.24 seconds
Started Mar 03 03:07:00 PM PST 24
Finished Mar 03 03:07:01 PM PST 24
Peak memory 198552 kb
Host smart-90e09b7f-bdd4-4826-ad27-835cf9a1fd7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839299710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1839299710
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3010417731
Short name T29
Test name
Test status
Simulation time 83208428 ps
CPU time 1.23 seconds
Started Mar 03 03:07:03 PM PST 24
Finished Mar 03 03:07:05 PM PST 24
Peak memory 198360 kb
Host smart-b4efd9a6-2573-4c89-8ff4-d0a3d9d3a71a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010417731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3010417731
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.295542521
Short name T338
Test name
Test status
Simulation time 32973745 ps
CPU time 0.79 seconds
Started Mar 03 12:38:52 PM PST 24
Finished Mar 03 12:38:54 PM PST 24
Peak memory 195932 kb
Host smart-77f0d4c5-ec80-4831-ba04-643e26c24e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295542521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.295542521
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3763454089
Short name T375
Test name
Test status
Simulation time 398386794 ps
CPU time 14.2 seconds
Started Mar 03 12:38:51 PM PST 24
Finished Mar 03 12:39:05 PM PST 24
Peak memory 196668 kb
Host smart-b36db83e-8ea3-47a0-bd4e-7dc90d1a3265
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763454089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3763454089
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2388205416
Short name T719
Test name
Test status
Simulation time 55394738 ps
CPU time 0.87 seconds
Started Mar 03 12:38:55 PM PST 24
Finished Mar 03 12:38:56 PM PST 24
Peak memory 195984 kb
Host smart-014ea13e-f24f-4d71-a584-48cda1abf4bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388205416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2388205416
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1090027481
Short name T257
Test name
Test status
Simulation time 56734432 ps
CPU time 1.26 seconds
Started Mar 03 12:38:52 PM PST 24
Finished Mar 03 12:38:54 PM PST 24
Peak memory 196936 kb
Host smart-b911c9a5-8363-4b21-bc61-e3b20d21c594
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090027481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1090027481
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3514346047
Short name T270
Test name
Test status
Simulation time 261162490 ps
CPU time 2.82 seconds
Started Mar 03 12:38:52 PM PST 24
Finished Mar 03 12:38:55 PM PST 24
Peak memory 198136 kb
Host smart-b8cecbdc-2da1-4115-a2c2-10d6de9d8a76
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514346047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3514346047
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2089725681
Short name T267
Test name
Test status
Simulation time 103421839 ps
CPU time 2.1 seconds
Started Mar 03 12:38:53 PM PST 24
Finished Mar 03 12:38:55 PM PST 24
Peak memory 196864 kb
Host smart-0690370a-5635-4d5c-af62-f4afc3d8a6bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089725681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2089725681
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3480610571
Short name T471
Test name
Test status
Simulation time 262813276 ps
CPU time 0.86 seconds
Started Mar 03 12:38:52 PM PST 24
Finished Mar 03 12:38:53 PM PST 24
Peak memory 196556 kb
Host smart-22829d15-f03b-470e-9b52-1a8ef65484ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480610571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3480610571
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1722518924
Short name T272
Test name
Test status
Simulation time 68906900 ps
CPU time 0.75 seconds
Started Mar 03 12:38:55 PM PST 24
Finished Mar 03 12:38:56 PM PST 24
Peak memory 195300 kb
Host smart-2e2ae86e-47eb-4618-afad-3f080afa9afd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722518924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1722518924
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.845721377
Short name T212
Test name
Test status
Simulation time 115259525 ps
CPU time 5.37 seconds
Started Mar 03 12:38:54 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 198028 kb
Host smart-9fb82399-96ce-4113-afc4-441fb22630b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845721377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.845721377
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3402555390
Short name T45
Test name
Test status
Simulation time 56709920 ps
CPU time 0.86 seconds
Started Mar 03 12:38:59 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 213648 kb
Host smart-1c05b985-24fe-483c-a90b-91c9b3e3ef80
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402555390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3402555390
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.969157700
Short name T415
Test name
Test status
Simulation time 109723450 ps
CPU time 1.49 seconds
Started Mar 03 12:38:53 PM PST 24
Finished Mar 03 12:38:55 PM PST 24
Peak memory 198068 kb
Host smart-d3023a23-61d5-4657-a0d0-1e418e75bf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969157700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.969157700
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3678629757
Short name T209
Test name
Test status
Simulation time 51302423 ps
CPU time 0.97 seconds
Started Mar 03 12:38:55 PM PST 24
Finished Mar 03 12:38:56 PM PST 24
Peak memory 197188 kb
Host smart-a84977d8-74ee-423c-a9b7-3302768b524b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678629757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3678629757
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1626586495
Short name T6
Test name
Test status
Simulation time 105434167378 ps
CPU time 128.86 seconds
Started Mar 03 12:39:03 PM PST 24
Finished Mar 03 12:41:13 PM PST 24
Peak memory 198200 kb
Host smart-fd029f56-11ae-4457-8879-9a89a7fdfa4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626586495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1626586495
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.242206145
Short name T277
Test name
Test status
Simulation time 14950219 ps
CPU time 0.58 seconds
Started Mar 03 12:38:59 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 194104 kb
Host smart-e4c86afb-c887-4bab-a179-c799f7d8df77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242206145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.242206145
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.857297035
Short name T305
Test name
Test status
Simulation time 43904847 ps
CPU time 0.87 seconds
Started Mar 03 12:39:01 PM PST 24
Finished Mar 03 12:39:03 PM PST 24
Peak memory 196348 kb
Host smart-88196d86-fbe8-4784-b159-690990426f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857297035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.857297035
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3695957737
Short name T384
Test name
Test status
Simulation time 447290682 ps
CPU time 6.74 seconds
Started Mar 03 12:38:58 PM PST 24
Finished Mar 03 12:39:05 PM PST 24
Peak memory 197016 kb
Host smart-e349bdb1-0c2d-48a6-acec-16eeb34441c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695957737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3695957737
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1913563720
Short name T51
Test name
Test status
Simulation time 275029997 ps
CPU time 0.92 seconds
Started Mar 03 12:38:57 PM PST 24
Finished Mar 03 12:38:58 PM PST 24
Peak memory 196948 kb
Host smart-f3dab525-0d08-447c-9641-e1146ac76c27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913563720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1913563720
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1542541747
Short name T586
Test name
Test status
Simulation time 506746270 ps
CPU time 1.09 seconds
Started Mar 03 12:38:59 PM PST 24
Finished Mar 03 12:39:01 PM PST 24
Peak memory 196812 kb
Host smart-ae983fc6-07c7-4446-91ba-bbc402b21f25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542541747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1542541747
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3464120264
Short name T468
Test name
Test status
Simulation time 36465793 ps
CPU time 1.11 seconds
Started Mar 03 12:38:59 PM PST 24
Finished Mar 03 12:39:01 PM PST 24
Peak memory 197616 kb
Host smart-56685969-32ef-44c4-90f9-79f8d42e3b20
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464120264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3464120264
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2339887906
Short name T379
Test name
Test status
Simulation time 215226848 ps
CPU time 2.57 seconds
Started Mar 03 12:39:00 PM PST 24
Finished Mar 03 12:39:02 PM PST 24
Peak memory 198120 kb
Host smart-cec8f3cc-5627-4210-8523-aa370c22cd13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339887906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2339887906
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.537777014
Short name T635
Test name
Test status
Simulation time 23093203 ps
CPU time 0.82 seconds
Started Mar 03 12:39:00 PM PST 24
Finished Mar 03 12:39:01 PM PST 24
Peak memory 196600 kb
Host smart-20a23972-92cf-4ea6-b8d5-cce550b32207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537777014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.537777014
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2483804193
Short name T310
Test name
Test status
Simulation time 102642140 ps
CPU time 0.75 seconds
Started Mar 03 12:38:57 PM PST 24
Finished Mar 03 12:38:58 PM PST 24
Peak memory 195280 kb
Host smart-f964f2cd-e444-4973-9028-c71d9a06d002
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483804193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2483804193
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.615668919
Short name T655
Test name
Test status
Simulation time 546427741 ps
CPU time 6.6 seconds
Started Mar 03 12:38:57 PM PST 24
Finished Mar 03 12:39:05 PM PST 24
Peak memory 198060 kb
Host smart-047a04cc-5f13-4908-9a3d-2205be146868
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615668919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.615668919
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3369144103
Short name T33
Test name
Test status
Simulation time 214638231 ps
CPU time 0.91 seconds
Started Mar 03 12:39:07 PM PST 24
Finished Mar 03 12:39:08 PM PST 24
Peak memory 213868 kb
Host smart-c03afa73-9d0e-4178-95d9-fda941aba948
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369144103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3369144103
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.907851964
Short name T636
Test name
Test status
Simulation time 54926654 ps
CPU time 0.83 seconds
Started Mar 03 12:38:59 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 195800 kb
Host smart-39734f64-bbf4-4be2-b3bc-2f8c4477f206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907851964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.907851964
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.697024299
Short name T549
Test name
Test status
Simulation time 31809541 ps
CPU time 0.79 seconds
Started Mar 03 12:38:57 PM PST 24
Finished Mar 03 12:38:58 PM PST 24
Peak memory 195984 kb
Host smart-54ed7d57-5cc1-4f57-8050-00e4219ee78f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697024299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.697024299
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3726696707
Short name T319
Test name
Test status
Simulation time 5579575256 ps
CPU time 143.77 seconds
Started Mar 03 12:39:01 PM PST 24
Finished Mar 03 12:41:26 PM PST 24
Peak memory 198092 kb
Host smart-ba99ac65-a7ed-4307-9152-071541caa52e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726696707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3726696707
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.662122711
Short name T387
Test name
Test status
Simulation time 17905222 ps
CPU time 0.56 seconds
Started Mar 03 12:39:27 PM PST 24
Finished Mar 03 12:39:29 PM PST 24
Peak memory 194100 kb
Host smart-89f7b773-7908-4f28-b2d7-54e0c3f6bf8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662122711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.662122711
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2527608528
Short name T452
Test name
Test status
Simulation time 26907835 ps
CPU time 0.72 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:31 PM PST 24
Peak memory 195980 kb
Host smart-65dd6a21-7039-4bc8-b56e-a79c2c747052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527608528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2527608528
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.4220226262
Short name T139
Test name
Test status
Simulation time 542616657 ps
CPU time 9.44 seconds
Started Mar 03 12:39:11 PM PST 24
Finished Mar 03 12:39:21 PM PST 24
Peak memory 197228 kb
Host smart-62d78e49-b9d6-4d85-b79b-cee5fdb8aa8c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220226262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.4220226262
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3179811418
Short name T17
Test name
Test status
Simulation time 78291315 ps
CPU time 0.62 seconds
Started Mar 03 12:39:15 PM PST 24
Finished Mar 03 12:39:23 PM PST 24
Peak memory 195268 kb
Host smart-e0121377-4348-4d1e-aa6d-cd55d3ebdb4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179811418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3179811418
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3025917662
Short name T441
Test name
Test status
Simulation time 20875709 ps
CPU time 0.73 seconds
Started Mar 03 12:39:18 PM PST 24
Finished Mar 03 12:39:21 PM PST 24
Peak memory 195588 kb
Host smart-7485a3e6-5d9b-4a30-b2b1-90d595e10a32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025917662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3025917662
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2259922499
Short name T473
Test name
Test status
Simulation time 218123797 ps
CPU time 2.36 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:33 PM PST 24
Peak memory 197244 kb
Host smart-9230a0de-e4a9-4d53-a5ad-27ca075eb349
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259922499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2259922499
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3197684915
Short name T231
Test name
Test status
Simulation time 677578277 ps
CPU time 3.6 seconds
Started Mar 03 12:39:24 PM PST 24
Finished Mar 03 12:39:28 PM PST 24
Peak memory 197200 kb
Host smart-fdb44a89-4c0d-4a8b-afa1-1e18ee9e145c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197684915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3197684915
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.4206815757
Short name T513
Test name
Test status
Simulation time 326526450 ps
CPU time 1.17 seconds
Started Mar 03 12:39:12 PM PST 24
Finished Mar 03 12:39:13 PM PST 24
Peak memory 196064 kb
Host smart-8b505708-d3a1-4cae-8ce9-ce5110a2bce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206815757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.4206815757
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1945889594
Short name T380
Test name
Test status
Simulation time 30076125 ps
CPU time 0.8 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:31 PM PST 24
Peak memory 196216 kb
Host smart-ff866d8c-946c-43db-8176-9f144541cfcc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945889594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1945889594
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.311191351
Short name T646
Test name
Test status
Simulation time 59869467 ps
CPU time 2.84 seconds
Started Mar 03 12:39:14 PM PST 24
Finished Mar 03 12:39:21 PM PST 24
Peak memory 198084 kb
Host smart-dbadc45d-1a64-4c2e-b0fb-ca905ed55210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311191351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.311191351
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.89064372
Short name T580
Test name
Test status
Simulation time 182018134 ps
CPU time 0.88 seconds
Started Mar 03 12:39:19 PM PST 24
Finished Mar 03 12:39:22 PM PST 24
Peak memory 195464 kb
Host smart-1cff71ca-df5a-4e7b-85a9-bbc981eecf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89064372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.89064372
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.29050096
Short name T363
Test name
Test status
Simulation time 77554447 ps
CPU time 1.05 seconds
Started Mar 03 12:39:26 PM PST 24
Finished Mar 03 12:39:27 PM PST 24
Peak memory 195688 kb
Host smart-249d0e46-8e1e-4d89-b550-006dcb0a56af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29050096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.29050096
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3843478425
Short name T685
Test name
Test status
Simulation time 5846342596 ps
CPU time 97.17 seconds
Started Mar 03 12:39:17 PM PST 24
Finished Mar 03 12:40:57 PM PST 24
Peak memory 198364 kb
Host smart-ff120335-61a1-4be4-ae9c-c81984a12a06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843478425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3843478425
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3819738982
Short name T253
Test name
Test status
Simulation time 14680957 ps
CPU time 0.58 seconds
Started Mar 03 12:39:16 PM PST 24
Finished Mar 03 12:39:21 PM PST 24
Peak memory 195048 kb
Host smart-4687e33b-78a1-46a1-9e06-53b926c0e9c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819738982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3819738982
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1220094425
Short name T150
Test name
Test status
Simulation time 55064129 ps
CPU time 0.94 seconds
Started Mar 03 12:39:13 PM PST 24
Finished Mar 03 12:39:26 PM PST 24
Peak memory 196640 kb
Host smart-ffef5eb0-4b8d-4d45-b7cf-64dc806f4e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220094425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1220094425
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3572422469
Short name T332
Test name
Test status
Simulation time 725231922 ps
CPU time 22.36 seconds
Started Mar 03 12:39:18 PM PST 24
Finished Mar 03 12:39:46 PM PST 24
Peak memory 196820 kb
Host smart-c0ed4a33-4dcc-46cd-a9a1-ef228d896371
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572422469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3572422469
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1287391655
Short name T637
Test name
Test status
Simulation time 66872593 ps
CPU time 0.87 seconds
Started Mar 03 12:39:14 PM PST 24
Finished Mar 03 12:39:16 PM PST 24
Peak memory 197680 kb
Host smart-15749394-233d-44c5-95bf-f4db2b20c41a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287391655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1287391655
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2630581140
Short name T234
Test name
Test status
Simulation time 39077175 ps
CPU time 1.07 seconds
Started Mar 03 12:39:25 PM PST 24
Finished Mar 03 12:39:26 PM PST 24
Peak memory 196148 kb
Host smart-7d3ab0c6-9e28-401c-9266-f99ce9962c40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630581140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2630581140
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3207100198
Short name T464
Test name
Test status
Simulation time 25114594 ps
CPU time 0.97 seconds
Started Mar 03 12:39:14 PM PST 24
Finished Mar 03 12:39:19 PM PST 24
Peak memory 195964 kb
Host smart-b33fd007-1409-4d00-a545-a36d644ca78f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207100198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3207100198
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1321339949
Short name T444
Test name
Test status
Simulation time 111677235 ps
CPU time 2.57 seconds
Started Mar 03 12:39:21 PM PST 24
Finished Mar 03 12:39:24 PM PST 24
Peak memory 198112 kb
Host smart-4725489b-f3f9-48cb-bdcd-3de91c48fdc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321339949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1321339949
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2596004835
Short name T396
Test name
Test status
Simulation time 58472475 ps
CPU time 1.28 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:32 PM PST 24
Peak memory 198088 kb
Host smart-68feb4ba-be02-4eff-9960-0571e313e44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596004835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2596004835
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2644684940
Short name T695
Test name
Test status
Simulation time 25279833 ps
CPU time 0.72 seconds
Started Mar 03 12:39:24 PM PST 24
Finished Mar 03 12:39:25 PM PST 24
Peak memory 195400 kb
Host smart-faf9d4c8-61dc-41f4-a76c-bee6abead7ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644684940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2644684940
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2768967989
Short name T465
Test name
Test status
Simulation time 1203663795 ps
CPU time 1.53 seconds
Started Mar 03 12:39:24 PM PST 24
Finished Mar 03 12:39:26 PM PST 24
Peak memory 198048 kb
Host smart-7b55b6fa-ef1f-439f-b207-1ae5ab2d80d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768967989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2768967989
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1966162783
Short name T613
Test name
Test status
Simulation time 99158462 ps
CPU time 1.39 seconds
Started Mar 03 12:39:27 PM PST 24
Finished Mar 03 12:39:29 PM PST 24
Peak memory 195560 kb
Host smart-05636a47-bf00-42e2-89dd-ff75a6cff75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966162783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1966162783
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2802085376
Short name T308
Test name
Test status
Simulation time 39890316 ps
CPU time 1.16 seconds
Started Mar 03 12:39:12 PM PST 24
Finished Mar 03 12:39:15 PM PST 24
Peak memory 195848 kb
Host smart-183282ff-6921-48e7-8872-db2d2499c899
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802085376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2802085376
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1437893512
Short name T394
Test name
Test status
Simulation time 62823997597 ps
CPU time 174.02 seconds
Started Mar 03 12:39:25 PM PST 24
Finished Mar 03 12:42:19 PM PST 24
Peak memory 198256 kb
Host smart-c90c7816-0626-4363-95b2-f48d280c253e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437893512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1437893512
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2851642576
Short name T632
Test name
Test status
Simulation time 45982543 ps
CPU time 0.58 seconds
Started Mar 03 12:39:53 PM PST 24
Finished Mar 03 12:39:54 PM PST 24
Peak memory 193472 kb
Host smart-555b3fd9-1748-4ffa-a155-b9dcd86723db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851642576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2851642576
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.683095306
Short name T47
Test name
Test status
Simulation time 30756326 ps
CPU time 0.83 seconds
Started Mar 03 12:39:41 PM PST 24
Finished Mar 03 12:39:42 PM PST 24
Peak memory 196372 kb
Host smart-1c71ffe4-a803-43e0-aede-78904af11472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683095306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.683095306
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3764788820
Short name T177
Test name
Test status
Simulation time 229475038 ps
CPU time 6.68 seconds
Started Mar 03 12:39:27 PM PST 24
Finished Mar 03 12:39:35 PM PST 24
Peak memory 197016 kb
Host smart-92686a45-4c4f-47ce-9baa-99bdad2fad4a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764788820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3764788820
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3964391572
Short name T607
Test name
Test status
Simulation time 273643018 ps
CPU time 1.01 seconds
Started Mar 03 12:39:25 PM PST 24
Finished Mar 03 12:39:27 PM PST 24
Peak memory 197076 kb
Host smart-d74e939e-e7f6-479d-bcb5-c53a42936fee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964391572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3964391572
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2436119036
Short name T184
Test name
Test status
Simulation time 115225431 ps
CPU time 0.79 seconds
Started Mar 03 12:39:29 PM PST 24
Finished Mar 03 12:39:30 PM PST 24
Peak memory 195672 kb
Host smart-50b8bebf-5b37-4bb5-bd8e-efade4921a42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436119036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2436119036
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3815049556
Short name T198
Test name
Test status
Simulation time 55570088 ps
CPU time 2.27 seconds
Started Mar 03 12:39:29 PM PST 24
Finished Mar 03 12:39:31 PM PST 24
Peak memory 198232 kb
Host smart-e208acf5-b2a1-484f-b614-5e6f7b920b11
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815049556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3815049556
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3756758993
Short name T455
Test name
Test status
Simulation time 437980784 ps
CPU time 2.97 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:35 PM PST 24
Peak memory 195948 kb
Host smart-008385bb-08dc-4291-a05e-4c2dc2068b35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756758993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3756758993
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3037551922
Short name T612
Test name
Test status
Simulation time 167980582 ps
CPU time 1.21 seconds
Started Mar 03 12:39:23 PM PST 24
Finished Mar 03 12:39:25 PM PST 24
Peak memory 196028 kb
Host smart-125a3e1f-74bf-4503-9b7f-7130214efcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037551922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3037551922
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.3436185749
Short name T174
Test name
Test status
Simulation time 23002151 ps
CPU time 0.85 seconds
Started Mar 03 12:39:14 PM PST 24
Finished Mar 03 12:39:16 PM PST 24
Peak memory 197280 kb
Host smart-946d57be-02b2-4c84-af06-60f436fe6145
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436185749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.3436185749
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.4231136030
Short name T20
Test name
Test status
Simulation time 315059550 ps
CPU time 3.66 seconds
Started Mar 03 12:39:34 PM PST 24
Finished Mar 03 12:39:38 PM PST 24
Peak memory 198060 kb
Host smart-70355d9c-f32e-4aec-933c-43ecbf28525c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231136030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.4231136030
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3504335318
Short name T301
Test name
Test status
Simulation time 44953909 ps
CPU time 0.9 seconds
Started Mar 03 12:39:20 PM PST 24
Finished Mar 03 12:39:22 PM PST 24
Peak memory 195336 kb
Host smart-ab641493-2c3f-4189-aabe-ae1bc8f257ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504335318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3504335318
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1508143409
Short name T306
Test name
Test status
Simulation time 177242710 ps
CPU time 1.01 seconds
Started Mar 03 12:39:13 PM PST 24
Finished Mar 03 12:39:16 PM PST 24
Peak memory 195540 kb
Host smart-14c8c7b4-0aa8-4ffa-8a27-dbb6763acdbd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508143409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1508143409
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2015180222
Short name T555
Test name
Test status
Simulation time 4064149951 ps
CPU time 110.56 seconds
Started Mar 03 12:39:29 PM PST 24
Finished Mar 03 12:41:20 PM PST 24
Peak memory 198252 kb
Host smart-0c32254b-c163-47cd-b6ee-26597df43a4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015180222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2015180222
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3874008994
Short name T429
Test name
Test status
Simulation time 24446746 ps
CPU time 0.57 seconds
Started Mar 03 12:39:38 PM PST 24
Finished Mar 03 12:39:38 PM PST 24
Peak memory 194304 kb
Host smart-abbc8dd3-32a5-47fd-a9ee-34bf1bc26073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874008994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3874008994
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2409003645
Short name T648
Test name
Test status
Simulation time 28847781 ps
CPU time 0.83 seconds
Started Mar 03 12:39:33 PM PST 24
Finished Mar 03 12:39:34 PM PST 24
Peak memory 196212 kb
Host smart-4c5cfa2d-a9a5-4c0e-b400-b60ea7eed3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409003645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2409003645
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2679663161
Short name T171
Test name
Test status
Simulation time 1025986971 ps
CPU time 4.42 seconds
Started Mar 03 12:39:47 PM PST 24
Finished Mar 03 12:39:51 PM PST 24
Peak memory 195836 kb
Host smart-c4f526e2-7862-482a-91c9-cc31cea1b3f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679663161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2679663161
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.584386777
Short name T23
Test name
Test status
Simulation time 355229910 ps
CPU time 1.08 seconds
Started Mar 03 12:39:28 PM PST 24
Finished Mar 03 12:39:30 PM PST 24
Peak memory 198132 kb
Host smart-c6cfd05c-7265-461c-96d0-cf6efd9c8cf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584386777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.584386777
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2540651097
Short name T138
Test name
Test status
Simulation time 63996921 ps
CPU time 0.84 seconds
Started Mar 03 12:39:34 PM PST 24
Finished Mar 03 12:39:35 PM PST 24
Peak memory 195680 kb
Host smart-a4650985-84cc-49f4-ace9-7f8586ccf90d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540651097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2540651097
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2072399233
Short name T240
Test name
Test status
Simulation time 33676370 ps
CPU time 1.41 seconds
Started Mar 03 12:39:49 PM PST 24
Finished Mar 03 12:39:50 PM PST 24
Peak memory 198384 kb
Host smart-f18114ba-0f96-4802-ac2f-9597ad4f5e76
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072399233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2072399233
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3783248030
Short name T390
Test name
Test status
Simulation time 327793272 ps
CPU time 1.09 seconds
Started Mar 03 12:39:43 PM PST 24
Finished Mar 03 12:39:44 PM PST 24
Peak memory 195452 kb
Host smart-eb001ff1-8dd0-4cce-bdd9-40ae11f3a375
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783248030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3783248030
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3426410962
Short name T510
Test name
Test status
Simulation time 44511366 ps
CPU time 0.93 seconds
Started Mar 03 12:39:15 PM PST 24
Finished Mar 03 12:39:21 PM PST 24
Peak memory 196584 kb
Host smart-23fb3ba8-c0b8-46f5-86b6-6fd24ea7574a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426410962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3426410962
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1838457952
Short name T157
Test name
Test status
Simulation time 801288957 ps
CPU time 1.2 seconds
Started Mar 03 12:39:28 PM PST 24
Finished Mar 03 12:39:30 PM PST 24
Peak memory 197080 kb
Host smart-f36d4f33-fa93-4e30-b57b-a2886a09a901
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838457952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1838457952
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3042419804
Short name T216
Test name
Test status
Simulation time 822247981 ps
CPU time 3.81 seconds
Started Mar 03 12:39:45 PM PST 24
Finished Mar 03 12:39:49 PM PST 24
Peak memory 198044 kb
Host smart-956d518e-afd8-463d-975a-11bb88ff23a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042419804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3042419804
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2695858210
Short name T123
Test name
Test status
Simulation time 179895054 ps
CPU time 1.07 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:32 PM PST 24
Peak memory 195744 kb
Host smart-08a8ac9b-c0f5-44cf-8b47-9112d079a644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695858210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2695858210
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3118941185
Short name T48
Test name
Test status
Simulation time 91528915 ps
CPU time 0.77 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:33 PM PST 24
Peak memory 195128 kb
Host smart-821d11e9-2ce7-4cd4-a9ba-fb82c2ce4df0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118941185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3118941185
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1580018263
Short name T551
Test name
Test status
Simulation time 7859581639 ps
CPU time 59.53 seconds
Started Mar 03 12:39:22 PM PST 24
Finished Mar 03 12:40:27 PM PST 24
Peak memory 198324 kb
Host smart-94be4b64-ff44-45b3-a1fc-645ae8e64135
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580018263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1580018263
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1849396301
Short name T627
Test name
Test status
Simulation time 13017198 ps
CPU time 0.64 seconds
Started Mar 03 12:39:29 PM PST 24
Finished Mar 03 12:39:29 PM PST 24
Peak memory 194732 kb
Host smart-fb0ea9c1-1ae8-4a87-843f-a941d10b6339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849396301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1849396301
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.4023575099
Short name T422
Test name
Test status
Simulation time 33205155 ps
CPU time 0.86 seconds
Started Mar 03 12:39:27 PM PST 24
Finished Mar 03 12:39:29 PM PST 24
Peak memory 196160 kb
Host smart-578bb727-e1c0-4afb-9216-a58a818f9bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023575099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.4023575099
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2603976449
Short name T25
Test name
Test status
Simulation time 398287707 ps
CPU time 11.82 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:44 PM PST 24
Peak memory 198340 kb
Host smart-dc98a843-24ca-4ea4-afad-76aa6b97c16a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603976449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2603976449
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.4098426636
Short name T707
Test name
Test status
Simulation time 180340964 ps
CPU time 1.07 seconds
Started Mar 03 12:39:30 PM PST 24
Finished Mar 03 12:39:32 PM PST 24
Peak memory 196488 kb
Host smart-22315ad2-9811-4649-bd17-50caf179e73e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098426636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.4098426636
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3793147659
Short name T702
Test name
Test status
Simulation time 224828448 ps
CPU time 1.07 seconds
Started Mar 03 12:39:33 PM PST 24
Finished Mar 03 12:39:35 PM PST 24
Peak memory 196064 kb
Host smart-bd581324-aede-4f0f-9193-1cfcb7b26d0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793147659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3793147659
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.995296319
Short name T95
Test name
Test status
Simulation time 218252011 ps
CPU time 2.09 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:35 PM PST 24
Peak memory 198088 kb
Host smart-61b5d340-7257-4ce2-bacb-ba2397c4b570
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995296319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.gpio_intr_with_filter_rand_intr_event.995296319
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2616966512
Short name T260
Test name
Test status
Simulation time 567124023 ps
CPU time 2.72 seconds
Started Mar 03 12:39:33 PM PST 24
Finished Mar 03 12:39:36 PM PST 24
Peak memory 197052 kb
Host smart-cf5dbc64-8ae2-4d13-9c09-1420b9e843d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616966512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2616966512
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.190300494
Short name T629
Test name
Test status
Simulation time 25028819 ps
CPU time 0.71 seconds
Started Mar 03 12:39:46 PM PST 24
Finished Mar 03 12:39:47 PM PST 24
Peak memory 195332 kb
Host smart-9b8fd696-ec0e-45d5-b8ec-e8769740d8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190300494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.190300494
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2622237218
Short name T406
Test name
Test status
Simulation time 61808521 ps
CPU time 1.37 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:33 PM PST 24
Peak memory 197252 kb
Host smart-3a828453-4462-4f91-8ef8-dba76c25e992
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622237218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2622237218
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1760066888
Short name T411
Test name
Test status
Simulation time 993226517 ps
CPU time 2.92 seconds
Started Mar 03 12:39:24 PM PST 24
Finished Mar 03 12:39:28 PM PST 24
Peak memory 197984 kb
Host smart-2e4f2823-21a1-4b3e-b68d-884aed46da20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760066888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1760066888
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2870403728
Short name T548
Test name
Test status
Simulation time 408656039 ps
CPU time 1.17 seconds
Started Mar 03 12:39:40 PM PST 24
Finished Mar 03 12:39:41 PM PST 24
Peak memory 196408 kb
Host smart-bfbaed60-2da6-46a4-ac37-8fe8adda69cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870403728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2870403728
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.827367254
Short name T389
Test name
Test status
Simulation time 302123618 ps
CPU time 1.12 seconds
Started Mar 03 12:39:26 PM PST 24
Finished Mar 03 12:39:27 PM PST 24
Peak memory 195632 kb
Host smart-f8e04b98-d728-4699-8772-6bba518eaa6a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827367254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.827367254
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3087352711
Short name T293
Test name
Test status
Simulation time 16814559307 ps
CPU time 113.47 seconds
Started Mar 03 12:39:27 PM PST 24
Finished Mar 03 12:41:20 PM PST 24
Peak memory 198256 kb
Host smart-852424fc-4592-4302-a83f-d755125cfdbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087352711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3087352711
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.3437015903
Short name T59
Test name
Test status
Simulation time 28637989936 ps
CPU time 300.43 seconds
Started Mar 03 12:39:36 PM PST 24
Finished Mar 03 12:44:37 PM PST 24
Peak memory 198436 kb
Host smart-ec8ca9d2-3d99-4c5b-8526-26f6c45fd628
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3437015903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.3437015903
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3039781103
Short name T657
Test name
Test status
Simulation time 19060594 ps
CPU time 0.6 seconds
Started Mar 03 12:39:58 PM PST 24
Finished Mar 03 12:39:59 PM PST 24
Peak memory 194248 kb
Host smart-43c9dfda-79db-4f0d-a4b0-fd4d417b52f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039781103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3039781103
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2728013228
Short name T131
Test name
Test status
Simulation time 87148383 ps
CPU time 0.69 seconds
Started Mar 03 12:39:30 PM PST 24
Finished Mar 03 12:39:31 PM PST 24
Peak memory 194184 kb
Host smart-0e97d706-6b03-4ca9-95c7-3ab420eb3fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728013228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2728013228
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2511080037
Short name T291
Test name
Test status
Simulation time 239910280 ps
CPU time 6.9 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:43 PM PST 24
Peak memory 197132 kb
Host smart-dbce508e-dc6f-4a35-afa8-ee274be49961
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511080037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2511080037
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1118822506
Short name T713
Test name
Test status
Simulation time 20368106 ps
CPU time 0.69 seconds
Started Mar 03 12:39:30 PM PST 24
Finished Mar 03 12:39:31 PM PST 24
Peak memory 194568 kb
Host smart-72fb29cb-3078-4282-878a-9275b19e2a94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118822506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1118822506
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2804539606
Short name T377
Test name
Test status
Simulation time 139993487 ps
CPU time 0.63 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:31 PM PST 24
Peak memory 194988 kb
Host smart-e015088d-d323-4045-b669-17c40474000e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804539606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2804539606
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2468104936
Short name T346
Test name
Test status
Simulation time 349667318 ps
CPU time 3.4 seconds
Started Mar 03 12:39:46 PM PST 24
Finished Mar 03 12:39:53 PM PST 24
Peak memory 198116 kb
Host smart-bd9538c5-58f0-4125-8129-2f84c2c7ab88
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468104936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2468104936
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3007443178
Short name T462
Test name
Test status
Simulation time 77050367 ps
CPU time 2.2 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:35 PM PST 24
Peak memory 197096 kb
Host smart-4f6b7a4d-a878-4b4d-bf2b-25a928bc748c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007443178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3007443178
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1902696910
Short name T222
Test name
Test status
Simulation time 28061566 ps
CPU time 0.83 seconds
Started Mar 03 12:39:27 PM PST 24
Finished Mar 03 12:39:28 PM PST 24
Peak memory 196236 kb
Host smart-95e3e528-9850-4d66-8bfe-3b16c28ec0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902696910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1902696910
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1960934552
Short name T114
Test name
Test status
Simulation time 179126703 ps
CPU time 1.21 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:34 PM PST 24
Peak memory 197980 kb
Host smart-9c3652b4-b563-4768-bb37-6c85b107a100
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960934552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1960934552
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3288861464
Short name T356
Test name
Test status
Simulation time 201608408 ps
CPU time 2.76 seconds
Started Mar 03 12:39:25 PM PST 24
Finished Mar 03 12:39:28 PM PST 24
Peak memory 198068 kb
Host smart-a2272a7a-efae-4e73-b004-60a86b9ec304
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288861464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3288861464
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3590189585
Short name T480
Test name
Test status
Simulation time 90897568 ps
CPU time 1.31 seconds
Started Mar 03 12:39:30 PM PST 24
Finished Mar 03 12:39:32 PM PST 24
Peak memory 196844 kb
Host smart-fd496d34-d275-4ad2-8ba2-615a3e8b1409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590189585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3590189585
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.279447189
Short name T316
Test name
Test status
Simulation time 50899804 ps
CPU time 1.29 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:34 PM PST 24
Peak memory 196800 kb
Host smart-c3e874eb-f1b1-4ce0-bbe9-a25f05fa7c92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279447189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.279447189
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.181292223
Short name T362
Test name
Test status
Simulation time 10869866470 ps
CPU time 136.66 seconds
Started Mar 03 12:39:30 PM PST 24
Finished Mar 03 12:41:46 PM PST 24
Peak memory 198128 kb
Host smart-729c06d5-c89f-4d51-8ce9-ebb2e971311f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181292223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.181292223
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2100829274
Short name T299
Test name
Test status
Simulation time 15606056 ps
CPU time 0.6 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:31 PM PST 24
Peak memory 193280 kb
Host smart-684f0ea2-7f21-427a-b3ff-96ba7e221028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100829274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2100829274
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.392528438
Short name T104
Test name
Test status
Simulation time 124284126 ps
CPU time 0.84 seconds
Started Mar 03 12:39:42 PM PST 24
Finished Mar 03 12:39:43 PM PST 24
Peak memory 196016 kb
Host smart-425e55d7-3b4d-4655-a077-7e0fdfba89e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392528438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.392528438
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3916386290
Short name T615
Test name
Test status
Simulation time 2115780336 ps
CPU time 17.63 seconds
Started Mar 03 12:39:47 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 195576 kb
Host smart-0aac22d6-4194-4a1a-8a8a-16962b5cd598
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916386290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3916386290
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3284537780
Short name T22
Test name
Test status
Simulation time 59063725 ps
CPU time 0.9 seconds
Started Mar 03 12:39:29 PM PST 24
Finished Mar 03 12:39:30 PM PST 24
Peak memory 196500 kb
Host smart-da536858-8187-4f49-8322-543e233c9ee7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284537780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3284537780
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.275329431
Short name T609
Test name
Test status
Simulation time 389433017 ps
CPU time 1.25 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:33 PM PST 24
Peak memory 195960 kb
Host smart-f7ceb34a-42c0-49f1-b947-3ace8c5ea42c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275329431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.275329431
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3227954468
Short name T378
Test name
Test status
Simulation time 338629001 ps
CPU time 3.58 seconds
Started Mar 03 12:39:29 PM PST 24
Finished Mar 03 12:39:32 PM PST 24
Peak memory 198252 kb
Host smart-39cc3bb6-d3f6-4787-813d-3cbe75fed9df
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227954468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3227954468
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1162102452
Short name T269
Test name
Test status
Simulation time 62119646 ps
CPU time 1.66 seconds
Started Mar 03 12:39:29 PM PST 24
Finished Mar 03 12:39:31 PM PST 24
Peak memory 196160 kb
Host smart-31c40b94-140f-4dae-955e-69f8be3ad97b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162102452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1162102452
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1942330498
Short name T457
Test name
Test status
Simulation time 46369677 ps
CPU time 0.94 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:32 PM PST 24
Peak memory 195980 kb
Host smart-3467b924-8551-48ad-a6d2-aebef83ea893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942330498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1942330498
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1336414040
Short name T477
Test name
Test status
Simulation time 40786418 ps
CPU time 1.08 seconds
Started Mar 03 12:39:29 PM PST 24
Finished Mar 03 12:39:30 PM PST 24
Peak memory 196740 kb
Host smart-86844a0f-9d58-45bc-882c-fdd162dcc74e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336414040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1336414040
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3301334607
Short name T463
Test name
Test status
Simulation time 112170430 ps
CPU time 5.14 seconds
Started Mar 03 12:39:30 PM PST 24
Finished Mar 03 12:39:35 PM PST 24
Peak memory 198096 kb
Host smart-31d1905a-04d3-4449-9cb8-651b8ccf1c6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301334607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3301334607
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2714335540
Short name T309
Test name
Test status
Simulation time 32776623 ps
CPU time 0.85 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:33 PM PST 24
Peak memory 196012 kb
Host smart-99d7933d-a256-479f-a277-ef807e42f731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714335540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2714335540
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3798994487
Short name T170
Test name
Test status
Simulation time 28855508 ps
CPU time 0.71 seconds
Started Mar 03 12:39:45 PM PST 24
Finished Mar 03 12:39:46 PM PST 24
Peak memory 194916 kb
Host smart-916054e5-fb30-4aae-942e-26ea900cc0b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798994487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3798994487
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1063064389
Short name T124
Test name
Test status
Simulation time 15429033946 ps
CPU time 105.19 seconds
Started Mar 03 12:40:03 PM PST 24
Finished Mar 03 12:41:48 PM PST 24
Peak memory 198284 kb
Host smart-f4743cee-b580-4f3f-a94f-fb85474b3bf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063064389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1063064389
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.733573257
Short name T546
Test name
Test status
Simulation time 15757410 ps
CPU time 0.56 seconds
Started Mar 03 12:39:44 PM PST 24
Finished Mar 03 12:39:44 PM PST 24
Peak memory 194076 kb
Host smart-c8441f6f-7a28-4989-8831-5a1f4f3a86ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733573257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.733573257
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.597544423
Short name T145
Test name
Test status
Simulation time 41438851 ps
CPU time 0.89 seconds
Started Mar 03 12:39:49 PM PST 24
Finished Mar 03 12:39:50 PM PST 24
Peak memory 197220 kb
Host smart-07e413a5-9313-4164-8e71-5bb01ebcb6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597544423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.597544423
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2620145597
Short name T576
Test name
Test status
Simulation time 1900031759 ps
CPU time 15.77 seconds
Started Mar 03 12:39:30 PM PST 24
Finished Mar 03 12:39:46 PM PST 24
Peak memory 198016 kb
Host smart-52113af9-4662-4beb-8b50-dca3dd3b42fd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620145597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2620145597
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2529991945
Short name T403
Test name
Test status
Simulation time 397962048 ps
CPU time 0.79 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:32 PM PST 24
Peak memory 196664 kb
Host smart-af920ebe-7a34-446d-af7e-761896617852
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529991945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2529991945
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.87449299
Short name T101
Test name
Test status
Simulation time 51726512 ps
CPU time 1.4 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:34 PM PST 24
Peak memory 195840 kb
Host smart-9bcb2b48-fb33-4546-a8ec-fc4cc2bad50f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87449299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.87449299
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3486907151
Short name T49
Test name
Test status
Simulation time 104196878 ps
CPU time 1.45 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:33 PM PST 24
Peak memory 196832 kb
Host smart-849b9026-fed7-46d2-a355-c17ce80fe436
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486907151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3486907151
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.509703680
Short name T478
Test name
Test status
Simulation time 373686098 ps
CPU time 2.42 seconds
Started Mar 03 12:39:25 PM PST 24
Finished Mar 03 12:39:28 PM PST 24
Peak memory 195868 kb
Host smart-4a78b8e0-d224-4354-a264-429c0e86df76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509703680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
509703680
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1999491206
Short name T297
Test name
Test status
Simulation time 27927245 ps
CPU time 0.8 seconds
Started Mar 03 12:39:51 PM PST 24
Finished Mar 03 12:39:52 PM PST 24
Peak memory 195340 kb
Host smart-bf1ea643-cf46-49e4-8565-5272a0b6dd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999491206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1999491206
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1734092123
Short name T352
Test name
Test status
Simulation time 18719498 ps
CPU time 0.79 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:33 PM PST 24
Peak memory 196472 kb
Host smart-02de0108-1284-4603-907d-d9c34fccaad5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734092123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1734092123
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1330374580
Short name T258
Test name
Test status
Simulation time 318659262 ps
CPU time 4.86 seconds
Started Mar 03 12:39:48 PM PST 24
Finished Mar 03 12:39:53 PM PST 24
Peak memory 198020 kb
Host smart-1f6ddbb6-bd34-48b4-a135-48ebb73fec99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330374580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1330374580
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2626918612
Short name T148
Test name
Test status
Simulation time 168168831 ps
CPU time 0.92 seconds
Started Mar 03 12:39:44 PM PST 24
Finished Mar 03 12:39:45 PM PST 24
Peak memory 196372 kb
Host smart-087ef8fe-316c-430b-be6c-4671d22117b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626918612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2626918612
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2279795030
Short name T523
Test name
Test status
Simulation time 51448030 ps
CPU time 1.03 seconds
Started Mar 03 12:40:01 PM PST 24
Finished Mar 03 12:40:02 PM PST 24
Peak memory 195832 kb
Host smart-9aa47c61-0d48-4828-8244-f1b05023992c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279795030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2279795030
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.888857070
Short name T606
Test name
Test status
Simulation time 29972006367 ps
CPU time 189.69 seconds
Started Mar 03 12:40:01 PM PST 24
Finished Mar 03 12:43:11 PM PST 24
Peak memory 198232 kb
Host smart-3b3b7e2b-da07-438a-819f-23ba90bd5a38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888857070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.888857070
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1536990609
Short name T618
Test name
Test status
Simulation time 99067575402 ps
CPU time 710.31 seconds
Started Mar 03 12:39:30 PM PST 24
Finished Mar 03 12:51:21 PM PST 24
Peak memory 198468 kb
Host smart-59f4297b-0cf3-4dbe-95ec-29dacfe0fbb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1536990609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1536990609
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1839509965
Short name T717
Test name
Test status
Simulation time 17893282 ps
CPU time 0.56 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:33 PM PST 24
Peak memory 193928 kb
Host smart-d6235733-4430-400a-bda2-849f24f30fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839509965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1839509965
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.4209782261
Short name T116
Test name
Test status
Simulation time 15469887 ps
CPU time 0.6 seconds
Started Mar 03 12:39:25 PM PST 24
Finished Mar 03 12:39:25 PM PST 24
Peak memory 193920 kb
Host smart-1856302b-5c79-41dd-bca7-facf8ac535f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209782261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.4209782261
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.669771645
Short name T720
Test name
Test status
Simulation time 527995725 ps
CPU time 3.76 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:34 PM PST 24
Peak memory 195544 kb
Host smart-8be24265-f036-47f9-ad6f-4f8ef321388d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669771645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.669771645
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3134711216
Short name T631
Test name
Test status
Simulation time 40597358 ps
CPU time 0.65 seconds
Started Mar 03 12:39:29 PM PST 24
Finished Mar 03 12:39:30 PM PST 24
Peak memory 195192 kb
Host smart-be5a71a5-8d3d-40dd-a9bd-b8f586b928a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134711216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3134711216
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.601875662
Short name T367
Test name
Test status
Simulation time 68342655 ps
CPU time 1.09 seconds
Started Mar 03 12:39:49 PM PST 24
Finished Mar 03 12:39:50 PM PST 24
Peak memory 196112 kb
Host smart-cffaefff-7ecb-4fed-b98c-f0fd7b205e33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601875662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.601875662
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3307299285
Short name T242
Test name
Test status
Simulation time 43812814 ps
CPU time 1.89 seconds
Started Mar 03 12:39:27 PM PST 24
Finished Mar 03 12:39:29 PM PST 24
Peak memory 197984 kb
Host smart-46ee6c5f-7ea8-4a43-887d-c4b2954849f4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307299285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3307299285
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.4228007158
Short name T134
Test name
Test status
Simulation time 166234047 ps
CPU time 3.09 seconds
Started Mar 03 12:39:43 PM PST 24
Finished Mar 03 12:39:47 PM PST 24
Peak memory 197248 kb
Host smart-1d73d59d-5bae-422d-93b1-2542e112cacf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228007158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.4228007158
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1865952741
Short name T343
Test name
Test status
Simulation time 44626664 ps
CPU time 0.77 seconds
Started Mar 03 12:39:30 PM PST 24
Finished Mar 03 12:39:31 PM PST 24
Peak memory 196160 kb
Host smart-489131b1-12dd-41d5-aa19-78f36bd80d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865952741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1865952741
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2332293891
Short name T659
Test name
Test status
Simulation time 33970979 ps
CPU time 0.77 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:33 PM PST 24
Peak memory 195516 kb
Host smart-a20d29e0-201d-4b56-98a2-a911b7ee08d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332293891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2332293891
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2524588549
Short name T381
Test name
Test status
Simulation time 34338129 ps
CPU time 1.42 seconds
Started Mar 03 12:39:41 PM PST 24
Finished Mar 03 12:39:42 PM PST 24
Peak memory 197968 kb
Host smart-7a949ffc-5f5b-46d1-9899-21438b65fd43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524588549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2524588549
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.444814227
Short name T670
Test name
Test status
Simulation time 133007917 ps
CPU time 1.12 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:32 PM PST 24
Peak memory 195844 kb
Host smart-1a083f5e-8246-420d-a38b-30dc7e75328f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444814227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.444814227
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2483090387
Short name T449
Test name
Test status
Simulation time 25747616 ps
CPU time 0.79 seconds
Started Mar 03 12:39:27 PM PST 24
Finished Mar 03 12:39:33 PM PST 24
Peak memory 195288 kb
Host smart-7b8be5e1-4342-423e-aacb-2f9eb9e1997f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483090387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2483090387
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3022153049
Short name T252
Test name
Test status
Simulation time 15619418968 ps
CPU time 92.51 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:41:05 PM PST 24
Peak memory 198148 kb
Host smart-c332c4db-f448-4324-b9da-ec9d9eee1017
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022153049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3022153049
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3504119230
Short name T718
Test name
Test status
Simulation time 14359832 ps
CPU time 0.56 seconds
Started Mar 03 12:39:42 PM PST 24
Finished Mar 03 12:39:48 PM PST 24
Peak memory 194704 kb
Host smart-455596d4-3e58-4b36-8128-87def75987ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504119230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3504119230
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1887319236
Short name T526
Test name
Test status
Simulation time 101195826 ps
CPU time 0.87 seconds
Started Mar 03 12:39:41 PM PST 24
Finished Mar 03 12:39:41 PM PST 24
Peak memory 196428 kb
Host smart-76aa98bf-9b87-4034-aee6-fc28ed8e3358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887319236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1887319236
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1151417502
Short name T122
Test name
Test status
Simulation time 274711313 ps
CPU time 4.57 seconds
Started Mar 03 12:39:51 PM PST 24
Finished Mar 03 12:39:55 PM PST 24
Peak memory 195584 kb
Host smart-3a07b1c0-c6e5-4697-8a4c-1faa3b73dd3b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151417502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1151417502
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1715939312
Short name T191
Test name
Test status
Simulation time 69740492 ps
CPU time 0.87 seconds
Started Mar 03 12:39:49 PM PST 24
Finished Mar 03 12:39:50 PM PST 24
Peak memory 196700 kb
Host smart-12452d46-4626-4c04-9ceb-df146f81d35b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715939312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1715939312
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2519188868
Short name T98
Test name
Test status
Simulation time 331834274 ps
CPU time 1.23 seconds
Started Mar 03 12:39:43 PM PST 24
Finished Mar 03 12:39:44 PM PST 24
Peak memory 196364 kb
Host smart-649b5826-7714-4ed2-b8e1-bbc56d665ffa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519188868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2519188868
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1227838212
Short name T484
Test name
Test status
Simulation time 45548613 ps
CPU time 1.8 seconds
Started Mar 03 12:39:36 PM PST 24
Finished Mar 03 12:39:37 PM PST 24
Peak memory 198212 kb
Host smart-2f652069-6bad-435e-855d-067089f85375
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227838212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1227838212
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.939081666
Short name T587
Test name
Test status
Simulation time 201363002 ps
CPU time 2.14 seconds
Started Mar 03 12:39:29 PM PST 24
Finished Mar 03 12:39:32 PM PST 24
Peak memory 198108 kb
Host smart-ba9eec39-bb61-44b8-91b2-21300269b16a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939081666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
939081666
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.405320346
Short name T296
Test name
Test status
Simulation time 18815690 ps
CPU time 0.63 seconds
Started Mar 03 12:39:55 PM PST 24
Finished Mar 03 12:39:56 PM PST 24
Peak memory 194196 kb
Host smart-c3726aa7-5b19-4a6e-ad20-35f8987dcd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405320346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.405320346
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.336032522
Short name T405
Test name
Test status
Simulation time 34131606 ps
CPU time 0.66 seconds
Started Mar 03 12:39:39 PM PST 24
Finished Mar 03 12:39:40 PM PST 24
Peak memory 195008 kb
Host smart-c8ec417d-2895-4814-949d-b2bf22b66727
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336032522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.336032522
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.4074010375
Short name T418
Test name
Test status
Simulation time 1108611836 ps
CPU time 4.74 seconds
Started Mar 03 12:39:46 PM PST 24
Finished Mar 03 12:39:51 PM PST 24
Peak memory 198152 kb
Host smart-4aa07b40-aeef-40d2-8f6b-2f43d5fe88ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074010375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.4074010375
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3137294115
Short name T295
Test name
Test status
Simulation time 76449192 ps
CPU time 0.77 seconds
Started Mar 03 12:39:43 PM PST 24
Finished Mar 03 12:39:43 PM PST 24
Peak memory 195172 kb
Host smart-d4d61c7a-a070-4938-aba8-1d18bcaee207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137294115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3137294115
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3956058772
Short name T335
Test name
Test status
Simulation time 309452231 ps
CPU time 1.23 seconds
Started Mar 03 12:39:44 PM PST 24
Finished Mar 03 12:39:45 PM PST 24
Peak memory 196496 kb
Host smart-20887869-bc9d-4ec4-aa43-6f9e1786d7c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956058772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3956058772
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3335391320
Short name T610
Test name
Test status
Simulation time 27559365530 ps
CPU time 109.25 seconds
Started Mar 03 12:39:34 PM PST 24
Finished Mar 03 12:41:23 PM PST 24
Peak memory 198240 kb
Host smart-8edc0476-577f-4728-ba17-1867b9f86ca8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335391320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3335391320
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.4150857589
Short name T271
Test name
Test status
Simulation time 25097350 ps
CPU time 0.56 seconds
Started Mar 03 12:38:59 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 194020 kb
Host smart-32f2b2fc-f423-498f-aa01-9aa57b7ddd12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150857589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.4150857589
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2281060895
Short name T172
Test name
Test status
Simulation time 27191711 ps
CPU time 0.81 seconds
Started Mar 03 12:38:58 PM PST 24
Finished Mar 03 12:38:59 PM PST 24
Peak memory 195456 kb
Host smart-5f34cb57-a12f-4832-8730-4bb3f6197ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281060895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2281060895
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2882501017
Short name T254
Test name
Test status
Simulation time 200541073 ps
CPU time 3.73 seconds
Started Mar 03 12:38:56 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 196068 kb
Host smart-d30cf3ac-c283-4da5-9bdd-86ed519af6e4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882501017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2882501017
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1625552085
Short name T290
Test name
Test status
Simulation time 48464605 ps
CPU time 0.69 seconds
Started Mar 03 12:39:01 PM PST 24
Finished Mar 03 12:39:03 PM PST 24
Peak memory 194616 kb
Host smart-e1bf494e-8d4a-4076-8f4b-4d2275df3598
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625552085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1625552085
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1864162892
Short name T344
Test name
Test status
Simulation time 154905315 ps
CPU time 0.91 seconds
Started Mar 03 12:39:00 PM PST 24
Finished Mar 03 12:39:01 PM PST 24
Peak memory 196592 kb
Host smart-2f393dd3-d5db-4231-b0a9-0331caa663a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864162892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1864162892
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.4153127348
Short name T94
Test name
Test status
Simulation time 347799072 ps
CPU time 3.47 seconds
Started Mar 03 12:38:58 PM PST 24
Finished Mar 03 12:39:02 PM PST 24
Peak memory 198144 kb
Host smart-f5f32ac0-2495-4447-afb6-531874b32001
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153127348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.4153127348
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3974536786
Short name T604
Test name
Test status
Simulation time 148116323 ps
CPU time 1.97 seconds
Started Mar 03 12:38:58 PM PST 24
Finished Mar 03 12:39:01 PM PST 24
Peak memory 196920 kb
Host smart-616d2fea-270a-4ba6-99e4-828276b3c104
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974536786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3974536786
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3279285636
Short name T365
Test name
Test status
Simulation time 195896706 ps
CPU time 1.11 seconds
Started Mar 03 12:38:59 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 196080 kb
Host smart-55dbc689-2fca-4713-8095-ddd77329ba8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279285636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3279285636
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.4009683827
Short name T476
Test name
Test status
Simulation time 120721883 ps
CPU time 0.82 seconds
Started Mar 03 12:38:59 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 196100 kb
Host smart-f4b939e0-a7d2-4641-b4b1-c43b6bff94ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009683827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.4009683827
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2719608911
Short name T348
Test name
Test status
Simulation time 681027644 ps
CPU time 5.62 seconds
Started Mar 03 12:39:01 PM PST 24
Finished Mar 03 12:39:08 PM PST 24
Peak memory 197960 kb
Host smart-5ba65af4-884e-4bfe-9388-2665b808c0c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719608911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2719608911
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1906147190
Short name T31
Test name
Test status
Simulation time 82050661 ps
CPU time 0.82 seconds
Started Mar 03 12:38:59 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 213708 kb
Host smart-bc31aabb-2ae6-48bb-a391-1c9cfd526372
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906147190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1906147190
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.866281122
Short name T573
Test name
Test status
Simulation time 173628296 ps
CPU time 1.13 seconds
Started Mar 03 12:39:02 PM PST 24
Finished Mar 03 12:39:04 PM PST 24
Peak memory 195908 kb
Host smart-42b8e31a-4deb-40a5-83dd-29f54bb51cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866281122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.866281122
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1406460834
Short name T563
Test name
Test status
Simulation time 43308466 ps
CPU time 1.18 seconds
Started Mar 03 12:38:56 PM PST 24
Finished Mar 03 12:38:58 PM PST 24
Peak memory 195888 kb
Host smart-b7af7210-98c8-40a3-8120-1c5cbfb1efdf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406460834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1406460834
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.862838448
Short name T425
Test name
Test status
Simulation time 21579035484 ps
CPU time 246.43 seconds
Started Mar 03 12:38:57 PM PST 24
Finished Mar 03 12:43:04 PM PST 24
Peak memory 198244 kb
Host smart-13ee9b95-c8be-417f-84f7-1865b30857b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862838448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.862838448
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.706254238
Short name T4
Test name
Test status
Simulation time 103758784284 ps
CPU time 585.14 seconds
Started Mar 03 12:38:58 PM PST 24
Finished Mar 03 12:48:44 PM PST 24
Peak memory 198392 kb
Host smart-a367dbac-5cd7-4edb-b27a-6d0c353620b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=706254238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.706254238
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2770845160
Short name T35
Test name
Test status
Simulation time 22102722 ps
CPU time 0.57 seconds
Started Mar 03 12:39:37 PM PST 24
Finished Mar 03 12:39:38 PM PST 24
Peak memory 194648 kb
Host smart-93b14779-c35d-4f20-b978-4c1a101715b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770845160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2770845160
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.3084294027
Short name T593
Test name
Test status
Simulation time 26812494 ps
CPU time 0.74 seconds
Started Mar 03 12:40:19 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 194184 kb
Host smart-29e0f68f-f08e-4275-9434-2d7219c77979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084294027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.3084294027
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.861466863
Short name T275
Test name
Test status
Simulation time 2057029333 ps
CPU time 25.9 seconds
Started Mar 03 12:39:48 PM PST 24
Finished Mar 03 12:40:14 PM PST 24
Peak memory 195616 kb
Host smart-92b3818c-5360-4df2-9a80-d37f2a34ebd9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861466863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.861466863
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3942752939
Short name T336
Test name
Test status
Simulation time 64970183 ps
CPU time 0.82 seconds
Started Mar 03 12:39:49 PM PST 24
Finished Mar 03 12:39:50 PM PST 24
Peak memory 196296 kb
Host smart-2d1bd899-94a1-426c-bb19-162c1f4cac1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942752939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3942752939
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.830837872
Short name T388
Test name
Test status
Simulation time 33390650 ps
CPU time 0.66 seconds
Started Mar 03 12:39:52 PM PST 24
Finished Mar 03 12:39:53 PM PST 24
Peak memory 194156 kb
Host smart-d9109928-1808-4ca4-9110-4db0d594adbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830837872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.830837872
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.828637333
Short name T677
Test name
Test status
Simulation time 242454527 ps
CPU time 2.52 seconds
Started Mar 03 12:39:46 PM PST 24
Finished Mar 03 12:39:48 PM PST 24
Peak memory 198060 kb
Host smart-902d3709-2d6f-4076-856b-187b0b13ad99
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828637333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.828637333
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1104079031
Short name T313
Test name
Test status
Simulation time 52617396 ps
CPU time 1.63 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:33 PM PST 24
Peak memory 196500 kb
Host smart-d045c77e-0696-4fcf-912d-e22704eef281
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104079031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1104079031
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.4088599785
Short name T266
Test name
Test status
Simulation time 58557685 ps
CPU time 1.12 seconds
Started Mar 03 12:39:53 PM PST 24
Finished Mar 03 12:39:55 PM PST 24
Peak memory 195912 kb
Host smart-c57b25ee-3d3c-410c-8ee9-2a927e2fbb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088599785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.4088599785
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2892839164
Short name T524
Test name
Test status
Simulation time 113304119 ps
CPU time 1.09 seconds
Started Mar 03 12:39:46 PM PST 24
Finished Mar 03 12:39:48 PM PST 24
Peak memory 195804 kb
Host smart-751ca18e-2b0a-4dd7-8250-1ca62e3ed0d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892839164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2892839164
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2393165168
Short name T350
Test name
Test status
Simulation time 300842381 ps
CPU time 4.75 seconds
Started Mar 03 12:39:52 PM PST 24
Finished Mar 03 12:39:57 PM PST 24
Peak memory 198044 kb
Host smart-376702ee-cfe4-4b6b-bab2-1821f0fb4da1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393165168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2393165168
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.454848509
Short name T178
Test name
Test status
Simulation time 114102913 ps
CPU time 1.29 seconds
Started Mar 03 12:39:43 PM PST 24
Finished Mar 03 12:39:45 PM PST 24
Peak memory 195700 kb
Host smart-17c1df3c-e3cd-4cf5-b4a1-5c4d61d35902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454848509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.454848509
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1969805904
Short name T634
Test name
Test status
Simulation time 72991708 ps
CPU time 1.18 seconds
Started Mar 03 12:39:34 PM PST 24
Finished Mar 03 12:39:35 PM PST 24
Peak memory 196736 kb
Host smart-c8493d18-5016-45ee-8853-57434320d2b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969805904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1969805904
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2450244408
Short name T315
Test name
Test status
Simulation time 13673207672 ps
CPU time 63.45 seconds
Started Mar 03 12:39:47 PM PST 24
Finished Mar 03 12:40:50 PM PST 24
Peak memory 198332 kb
Host smart-c6c66025-0c5c-418e-b89d-5c8e595b4dcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450244408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2450244408
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.1287983218
Short name T264
Test name
Test status
Simulation time 76602169368 ps
CPU time 1773.8 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 01:09:51 PM PST 24
Peak memory 198280 kb
Host smart-54cd1b3e-515c-4597-b1b6-4b3545fabe0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1287983218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.1287983218
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3428430606
Short name T640
Test name
Test status
Simulation time 13683232 ps
CPU time 0.59 seconds
Started Mar 03 12:40:09 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 194212 kb
Host smart-f57eeaac-6aa8-4ed8-b312-a612e8bfb904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428430606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3428430606
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.289660945
Short name T246
Test name
Test status
Simulation time 48960665 ps
CPU time 0.66 seconds
Started Mar 03 12:39:49 PM PST 24
Finished Mar 03 12:39:50 PM PST 24
Peak memory 194060 kb
Host smart-8ba8204f-9e16-4a1a-95cd-4bac9ca1579a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289660945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.289660945
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3540850478
Short name T630
Test name
Test status
Simulation time 723938545 ps
CPU time 24.1 seconds
Started Mar 03 12:39:34 PM PST 24
Finished Mar 03 12:39:59 PM PST 24
Peak memory 196736 kb
Host smart-32110240-0275-4359-bc58-ff23d79bd24e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540850478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3540850478
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1893544642
Short name T461
Test name
Test status
Simulation time 346374179 ps
CPU time 0.87 seconds
Started Mar 03 12:39:34 PM PST 24
Finished Mar 03 12:39:35 PM PST 24
Peak memory 195992 kb
Host smart-687049fd-4239-4790-b2af-98c91056e068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893544642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1893544642
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2233861909
Short name T628
Test name
Test status
Simulation time 77838328 ps
CPU time 0.91 seconds
Started Mar 03 12:39:36 PM PST 24
Finished Mar 03 12:39:37 PM PST 24
Peak memory 197392 kb
Host smart-6ba415a6-63a2-4df5-ab10-f0ded21d3b70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233861909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2233861909
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2458707061
Short name T376
Test name
Test status
Simulation time 258815152 ps
CPU time 2.91 seconds
Started Mar 03 12:40:07 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 198048 kb
Host smart-958b2a7a-26f8-4da2-a4b3-7f7e9b15e38c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458707061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2458707061
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.4136282436
Short name T219
Test name
Test status
Simulation time 351393964 ps
CPU time 1.85 seconds
Started Mar 03 12:39:46 PM PST 24
Finished Mar 03 12:39:48 PM PST 24
Peak memory 196836 kb
Host smart-06b34b10-7397-4656-a1d9-81b3174cc645
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136282436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.4136282436
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.4090441826
Short name T100
Test name
Test status
Simulation time 76479589 ps
CPU time 1.3 seconds
Started Mar 03 12:40:10 PM PST 24
Finished Mar 03 12:40:12 PM PST 24
Peak memory 198016 kb
Host smart-5b106cad-4700-4f51-997b-0893eac54c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090441826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.4090441826
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3629343700
Short name T460
Test name
Test status
Simulation time 58058591 ps
CPU time 1.2 seconds
Started Mar 03 12:39:52 PM PST 24
Finished Mar 03 12:39:54 PM PST 24
Peak memory 196840 kb
Host smart-f5ee0e6f-b598-4884-8a65-f911d8fac22f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629343700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3629343700
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1777922343
Short name T173
Test name
Test status
Simulation time 873613016 ps
CPU time 2.13 seconds
Started Mar 03 12:39:57 PM PST 24
Finished Mar 03 12:40:00 PM PST 24
Peak memory 197776 kb
Host smart-74d01bec-abbb-48ca-925b-c423b92953e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777922343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1777922343
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1134983309
Short name T190
Test name
Test status
Simulation time 111419993 ps
CPU time 1.55 seconds
Started Mar 03 12:39:30 PM PST 24
Finished Mar 03 12:39:32 PM PST 24
Peak memory 196880 kb
Host smart-99475adc-8016-431f-99d3-c7827dcddb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134983309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1134983309
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2531172139
Short name T286
Test name
Test status
Simulation time 409068668 ps
CPU time 1.38 seconds
Started Mar 03 12:39:33 PM PST 24
Finished Mar 03 12:39:35 PM PST 24
Peak memory 196744 kb
Host smart-9df71e60-7d85-4d0e-b540-ba35de93ce4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531172139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2531172139
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.487835098
Short name T432
Test name
Test status
Simulation time 6691980544 ps
CPU time 185.03 seconds
Started Mar 03 12:39:38 PM PST 24
Finished Mar 03 12:42:43 PM PST 24
Peak memory 198332 kb
Host smart-56a2ad46-d712-4412-8e4d-61e15bb09d9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487835098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.487835098
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.3174753729
Short name T661
Test name
Test status
Simulation time 203996937219 ps
CPU time 1119.43 seconds
Started Mar 03 12:40:00 PM PST 24
Finished Mar 03 12:58:40 PM PST 24
Peak memory 198400 kb
Host smart-3264fa7f-46c7-427b-b656-1ec45fcf9a22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3174753729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.3174753729
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2911040677
Short name T268
Test name
Test status
Simulation time 12509907 ps
CPU time 0.57 seconds
Started Mar 03 12:39:49 PM PST 24
Finished Mar 03 12:39:49 PM PST 24
Peak memory 194032 kb
Host smart-6b797dc3-1d5c-480f-a1ea-dd82a9a96654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911040677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2911040677
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2806232382
Short name T251
Test name
Test status
Simulation time 41744155 ps
CPU time 0.83 seconds
Started Mar 03 12:39:46 PM PST 24
Finished Mar 03 12:39:47 PM PST 24
Peak memory 195436 kb
Host smart-e831b400-4061-473e-9ad8-56820ec88da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806232382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2806232382
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3242781942
Short name T488
Test name
Test status
Simulation time 768154301 ps
CPU time 6.95 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:39 PM PST 24
Peak memory 196336 kb
Host smart-52610d04-5033-4390-9e5a-7334ba26a8a1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242781942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3242781942
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2665380953
Short name T499
Test name
Test status
Simulation time 207524724 ps
CPU time 0.87 seconds
Started Mar 03 12:39:36 PM PST 24
Finished Mar 03 12:39:37 PM PST 24
Peak memory 197248 kb
Host smart-0e60cc09-d0cc-4e87-aa89-14cc5e3ecdf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665380953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2665380953
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1615499504
Short name T53
Test name
Test status
Simulation time 42077182 ps
CPU time 1.14 seconds
Started Mar 03 12:39:51 PM PST 24
Finished Mar 03 12:39:52 PM PST 24
Peak memory 196188 kb
Host smart-326574ac-7bd9-4191-b4ec-f79f68ad40d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615499504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1615499504
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1260522052
Short name T545
Test name
Test status
Simulation time 448235885 ps
CPU time 3.69 seconds
Started Mar 03 12:39:35 PM PST 24
Finished Mar 03 12:39:39 PM PST 24
Peak memory 198040 kb
Host smart-6b4d4583-96f6-4b8e-a19a-efe227a21777
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260522052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1260522052
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1128476389
Short name T608
Test name
Test status
Simulation time 156825797 ps
CPU time 2.82 seconds
Started Mar 03 12:39:29 PM PST 24
Finished Mar 03 12:39:32 PM PST 24
Peak memory 196944 kb
Host smart-51efec10-91b8-4d5d-8925-73f132e8190b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128476389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1128476389
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3326484382
Short name T511
Test name
Test status
Simulation time 78678434 ps
CPU time 1.31 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:04 PM PST 24
Peak memory 197020 kb
Host smart-1867a085-5595-4ca4-b949-75be4f1f4dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326484382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3326484382
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1272402991
Short name T189
Test name
Test status
Simulation time 78280457 ps
CPU time 1.03 seconds
Started Mar 03 12:39:43 PM PST 24
Finished Mar 03 12:39:50 PM PST 24
Peak memory 195868 kb
Host smart-16c5a65e-6469-476d-9f63-8931d414b4f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272402991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1272402991
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3498134635
Short name T420
Test name
Test status
Simulation time 1509922195 ps
CPU time 6.69 seconds
Started Mar 03 12:39:46 PM PST 24
Finished Mar 03 12:39:54 PM PST 24
Peak memory 198052 kb
Host smart-ab0dfba3-3035-4583-b6f9-a5633b1b31c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498134635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3498134635
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3555496928
Short name T133
Test name
Test status
Simulation time 29398854 ps
CPU time 0.87 seconds
Started Mar 03 12:39:32 PM PST 24
Finished Mar 03 12:39:33 PM PST 24
Peak memory 196308 kb
Host smart-49212ce3-c0fc-4da5-9e6c-4b84145f55e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555496928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3555496928
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3653850711
Short name T96
Test name
Test status
Simulation time 56200162 ps
CPU time 1.03 seconds
Started Mar 03 12:39:49 PM PST 24
Finished Mar 03 12:39:51 PM PST 24
Peak memory 195736 kb
Host smart-76008dbf-b687-4fc4-b87b-99d7e3adba8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653850711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3653850711
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.180266931
Short name T159
Test name
Test status
Simulation time 15783965638 ps
CPU time 68.56 seconds
Started Mar 03 12:39:33 PM PST 24
Finished Mar 03 12:40:42 PM PST 24
Peak memory 198256 kb
Host smart-1feed864-a20f-4f2e-8327-601305d8d3f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180266931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.180266931
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.3065255276
Short name T7
Test name
Test status
Simulation time 24807867146 ps
CPU time 369.95 seconds
Started Mar 03 12:39:44 PM PST 24
Finished Mar 03 12:45:54 PM PST 24
Peak memory 198344 kb
Host smart-a35ef1e7-524a-4fc1-8637-ca48c28eec12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3065255276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.3065255276
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.535603587
Short name T531
Test name
Test status
Simulation time 29474970 ps
CPU time 0.56 seconds
Started Mar 03 12:39:48 PM PST 24
Finished Mar 03 12:39:49 PM PST 24
Peak memory 194708 kb
Host smart-68f5ec5a-3b48-4031-af59-4cd4cd5659d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535603587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.535603587
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.359429064
Short name T575
Test name
Test status
Simulation time 104502794 ps
CPU time 0.88 seconds
Started Mar 03 12:39:58 PM PST 24
Finished Mar 03 12:39:59 PM PST 24
Peak memory 195900 kb
Host smart-8ad183c4-603e-4a42-91e8-0e234ee83176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359429064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.359429064
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3358929313
Short name T386
Test name
Test status
Simulation time 601109637 ps
CPU time 8.72 seconds
Started Mar 03 12:39:49 PM PST 24
Finished Mar 03 12:40:03 PM PST 24
Peak memory 197000 kb
Host smart-5afae48d-acde-4524-bc9f-8946f119cb63
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358929313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3358929313
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3933619150
Short name T647
Test name
Test status
Simulation time 63980040 ps
CPU time 0.69 seconds
Started Mar 03 12:40:01 PM PST 24
Finished Mar 03 12:40:07 PM PST 24
Peak memory 195364 kb
Host smart-e08af1cc-1e29-4f4f-ae0f-d58842562d07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933619150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3933619150
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1622281561
Short name T507
Test name
Test status
Simulation time 143371832 ps
CPU time 1.05 seconds
Started Mar 03 12:39:42 PM PST 24
Finished Mar 03 12:39:43 PM PST 24
Peak memory 196116 kb
Host smart-6717820f-366f-4b00-ac93-777971f4da80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622281561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1622281561
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1506210141
Short name T165
Test name
Test status
Simulation time 29157322 ps
CPU time 1.19 seconds
Started Mar 03 12:39:31 PM PST 24
Finished Mar 03 12:39:33 PM PST 24
Peak memory 198084 kb
Host smart-781f9ad7-7f2d-4319-8cc6-7c15274ab7af
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506210141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1506210141
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.819738564
Short name T680
Test name
Test status
Simulation time 43661157 ps
CPU time 1.41 seconds
Started Mar 03 12:39:43 PM PST 24
Finished Mar 03 12:39:45 PM PST 24
Peak memory 195884 kb
Host smart-1acb8311-a218-4a08-9247-10ed7c1373c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819738564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
819738564
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1024775161
Short name T180
Test name
Test status
Simulation time 59079396 ps
CPU time 1.25 seconds
Started Mar 03 12:39:53 PM PST 24
Finished Mar 03 12:39:55 PM PST 24
Peak memory 197048 kb
Host smart-83f5988e-b94d-4237-bae0-762642448209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024775161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1024775161
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.310650494
Short name T303
Test name
Test status
Simulation time 270238070 ps
CPU time 0.79 seconds
Started Mar 03 12:39:44 PM PST 24
Finished Mar 03 12:39:45 PM PST 24
Peak memory 196176 kb
Host smart-16ccfaf0-0e38-465f-b29f-c6a2bb31e9b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310650494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.310650494
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2598727664
Short name T241
Test name
Test status
Simulation time 611482951 ps
CPU time 5.23 seconds
Started Mar 03 12:39:42 PM PST 24
Finished Mar 03 12:39:48 PM PST 24
Peak memory 197848 kb
Host smart-de60496a-1bf0-43a9-bc35-9aa8b921fdc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598727664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2598727664
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1319950311
Short name T424
Test name
Test status
Simulation time 46946784 ps
CPU time 0.81 seconds
Started Mar 03 12:39:42 PM PST 24
Finished Mar 03 12:39:43 PM PST 24
Peak memory 195412 kb
Host smart-2b6440dd-fddc-42a5-9c1f-d4497f2d4778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319950311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1319950311
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.17489582
Short name T558
Test name
Test status
Simulation time 786443333 ps
CPU time 1.01 seconds
Started Mar 03 12:39:46 PM PST 24
Finished Mar 03 12:39:47 PM PST 24
Peak memory 195812 kb
Host smart-6cef82fd-e11b-4eb4-9510-aa77a774a0e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17489582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.17489582
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1691601005
Short name T279
Test name
Test status
Simulation time 6456987306 ps
CPU time 42.99 seconds
Started Mar 03 12:39:54 PM PST 24
Finished Mar 03 12:40:37 PM PST 24
Peak memory 198256 kb
Host smart-58fca294-196b-4863-abdd-8a31aa80cff6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691601005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1691601005
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.4229471107
Short name T623
Test name
Test status
Simulation time 24137200 ps
CPU time 0.58 seconds
Started Mar 03 12:39:56 PM PST 24
Finished Mar 03 12:39:57 PM PST 24
Peak memory 194180 kb
Host smart-a9589835-eea5-4cc3-bb83-cf6e0bd174b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229471107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.4229471107
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.443166685
Short name T663
Test name
Test status
Simulation time 26165971 ps
CPU time 0.71 seconds
Started Mar 03 12:39:45 PM PST 24
Finished Mar 03 12:39:46 PM PST 24
Peak memory 195160 kb
Host smart-c616fb43-3d86-4f5c-9da9-9d8b3346bd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443166685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.443166685
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.268373162
Short name T564
Test name
Test status
Simulation time 710932825 ps
CPU time 6.51 seconds
Started Mar 03 12:39:47 PM PST 24
Finished Mar 03 12:39:54 PM PST 24
Peak memory 197052 kb
Host smart-0d2d8a01-c263-48cf-a1dd-6ad83034c9bc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268373162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.268373162
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3974948634
Short name T567
Test name
Test status
Simulation time 93499640 ps
CPU time 0.93 seconds
Started Mar 03 12:39:47 PM PST 24
Finished Mar 03 12:39:48 PM PST 24
Peak memory 197840 kb
Host smart-6fa9950c-eb13-40d3-b087-41faedeebd10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974948634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3974948634
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2451196277
Short name T324
Test name
Test status
Simulation time 19753885 ps
CPU time 0.83 seconds
Started Mar 03 12:40:15 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 196252 kb
Host smart-6fd06398-0adb-4c4c-aaef-f294154d6984
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451196277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2451196277
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1770232768
Short name T498
Test name
Test status
Simulation time 208282332 ps
CPU time 1.69 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:22 PM PST 24
Peak memory 198128 kb
Host smart-a9387137-06b8-46d9-b776-ec849204ae40
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770232768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1770232768
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3020683486
Short name T691
Test name
Test status
Simulation time 102205852 ps
CPU time 2.01 seconds
Started Mar 03 12:39:48 PM PST 24
Finished Mar 03 12:39:51 PM PST 24
Peak memory 196324 kb
Host smart-0eb7c0e6-ab68-4067-9aaf-11f95753c4c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020683486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3020683486
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2740019724
Short name T229
Test name
Test status
Simulation time 120204095 ps
CPU time 1.23 seconds
Started Mar 03 12:39:41 PM PST 24
Finished Mar 03 12:39:42 PM PST 24
Peak memory 198148 kb
Host smart-5a42dbce-e1b5-40b8-8287-de0a9385046a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740019724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2740019724
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3481537567
Short name T502
Test name
Test status
Simulation time 17739489 ps
CPU time 0.75 seconds
Started Mar 03 12:39:42 PM PST 24
Finished Mar 03 12:39:49 PM PST 24
Peak memory 195424 kb
Host smart-2a90e756-51cf-4647-9976-92099593ed9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481537567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3481537567
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1194410580
Short name T230
Test name
Test status
Simulation time 230069453 ps
CPU time 5.09 seconds
Started Mar 03 12:39:43 PM PST 24
Finished Mar 03 12:39:49 PM PST 24
Peak memory 197996 kb
Host smart-5e28bb68-4fd2-4164-b7d0-0328a194ded3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194410580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1194410580
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2182218059
Short name T321
Test name
Test status
Simulation time 291408766 ps
CPU time 1.03 seconds
Started Mar 03 12:39:38 PM PST 24
Finished Mar 03 12:39:39 PM PST 24
Peak memory 195728 kb
Host smart-3d40fa35-6c06-493b-8654-3802191a5549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182218059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2182218059
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1410253880
Short name T714
Test name
Test status
Simulation time 327061790 ps
CPU time 1.15 seconds
Started Mar 03 12:39:27 PM PST 24
Finished Mar 03 12:39:28 PM PST 24
Peak memory 195676 kb
Host smart-a060bc7e-79df-4cb2-8d6e-3bd0e9311352
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410253880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1410253880
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3966850280
Short name T102
Test name
Test status
Simulation time 4538814586 ps
CPU time 28.57 seconds
Started Mar 03 12:39:34 PM PST 24
Finished Mar 03 12:40:03 PM PST 24
Peak memory 198488 kb
Host smart-3e7564e8-a8c4-49ab-a37f-1d328ab9b087
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966850280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3966850280
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.553816579
Short name T687
Test name
Test status
Simulation time 389479123607 ps
CPU time 2385.04 seconds
Started Mar 03 12:40:00 PM PST 24
Finished Mar 03 01:19:46 PM PST 24
Peak memory 198464 kb
Host smart-b5b39aef-0a2b-4a88-87a0-b2cd81e3d00c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=553816579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.553816579
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2735356286
Short name T226
Test name
Test status
Simulation time 81693506 ps
CPU time 0.55 seconds
Started Mar 03 12:39:57 PM PST 24
Finished Mar 03 12:39:58 PM PST 24
Peak memory 194696 kb
Host smart-60568c48-e26a-4148-840e-9b578ab86c48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735356286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2735356286
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3290099033
Short name T206
Test name
Test status
Simulation time 17511690 ps
CPU time 0.6 seconds
Started Mar 03 12:39:42 PM PST 24
Finished Mar 03 12:39:43 PM PST 24
Peak memory 194604 kb
Host smart-80c1cd33-25ee-47d2-91a1-c6cb7faeee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290099033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3290099033
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.714505162
Short name T108
Test name
Test status
Simulation time 2304102299 ps
CPU time 18.14 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 197020 kb
Host smart-b44a46fc-5c29-4d7e-a33c-56251f53cab8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714505162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.714505162
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.30297766
Short name T450
Test name
Test status
Simulation time 340268016 ps
CPU time 1.04 seconds
Started Mar 03 12:39:59 PM PST 24
Finished Mar 03 12:40:00 PM PST 24
Peak memory 197876 kb
Host smart-b893f052-c3f3-4f89-b70d-70e62b3edc0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30297766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.30297766
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2625683205
Short name T214
Test name
Test status
Simulation time 28017367 ps
CPU time 0.68 seconds
Started Mar 03 12:39:57 PM PST 24
Finished Mar 03 12:39:57 PM PST 24
Peak memory 194216 kb
Host smart-f1a5508a-ef4e-4a6d-a05b-a0500a941b7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625683205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2625683205
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2773282497
Short name T645
Test name
Test status
Simulation time 71822129 ps
CPU time 1.64 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:03 PM PST 24
Peak memory 196728 kb
Host smart-ee5df1ff-97ef-41ad-9b02-fb5eee0085cf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773282497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2773282497
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1608269247
Short name T492
Test name
Test status
Simulation time 108700514 ps
CPU time 2.41 seconds
Started Mar 03 12:39:51 PM PST 24
Finished Mar 03 12:39:54 PM PST 24
Peak memory 196548 kb
Host smart-3c1cd9f6-e1fb-4460-b65b-6b1bb8f7129c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608269247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1608269247
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1913467365
Short name T232
Test name
Test status
Simulation time 25654442 ps
CPU time 0.68 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:03 PM PST 24
Peak memory 194308 kb
Host smart-462a0996-c3a7-4bed-94ce-a37bf3f2ea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913467365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1913467365
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3030884203
Short name T312
Test name
Test status
Simulation time 277091746 ps
CPU time 1.25 seconds
Started Mar 03 12:39:46 PM PST 24
Finished Mar 03 12:39:47 PM PST 24
Peak memory 198100 kb
Host smart-a08c1761-b7b2-4089-90e6-f3a5ce2b7510
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030884203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3030884203
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1188106491
Short name T284
Test name
Test status
Simulation time 23827759 ps
CPU time 1.02 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:22 PM PST 24
Peak memory 196444 kb
Host smart-4e1718bc-1934-4f6f-97f9-aca0c3f685a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188106491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1188106491
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3321250986
Short name T395
Test name
Test status
Simulation time 303191024 ps
CPU time 1.3 seconds
Started Mar 03 12:40:01 PM PST 24
Finished Mar 03 12:40:03 PM PST 24
Peak memory 195752 kb
Host smart-d7e85d9f-1095-4485-92c1-22c60e0cf35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321250986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3321250986
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2901126209
Short name T14
Test name
Test status
Simulation time 394837622 ps
CPU time 1.02 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:04 PM PST 24
Peak memory 195788 kb
Host smart-ca80f53e-b330-403d-a68b-85c4971087d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901126209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2901126209
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1745640464
Short name T115
Test name
Test status
Simulation time 1921075447 ps
CPU time 42.6 seconds
Started Mar 03 12:39:57 PM PST 24
Finished Mar 03 12:40:40 PM PST 24
Peak memory 198096 kb
Host smart-0798ffbd-3e1a-4e94-bd87-9e9b04463c68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745640464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1745640464
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.922825374
Short name T525
Test name
Test status
Simulation time 90227447045 ps
CPU time 1389.86 seconds
Started Mar 03 12:39:44 PM PST 24
Finished Mar 03 01:02:55 PM PST 24
Peak memory 198392 kb
Host smart-ce5c8898-476b-4af7-9d64-4891a95d8cde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=922825374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.922825374
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1709823152
Short name T433
Test name
Test status
Simulation time 41502624 ps
CPU time 0.6 seconds
Started Mar 03 12:39:53 PM PST 24
Finished Mar 03 12:39:54 PM PST 24
Peak memory 194092 kb
Host smart-ee82f236-0350-461d-8360-29733f6022b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709823152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1709823152
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2742147059
Short name T500
Test name
Test status
Simulation time 212288187 ps
CPU time 0.67 seconds
Started Mar 03 12:40:01 PM PST 24
Finished Mar 03 12:40:01 PM PST 24
Peak memory 194048 kb
Host smart-d9586550-c073-4c7b-9ce1-0dd9c5bc0a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742147059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2742147059
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1520794934
Short name T512
Test name
Test status
Simulation time 1370805014 ps
CPU time 24.56 seconds
Started Mar 03 12:39:35 PM PST 24
Finished Mar 03 12:39:59 PM PST 24
Peak memory 198080 kb
Host smart-06733558-35dd-49b9-9f43-1e43529909cf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520794934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1520794934
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.732755329
Short name T158
Test name
Test status
Simulation time 208055633 ps
CPU time 0.9 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:08 PM PST 24
Peak memory 197732 kb
Host smart-e4545fbd-4134-4c33-80ed-34d7b3e13672
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732755329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.732755329
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2738495103
Short name T712
Test name
Test status
Simulation time 194543489 ps
CPU time 0.89 seconds
Started Mar 03 12:39:34 PM PST 24
Finished Mar 03 12:39:36 PM PST 24
Peak memory 195892 kb
Host smart-992839ea-bd9b-4594-a4c1-d7c4d996ede9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738495103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2738495103
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.824070655
Short name T202
Test name
Test status
Simulation time 65143968 ps
CPU time 2.6 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 198048 kb
Host smart-23519572-3e86-4b8b-9afd-5d4ab5551ad4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824070655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.824070655
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.371458849
Short name T574
Test name
Test status
Simulation time 100168318 ps
CPU time 1.6 seconds
Started Mar 03 12:40:05 PM PST 24
Finished Mar 03 12:40:07 PM PST 24
Peak memory 196220 kb
Host smart-2ba2b92b-eb6a-48da-be43-4d080fd232e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371458849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
371458849
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2703548533
Short name T520
Test name
Test status
Simulation time 50529625 ps
CPU time 1.18 seconds
Started Mar 03 12:39:51 PM PST 24
Finished Mar 03 12:39:52 PM PST 24
Peak memory 198084 kb
Host smart-51753122-d5e0-442b-bda7-89f04ac5eca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703548533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2703548533
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.4039394365
Short name T693
Test name
Test status
Simulation time 95960906 ps
CPU time 0.73 seconds
Started Mar 03 12:39:38 PM PST 24
Finished Mar 03 12:39:39 PM PST 24
Peak memory 195520 kb
Host smart-fe40963f-4c8f-4675-abe4-b80cc6b1327d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039394365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.4039394365
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3699871583
Short name T355
Test name
Test status
Simulation time 79023118 ps
CPU time 1.98 seconds
Started Mar 03 12:39:45 PM PST 24
Finished Mar 03 12:39:47 PM PST 24
Peak memory 198000 kb
Host smart-a9c32f8a-4ef4-44b5-9d5c-6680fe050480
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699871583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3699871583
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.372603674
Short name T339
Test name
Test status
Simulation time 150332422 ps
CPU time 1.24 seconds
Started Mar 03 12:39:40 PM PST 24
Finished Mar 03 12:39:42 PM PST 24
Peak memory 198084 kb
Host smart-6d9f86c5-45f9-41d3-b40b-743467bc4803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372603674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.372603674
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3805727698
Short name T689
Test name
Test status
Simulation time 373535123 ps
CPU time 1.07 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:03 PM PST 24
Peak memory 196624 kb
Host smart-56a53cfd-235f-4bc3-ac2e-67df8bb3eb5a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805727698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3805727698
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3026993802
Short name T128
Test name
Test status
Simulation time 2972357223 ps
CPU time 75.15 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:41:22 PM PST 24
Peak memory 198280 kb
Host smart-958ad01e-2c64-4e9b-af9f-cd3f87ec5ac4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026993802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3026993802
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.1732026055
Short name T55
Test name
Test status
Simulation time 112536677792 ps
CPU time 829.5 seconds
Started Mar 03 12:40:18 PM PST 24
Finished Mar 03 12:54:08 PM PST 24
Peak memory 198388 kb
Host smart-19bcc7bb-9329-4fda-9e91-16caf8eb4b95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1732026055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.1732026055
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3597085776
Short name T698
Test name
Test status
Simulation time 17642025 ps
CPU time 0.64 seconds
Started Mar 03 12:40:05 PM PST 24
Finished Mar 03 12:40:06 PM PST 24
Peak memory 194200 kb
Host smart-1f33b2bd-89b3-47ff-9b52-e96fd86ce056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597085776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3597085776
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1554498953
Short name T681
Test name
Test status
Simulation time 148733323 ps
CPU time 0.83 seconds
Started Mar 03 12:39:55 PM PST 24
Finished Mar 03 12:39:56 PM PST 24
Peak memory 195416 kb
Host smart-fc2d2e11-907f-460e-b527-290e979c921b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554498953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1554498953
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3337944902
Short name T654
Test name
Test status
Simulation time 391412967 ps
CPU time 18.95 seconds
Started Mar 03 12:39:55 PM PST 24
Finished Mar 03 12:40:14 PM PST 24
Peak memory 198084 kb
Host smart-6a80e248-33b2-46ba-babc-31e6ed9a7d35
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337944902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3337944902
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1371300503
Short name T371
Test name
Test status
Simulation time 70319583 ps
CPU time 0.88 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 196004 kb
Host smart-f1da73a9-32ab-456c-8cc8-c90ceb4808bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371300503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1371300503
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.4097786976
Short name T245
Test name
Test status
Simulation time 46310819 ps
CPU time 0.92 seconds
Started Mar 03 12:39:57 PM PST 24
Finished Mar 03 12:39:58 PM PST 24
Peak memory 196896 kb
Host smart-f54516a5-2f38-4191-9a52-91af8ba890d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097786976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.4097786976
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1503756956
Short name T141
Test name
Test status
Simulation time 309257946 ps
CPU time 2.99 seconds
Started Mar 03 12:39:57 PM PST 24
Finished Mar 03 12:40:01 PM PST 24
Peak memory 198144 kb
Host smart-90806db0-7c86-4951-91e7-6c1423e46eb2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503756956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1503756956
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2946662385
Short name T683
Test name
Test status
Simulation time 83824720 ps
CPU time 1.25 seconds
Started Mar 03 12:40:10 PM PST 24
Finished Mar 03 12:40:12 PM PST 24
Peak memory 196400 kb
Host smart-4f769962-73dd-4a37-9513-e5eddd83cde7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946662385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2946662385
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2550668766
Short name T596
Test name
Test status
Simulation time 221459874 ps
CPU time 1.31 seconds
Started Mar 03 12:39:47 PM PST 24
Finished Mar 03 12:39:49 PM PST 24
Peak memory 197172 kb
Host smart-efe23575-f57f-41a0-8e89-4a9d63bcc8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550668766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2550668766
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2463835723
Short name T614
Test name
Test status
Simulation time 68757317 ps
CPU time 0.87 seconds
Started Mar 03 12:40:10 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 196636 kb
Host smart-b26536b3-1b4d-47af-8a1f-05ae234d85cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463835723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2463835723
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.232662510
Short name T8
Test name
Test status
Simulation time 2489707966 ps
CPU time 5.1 seconds
Started Mar 03 12:40:15 PM PST 24
Finished Mar 03 12:40:22 PM PST 24
Peak memory 198192 kb
Host smart-e2c57b07-8540-446f-b9ea-838005347a38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232662510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.232662510
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.563475177
Short name T283
Test name
Test status
Simulation time 30449203 ps
CPU time 0.95 seconds
Started Mar 03 12:39:53 PM PST 24
Finished Mar 03 12:39:54 PM PST 24
Peak memory 195576 kb
Host smart-310b63c1-664c-44cc-8680-d26abf6ed15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563475177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.563475177
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1737034363
Short name T125
Test name
Test status
Simulation time 67425020 ps
CPU time 0.87 seconds
Started Mar 03 12:39:37 PM PST 24
Finished Mar 03 12:39:38 PM PST 24
Peak memory 196988 kb
Host smart-f4b63303-a979-461c-9c2a-3adeba0da623
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737034363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1737034363
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2818961276
Short name T475
Test name
Test status
Simulation time 7355975706 ps
CPU time 179.61 seconds
Started Mar 03 12:40:05 PM PST 24
Finished Mar 03 12:43:06 PM PST 24
Peak memory 198204 kb
Host smart-31025398-be54-45af-8ba2-6ce7fdd43a2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818961276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2818961276
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2378937549
Short name T448
Test name
Test status
Simulation time 63611347 ps
CPU time 0.55 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:21 PM PST 24
Peak memory 194016 kb
Host smart-d46104e2-ee37-4d2b-8de8-14f3669473cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378937549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2378937549
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3964049764
Short name T617
Test name
Test status
Simulation time 25167401 ps
CPU time 0.66 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:03 PM PST 24
Peak memory 193996 kb
Host smart-8fb179c2-6abf-417b-9649-8b9ca35a0ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964049764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3964049764
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3567727430
Short name T188
Test name
Test status
Simulation time 3885625684 ps
CPU time 27.95 seconds
Started Mar 03 12:40:14 PM PST 24
Finished Mar 03 12:40:44 PM PST 24
Peak memory 196720 kb
Host smart-25d67aca-358f-4170-874e-288b0f3017ae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567727430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3567727430
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3487700162
Short name T320
Test name
Test status
Simulation time 243444188 ps
CPU time 0.91 seconds
Started Mar 03 12:40:19 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 195880 kb
Host smart-cb749685-ccfa-466f-9e6e-977202d96d55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487700162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3487700162
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3690078139
Short name T469
Test name
Test status
Simulation time 87674410 ps
CPU time 1.27 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:04 PM PST 24
Peak memory 196180 kb
Host smart-d3c14af4-5186-4983-b259-c49bcb729baa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690078139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3690078139
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2879879249
Short name T298
Test name
Test status
Simulation time 676133789 ps
CPU time 3.33 seconds
Started Mar 03 12:39:48 PM PST 24
Finished Mar 03 12:39:52 PM PST 24
Peak memory 198100 kb
Host smart-fb5f5de4-1f83-4e3a-9cbe-9c4a11983831
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879879249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2879879249
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3759780453
Short name T199
Test name
Test status
Simulation time 526839266 ps
CPU time 2.08 seconds
Started Mar 03 12:40:18 PM PST 24
Finished Mar 03 12:40:21 PM PST 24
Peak memory 195728 kb
Host smart-e56e505f-4d7d-4194-96a2-acd6d0cb8e39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759780453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3759780453
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.734364130
Short name T594
Test name
Test status
Simulation time 57950422 ps
CPU time 0.71 seconds
Started Mar 03 12:40:03 PM PST 24
Finished Mar 03 12:40:10 PM PST 24
Peak memory 195388 kb
Host smart-6c9dae68-e025-41a3-ae8d-f94dc07d51ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734364130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.734364130
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3935182883
Short name T667
Test name
Test status
Simulation time 38647220 ps
CPU time 1.07 seconds
Started Mar 03 12:40:03 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 196080 kb
Host smart-f99df873-fa64-4a8e-a25f-0fdeb1400e85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935182883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.3935182883
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_smoke.3736053331
Short name T328
Test name
Test status
Simulation time 254337571 ps
CPU time 1.22 seconds
Started Mar 03 12:40:03 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 195832 kb
Host smart-0117572c-9296-4d10-b487-3e454d05a47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736053331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3736053331
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2619227242
Short name T274
Test name
Test status
Simulation time 176979389 ps
CPU time 1.2 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:26 PM PST 24
Peak memory 196516 kb
Host smart-6b738692-c497-43e6-b6c6-74dbbf8906e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619227242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2619227242
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3700898898
Short name T671
Test name
Test status
Simulation time 2815161903 ps
CPU time 39.73 seconds
Started Mar 03 12:39:52 PM PST 24
Finished Mar 03 12:40:32 PM PST 24
Peak memory 198188 kb
Host smart-4e69baec-d676-4f6a-8406-e262ac2ba165
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700898898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3700898898
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1460958030
Short name T437
Test name
Test status
Simulation time 28361302 ps
CPU time 0.59 seconds
Started Mar 03 12:40:17 PM PST 24
Finished Mar 03 12:40:19 PM PST 24
Peak memory 192740 kb
Host smart-37120a6c-cf27-4fab-bfe5-55c04ed741f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460958030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1460958030
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3934489605
Short name T227
Test name
Test status
Simulation time 42163803 ps
CPU time 0.82 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 195152 kb
Host smart-28fd99a9-c06f-4fa2-a0ca-15c45ce002d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934489605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3934489605
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.1535916477
Short name T664
Test name
Test status
Simulation time 732941715 ps
CPU time 22.19 seconds
Started Mar 03 12:39:57 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 198164 kb
Host smart-2f6b62ba-0a2c-4718-a56e-2e211a13af65
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535916477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.1535916477
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3626941773
Short name T109
Test name
Test status
Simulation time 109435323 ps
CPU time 0.85 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:08 PM PST 24
Peak memory 196040 kb
Host smart-fe3e89f3-9824-4f12-80e4-261415adc56e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626941773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3626941773
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2919209418
Short name T557
Test name
Test status
Simulation time 211223266 ps
CPU time 0.97 seconds
Started Mar 03 12:40:03 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 196940 kb
Host smart-55c5bf69-7273-480e-8f20-1c4737d8eedc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919209418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2919209418
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.311898000
Short name T179
Test name
Test status
Simulation time 79978735 ps
CPU time 3.24 seconds
Started Mar 03 12:39:56 PM PST 24
Finished Mar 03 12:39:59 PM PST 24
Peak memory 198264 kb
Host smart-372117a4-eb55-46a0-8a5a-c1f53f5968c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311898000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.311898000
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.4019076646
Short name T300
Test name
Test status
Simulation time 101908435 ps
CPU time 2.01 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:19 PM PST 24
Peak memory 196224 kb
Host smart-570c998b-60ef-4ef2-ba7f-87ea2337c6e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019076646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.4019076646
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.4024337371
Short name T708
Test name
Test status
Simulation time 35096880 ps
CPU time 1.01 seconds
Started Mar 03 12:40:03 PM PST 24
Finished Mar 03 12:40:04 PM PST 24
Peak memory 195896 kb
Host smart-82ec2b84-25c7-4b90-92d8-2e059111de93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024337371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.4024337371
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1203538394
Short name T183
Test name
Test status
Simulation time 41898884 ps
CPU time 0.62 seconds
Started Mar 03 12:40:00 PM PST 24
Finished Mar 03 12:40:01 PM PST 24
Peak memory 194344 kb
Host smart-02b6c090-dec2-4002-881e-0d3e327930f5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203538394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1203538394
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1217230652
Short name T399
Test name
Test status
Simulation time 723457045 ps
CPU time 2.65 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 198052 kb
Host smart-588601ec-7472-47ba-830c-ba12921acb23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217230652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1217230652
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.346930900
Short name T454
Test name
Test status
Simulation time 183483694 ps
CPU time 1.18 seconds
Started Mar 03 12:39:43 PM PST 24
Finished Mar 03 12:39:45 PM PST 24
Peak memory 195860 kb
Host smart-b79c169c-1e26-482a-bed5-4555fe81dd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346930900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.346930900
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.4169204484
Short name T155
Test name
Test status
Simulation time 35542569 ps
CPU time 0.84 seconds
Started Mar 03 12:40:00 PM PST 24
Finished Mar 03 12:40:01 PM PST 24
Peak memory 195936 kb
Host smart-9cb8cbbe-46b6-4e18-8625-8d53d7c99f93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169204484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.4169204484
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.939644622
Short name T696
Test name
Test status
Simulation time 11833501043 ps
CPU time 60.02 seconds
Started Mar 03 12:40:21 PM PST 24
Finished Mar 03 12:41:21 PM PST 24
Peak memory 198236 kb
Host smart-de85ce26-938f-4cdb-bb3c-febf2ec9780b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939644622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.939644622
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.949338132
Short name T372
Test name
Test status
Simulation time 16353777 ps
CPU time 0.55 seconds
Started Mar 03 12:39:01 PM PST 24
Finished Mar 03 12:39:03 PM PST 24
Peak memory 193952 kb
Host smart-d46ffa53-29ce-4260-a212-bb2f8cc0da83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949338132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.949338132
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1911473760
Short name T181
Test name
Test status
Simulation time 233997721 ps
CPU time 0.77 seconds
Started Mar 03 12:39:02 PM PST 24
Finished Mar 03 12:39:03 PM PST 24
Peak memory 195388 kb
Host smart-90e80af9-e0be-4f12-b80a-368e7bcc38b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911473760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1911473760
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.4214914521
Short name T398
Test name
Test status
Simulation time 267923623 ps
CPU time 13.97 seconds
Started Mar 03 12:39:14 PM PST 24
Finished Mar 03 12:39:32 PM PST 24
Peak memory 197008 kb
Host smart-a741b203-9b10-4db0-8e4e-198a1bf13c61
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214914521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.4214914521
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2696038457
Short name T26
Test name
Test status
Simulation time 351524248 ps
CPU time 0.98 seconds
Started Mar 03 12:39:15 PM PST 24
Finished Mar 03 12:39:21 PM PST 24
Peak memory 197056 kb
Host smart-922078e0-da94-4514-b5b3-dedb6bc92881
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696038457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2696038457
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2156206090
Short name T666
Test name
Test status
Simulation time 456861472 ps
CPU time 1.4 seconds
Started Mar 03 12:39:03 PM PST 24
Finished Mar 03 12:39:04 PM PST 24
Peak memory 196836 kb
Host smart-179e979b-ed68-4188-9e65-027468e229ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156206090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2156206090
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3925068502
Short name T287
Test name
Test status
Simulation time 85916755 ps
CPU time 3.48 seconds
Started Mar 03 12:38:57 PM PST 24
Finished Mar 03 12:39:01 PM PST 24
Peak memory 198160 kb
Host smart-ff9c05c8-d39e-4f17-b78d-7e27b8a5f4c0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925068502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3925068502
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2265442388
Short name T354
Test name
Test status
Simulation time 84180408 ps
CPU time 1.56 seconds
Started Mar 03 12:38:58 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 196896 kb
Host smart-1b6c500c-4958-40fe-b2e3-93a59a9edd27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265442388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2265442388
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1898546104
Short name T193
Test name
Test status
Simulation time 44700803 ps
CPU time 0.8 seconds
Started Mar 03 12:38:59 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 196156 kb
Host smart-05892f29-b440-4f47-9e43-87b8df25ce2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898546104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1898546104
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3058225145
Short name T571
Test name
Test status
Simulation time 115043440 ps
CPU time 0.79 seconds
Started Mar 03 12:38:58 PM PST 24
Finished Mar 03 12:38:59 PM PST 24
Peak memory 195600 kb
Host smart-eb1c6727-61e8-44d6-bf61-cc4750c77965
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058225145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3058225145
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3663260111
Short name T517
Test name
Test status
Simulation time 1873571826 ps
CPU time 5.44 seconds
Started Mar 03 12:38:58 PM PST 24
Finished Mar 03 12:39:04 PM PST 24
Peak memory 197992 kb
Host smart-1626f889-6e2a-4a6a-9338-6cc366b326ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663260111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3663260111
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.3785507095
Short name T46
Test name
Test status
Simulation time 321078801 ps
CPU time 0.9 seconds
Started Mar 03 12:39:06 PM PST 24
Finished Mar 03 12:39:07 PM PST 24
Peak memory 213780 kb
Host smart-6b5892a7-6971-4569-b14f-981a22f54824
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785507095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.3785507095
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3871391995
Short name T368
Test name
Test status
Simulation time 176982707 ps
CPU time 1.34 seconds
Started Mar 03 12:38:58 PM PST 24
Finished Mar 03 12:38:59 PM PST 24
Peak memory 195596 kb
Host smart-c4682e74-e808-4a9e-8eb2-765af03e7341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871391995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3871391995
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2441652863
Short name T496
Test name
Test status
Simulation time 42618293 ps
CPU time 0.86 seconds
Started Mar 03 12:38:57 PM PST 24
Finished Mar 03 12:38:58 PM PST 24
Peak memory 196020 kb
Host smart-8a178794-d6b6-4c0a-8844-cd20613c9d90
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441652863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2441652863
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2128860650
Short name T442
Test name
Test status
Simulation time 66230146209 ps
CPU time 213.67 seconds
Started Mar 03 12:39:03 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 197964 kb
Host smart-7d4a0205-4995-4792-8724-59eed40b142d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128860650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2128860650
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2053571745
Short name T669
Test name
Test status
Simulation time 35556997 ps
CPU time 0.58 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 194012 kb
Host smart-3dad9ef4-6907-41c2-b2ef-18b09e0fb86d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053571745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2053571745
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3250981098
Short name T337
Test name
Test status
Simulation time 40451944 ps
CPU time 0.83 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:07 PM PST 24
Peak memory 195448 kb
Host smart-3072c68f-4d4a-482a-882d-1395fb7cca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250981098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3250981098
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1303294687
Short name T690
Test name
Test status
Simulation time 520037561 ps
CPU time 4.58 seconds
Started Mar 03 12:39:56 PM PST 24
Finished Mar 03 12:40:01 PM PST 24
Peak memory 195576 kb
Host smart-455def59-4ca1-4a8e-b759-fcaa6d0ac6ca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303294687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1303294687
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3368478958
Short name T18
Test name
Test status
Simulation time 36378467 ps
CPU time 0.73 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 195476 kb
Host smart-753c62de-7db0-49c3-ac54-81b593c3a124
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368478958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3368478958
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.581912024
Short name T611
Test name
Test status
Simulation time 109830107 ps
CPU time 1.44 seconds
Started Mar 03 12:39:52 PM PST 24
Finished Mar 03 12:39:53 PM PST 24
Peak memory 197484 kb
Host smart-f38635d1-f1f1-472e-b631-c7cf8a4d96cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581912024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.581912024
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2737584763
Short name T401
Test name
Test status
Simulation time 43639174 ps
CPU time 1.64 seconds
Started Mar 03 12:39:53 PM PST 24
Finished Mar 03 12:39:55 PM PST 24
Peak memory 196672 kb
Host smart-edf03ade-9550-40cf-aa44-4d00162e4cbf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737584763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2737584763
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2987733017
Short name T263
Test name
Test status
Simulation time 190638734 ps
CPU time 3.1 seconds
Started Mar 03 12:39:53 PM PST 24
Finished Mar 03 12:39:56 PM PST 24
Peak memory 195780 kb
Host smart-d3dd9fde-cb76-4360-bac7-fb0f5cc969a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987733017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2987733017
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.456954100
Short name T261
Test name
Test status
Simulation time 16149145 ps
CPU time 0.7 seconds
Started Mar 03 12:40:05 PM PST 24
Finished Mar 03 12:40:06 PM PST 24
Peak memory 195440 kb
Host smart-2268172c-8238-4737-b572-17325cf92f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456954100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.456954100
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2051258175
Short name T474
Test name
Test status
Simulation time 498150061 ps
CPU time 1.26 seconds
Started Mar 03 12:40:05 PM PST 24
Finished Mar 03 12:40:07 PM PST 24
Peak memory 197036 kb
Host smart-0280385c-d0ee-4595-a120-484f071ea35f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051258175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2051258175
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2916818267
Short name T2
Test name
Test status
Simulation time 1908218411 ps
CPU time 5.57 seconds
Started Mar 03 12:40:10 PM PST 24
Finished Mar 03 12:40:17 PM PST 24
Peak memory 197936 kb
Host smart-ee38f0e1-1697-45f4-b7ea-f535a1bfb9af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916818267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2916818267
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1205887525
Short name T349
Test name
Test status
Simulation time 179130410 ps
CPU time 0.99 seconds
Started Mar 03 12:40:11 PM PST 24
Finished Mar 03 12:40:13 PM PST 24
Peak memory 195768 kb
Host smart-67f77b4c-71ff-41c5-a96c-7c2556e9bf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205887525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1205887525
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2615623142
Short name T201
Test name
Test status
Simulation time 59766454 ps
CPU time 1.09 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:29 PM PST 24
Peak memory 195724 kb
Host smart-c24efee1-eb2a-4a77-905d-d1967f016a01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615623142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2615623142
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3900164255
Short name T542
Test name
Test status
Simulation time 6228637948 ps
CPU time 81.73 seconds
Started Mar 03 12:39:51 PM PST 24
Finished Mar 03 12:41:13 PM PST 24
Peak memory 198288 kb
Host smart-6d6399ae-bda5-4fd5-b542-a9b463e61013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900164255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3900164255
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1645220137
Short name T470
Test name
Test status
Simulation time 14399644 ps
CPU time 0.55 seconds
Started Mar 03 12:39:56 PM PST 24
Finished Mar 03 12:39:57 PM PST 24
Peak memory 194212 kb
Host smart-ffb13e99-4255-46c5-b14a-d1fedd214bbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645220137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1645220137
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.891051644
Short name T224
Test name
Test status
Simulation time 25826329 ps
CPU time 0.76 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 194128 kb
Host smart-82705995-6e77-4ab5-aab0-559bf84e8013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891051644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.891051644
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.989045829
Short name T345
Test name
Test status
Simulation time 1882991756 ps
CPU time 18.43 seconds
Started Mar 03 12:40:18 PM PST 24
Finished Mar 03 12:40:37 PM PST 24
Peak memory 196932 kb
Host smart-73f18ce8-d8fb-4aa9-91f0-1e4e74087e29
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989045829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.989045829
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1146895406
Short name T584
Test name
Test status
Simulation time 46141481 ps
CPU time 0.79 seconds
Started Mar 03 12:39:54 PM PST 24
Finished Mar 03 12:39:55 PM PST 24
Peak memory 195912 kb
Host smart-aaa92dda-df64-46ad-bcbb-20aee36677e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146895406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1146895406
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1948924905
Short name T479
Test name
Test status
Simulation time 55111682 ps
CPU time 0.8 seconds
Started Mar 03 12:40:19 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 195436 kb
Host smart-0c5c9532-f068-4608-a654-30fddcf4f29a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948924905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1948924905
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3422017639
Short name T552
Test name
Test status
Simulation time 382543499 ps
CPU time 3.63 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:27 PM PST 24
Peak memory 198108 kb
Host smart-76639c1f-716b-4bd4-86dc-7c66faba3816
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422017639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3422017639
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.155925160
Short name T340
Test name
Test status
Simulation time 575165652 ps
CPU time 3.42 seconds
Started Mar 03 12:39:59 PM PST 24
Finished Mar 03 12:40:02 PM PST 24
Peak memory 197496 kb
Host smart-1a2c552f-3015-4f51-ae77-2f1373b4d1c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155925160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
155925160
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1307367625
Short name T566
Test name
Test status
Simulation time 103995446 ps
CPU time 1.06 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 196828 kb
Host smart-8c6d65bc-a965-4c4e-b94a-75532a62e5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307367625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1307367625
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2723133504
Short name T701
Test name
Test status
Simulation time 93088072 ps
CPU time 1.15 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:04 PM PST 24
Peak memory 196776 kb
Host smart-701eb39b-cfba-4d64-b717-d6b2a11e4a2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723133504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2723133504
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2176260535
Short name T333
Test name
Test status
Simulation time 352625855 ps
CPU time 3.13 seconds
Started Mar 03 12:39:55 PM PST 24
Finished Mar 03 12:39:59 PM PST 24
Peak memory 198072 kb
Host smart-f010fae0-b107-4ee9-9109-e4557942f1e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176260535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2176260535
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2445757299
Short name T325
Test name
Test status
Simulation time 98396496 ps
CPU time 0.73 seconds
Started Mar 03 12:40:08 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 195152 kb
Host smart-3e7fe7f0-4823-4641-a14e-694bde6391d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445757299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2445757299
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.4098102458
Short name T709
Test name
Test status
Simulation time 676698127 ps
CPU time 1.28 seconds
Started Mar 03 12:39:46 PM PST 24
Finished Mar 03 12:39:47 PM PST 24
Peak memory 198008 kb
Host smart-02f27ab9-df7b-4076-b3bf-e8ba2a50f5cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098102458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.4098102458
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2161177499
Short name T601
Test name
Test status
Simulation time 10967885441 ps
CPU time 94.78 seconds
Started Mar 03 12:39:52 PM PST 24
Finished Mar 03 12:41:27 PM PST 24
Peak memory 198212 kb
Host smart-ee9d8664-031c-47d3-bcb6-64e574af4c15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161177499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2161177499
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.534774610
Short name T653
Test name
Test status
Simulation time 43393954 ps
CPU time 0.58 seconds
Started Mar 03 12:39:59 PM PST 24
Finished Mar 03 12:40:01 PM PST 24
Peak memory 193308 kb
Host smart-b3b10daf-a982-4959-9743-945ec4763221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534774610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.534774610
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3083550640
Short name T360
Test name
Test status
Simulation time 26477046 ps
CPU time 0.85 seconds
Started Mar 03 12:39:50 PM PST 24
Finished Mar 03 12:39:51 PM PST 24
Peak memory 196412 kb
Host smart-da37454d-90fb-4acd-8bbe-10f1ef689241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083550640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3083550640
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2093150628
Short name T235
Test name
Test status
Simulation time 1533325860 ps
CPU time 10.96 seconds
Started Mar 03 12:39:54 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 195696 kb
Host smart-e44d0e2a-e614-4868-8a36-def3c39bd440
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093150628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2093150628
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3195196291
Short name T393
Test name
Test status
Simulation time 154019859 ps
CPU time 0.95 seconds
Started Mar 03 12:39:41 PM PST 24
Finished Mar 03 12:39:42 PM PST 24
Peak memory 197920 kb
Host smart-e6a8eeff-9430-4418-98ca-e68d555afade
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195196291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3195196291
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3677185044
Short name T656
Test name
Test status
Simulation time 46622862 ps
CPU time 0.68 seconds
Started Mar 03 12:39:57 PM PST 24
Finished Mar 03 12:39:58 PM PST 24
Peak memory 194452 kb
Host smart-326a16c2-5bc0-4d54-b3b8-fe945699329f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677185044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3677185044
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.924333491
Short name T603
Test name
Test status
Simulation time 97893710 ps
CPU time 1.96 seconds
Started Mar 03 12:39:46 PM PST 24
Finished Mar 03 12:39:48 PM PST 24
Peak memory 198128 kb
Host smart-f2136bed-8dce-413f-a17d-fa340deb7df3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924333491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.924333491
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3226254498
Short name T516
Test name
Test status
Simulation time 496471015 ps
CPU time 2.32 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:22 PM PST 24
Peak memory 197052 kb
Host smart-104f1873-a434-4c10-b6ea-d492d68e8310
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226254498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3226254498
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1853235026
Short name T621
Test name
Test status
Simulation time 169343143 ps
CPU time 0.96 seconds
Started Mar 03 12:40:01 PM PST 24
Finished Mar 03 12:40:02 PM PST 24
Peak memory 196060 kb
Host smart-b1aaf9f4-2d78-48d2-bd52-cf269ee037ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853235026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1853235026
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.265895481
Short name T598
Test name
Test status
Simulation time 30246890 ps
CPU time 0.65 seconds
Started Mar 03 12:40:15 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 194868 kb
Host smart-9d0e533e-d3d8-4e0e-9f09-2e7f9756a014
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265895481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.265895481
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1261462844
Short name T676
Test name
Test status
Simulation time 363785654 ps
CPU time 4.2 seconds
Started Mar 03 12:39:57 PM PST 24
Finished Mar 03 12:40:02 PM PST 24
Peak memory 198040 kb
Host smart-12fd7900-61ca-4ae9-a3c2-42cf7339e1c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261462844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1261462844
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3608284885
Short name T353
Test name
Test status
Simulation time 247932935 ps
CPU time 0.95 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 196428 kb
Host smart-54c7e27e-f68d-4cda-a8c9-2cd65e12b349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608284885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3608284885
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.573685566
Short name T489
Test name
Test status
Simulation time 177652707 ps
CPU time 1.06 seconds
Started Mar 03 12:40:15 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 194820 kb
Host smart-8589a1fd-54c4-404b-9d7e-fb1f3c078a8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573685566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.573685566
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.139336328
Short name T697
Test name
Test status
Simulation time 12306636392 ps
CPU time 81.62 seconds
Started Mar 03 12:40:00 PM PST 24
Finished Mar 03 12:41:22 PM PST 24
Peak memory 198264 kb
Host smart-e7ade3fc-7baa-4240-bd8d-2fa4528bd1fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139336328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.139336328
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2096558181
Short name T453
Test name
Test status
Simulation time 48094414 ps
CPU time 0.59 seconds
Started Mar 03 12:40:08 PM PST 24
Finished Mar 03 12:40:09 PM PST 24
Peak memory 194984 kb
Host smart-3d3f266a-93a8-407c-acf1-0f6f74024519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096558181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2096558181
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2403261114
Short name T118
Test name
Test status
Simulation time 33170893 ps
CPU time 0.8 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 195380 kb
Host smart-91d6ceee-c148-4530-8958-e60d3fc1bcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403261114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2403261114
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2401739714
Short name T554
Test name
Test status
Simulation time 259620098 ps
CPU time 7.92 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:10 PM PST 24
Peak memory 196336 kb
Host smart-5f39877e-d21c-4c7c-abdc-302e4fe9e2be
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401739714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2401739714
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3725324569
Short name T200
Test name
Test status
Simulation time 128503345 ps
CPU time 0.77 seconds
Started Mar 03 12:40:17 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 196452 kb
Host smart-aca842e3-38ac-4cf5-adb6-cf5501dff8f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725324569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3725324569
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1804339726
Short name T592
Test name
Test status
Simulation time 203487310 ps
CPU time 1.29 seconds
Started Mar 03 12:40:04 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 198100 kb
Host smart-a00d74b1-846e-4b4d-8252-205e72800f78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804339726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1804339726
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2806781059
Short name T236
Test name
Test status
Simulation time 167664007 ps
CPU time 3.11 seconds
Started Mar 03 12:40:09 PM PST 24
Finished Mar 03 12:40:13 PM PST 24
Peak memory 197824 kb
Host smart-a072b93a-0efa-433e-81bb-9dda1c78b343
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806781059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2806781059
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1312898076
Short name T665
Test name
Test status
Simulation time 63063536 ps
CPU time 1.53 seconds
Started Mar 03 12:40:01 PM PST 24
Finished Mar 03 12:40:02 PM PST 24
Peak memory 195904 kb
Host smart-247f1b96-baf2-4f33-afd8-ffc3155b2ae9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312898076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1312898076
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3597575452
Short name T410
Test name
Test status
Simulation time 372131418 ps
CPU time 1.08 seconds
Started Mar 03 12:40:01 PM PST 24
Finished Mar 03 12:40:02 PM PST 24
Peak memory 196000 kb
Host smart-c92ade77-d795-4a87-afde-5bff6923f3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597575452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3597575452
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4049977321
Short name T561
Test name
Test status
Simulation time 58129269 ps
CPU time 0.83 seconds
Started Mar 03 12:39:59 PM PST 24
Finished Mar 03 12:40:00 PM PST 24
Peak memory 195568 kb
Host smart-d8433162-ede2-4da1-933f-17944a036839
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049977321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4049977321
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.321925526
Short name T9
Test name
Test status
Simulation time 323231504 ps
CPU time 3.84 seconds
Started Mar 03 12:39:51 PM PST 24
Finished Mar 03 12:39:55 PM PST 24
Peak memory 198020 kb
Host smart-479c3597-1e2b-4d6b-8642-96629d562f63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321925526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.321925526
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2050910120
Short name T694
Test name
Test status
Simulation time 130871462 ps
CPU time 1.08 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 195624 kb
Host smart-fb3b0f98-3574-48c4-b328-7f9c1413a6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050910120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2050910120
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2565676312
Short name T599
Test name
Test status
Simulation time 41247081 ps
CPU time 1.1 seconds
Started Mar 03 12:40:18 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 196500 kb
Host smart-33cf91e1-be1f-4310-b09e-8af606925451
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565676312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2565676312
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3414856636
Short name T417
Test name
Test status
Simulation time 4091945360 ps
CPU time 43.06 seconds
Started Mar 03 12:40:13 PM PST 24
Finished Mar 03 12:40:56 PM PST 24
Peak memory 198080 kb
Host smart-6edd8b48-fbc9-4709-804a-44052f1afa94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414856636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3414856636
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2380043096
Short name T595
Test name
Test status
Simulation time 26812401 ps
CPU time 0.6 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 193984 kb
Host smart-39be10c2-47ed-4fa2-9a83-3e9cd934a3bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380043096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2380043096
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3359247147
Short name T359
Test name
Test status
Simulation time 175717095 ps
CPU time 0.92 seconds
Started Mar 03 12:39:39 PM PST 24
Finished Mar 03 12:39:40 PM PST 24
Peak memory 196656 kb
Host smart-fe2886ba-00f0-4ced-8699-ca143ff0ca45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359247147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3359247147
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1274690990
Short name T597
Test name
Test status
Simulation time 2891104891 ps
CPU time 9.04 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:15 PM PST 24
Peak memory 196960 kb
Host smart-472bd4e7-1e8e-4299-a43b-6eb3d0cb85bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274690990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1274690990
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.144032864
Short name T317
Test name
Test status
Simulation time 117781896 ps
CPU time 0.93 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:08 PM PST 24
Peak memory 196596 kb
Host smart-61e32346-0594-4a9f-99d6-761399ecd88a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144032864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.144032864
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.289852215
Short name T302
Test name
Test status
Simulation time 26040209 ps
CPU time 0.71 seconds
Started Mar 03 12:39:43 PM PST 24
Finished Mar 03 12:39:44 PM PST 24
Peak memory 195140 kb
Host smart-23e37120-ed36-44b0-8b57-883ff703b59f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289852215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.289852215
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3050742282
Short name T660
Test name
Test status
Simulation time 68702205 ps
CPU time 2.76 seconds
Started Mar 03 12:39:53 PM PST 24
Finished Mar 03 12:39:56 PM PST 24
Peak memory 198068 kb
Host smart-8d9dd7a8-c050-4a68-9956-6f1cf5bc2cae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050742282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3050742282
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3664714217
Short name T169
Test name
Test status
Simulation time 32319782 ps
CPU time 1.09 seconds
Started Mar 03 12:39:58 PM PST 24
Finished Mar 03 12:39:59 PM PST 24
Peak memory 196560 kb
Host smart-d9641992-e4b0-42b9-84c8-16f05502fa9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664714217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3664714217
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1348217717
Short name T481
Test name
Test status
Simulation time 83077046 ps
CPU time 1.07 seconds
Started Mar 03 12:40:03 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 196052 kb
Host smart-e4aaad17-e426-4e2a-91b9-00a6a8b5f6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348217717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1348217717
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2888814304
Short name T130
Test name
Test status
Simulation time 72007470 ps
CPU time 0.85 seconds
Started Mar 03 12:40:04 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 196064 kb
Host smart-f61227a3-8fcc-4f2c-87a1-f374b3775df3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888814304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2888814304
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2847221014
Short name T675
Test name
Test status
Simulation time 127224000 ps
CPU time 5.72 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 198004 kb
Host smart-7ffa0c9e-5fad-4d5d-a68c-7d971725b4c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847221014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2847221014
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2525356869
Short name T97
Test name
Test status
Simulation time 112779122 ps
CPU time 1.05 seconds
Started Mar 03 12:40:15 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 194948 kb
Host smart-84c80b16-f8a2-48b5-b1f1-5f5de5a0f062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525356869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2525356869
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3549826760
Short name T318
Test name
Test status
Simulation time 55378202 ps
CPU time 1.3 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:04 PM PST 24
Peak memory 196864 kb
Host smart-5dee6435-4737-4a49-8c47-a9d55b6dadc4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549826760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3549826760
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.274367282
Short name T250
Test name
Test status
Simulation time 8628640372 ps
CPU time 118.21 seconds
Started Mar 03 12:40:17 PM PST 24
Finished Mar 03 12:42:16 PM PST 24
Peak memory 198160 kb
Host smart-d0eabe25-4a16-4ae6-9adb-754dfa97e8e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274367282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.274367282
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.2687012037
Short name T530
Test name
Test status
Simulation time 13884026268 ps
CPU time 421.35 seconds
Started Mar 03 12:40:14 PM PST 24
Finished Mar 03 12:47:17 PM PST 24
Peak memory 198340 kb
Host smart-4d0c5dc4-333f-4aa4-a4a1-f99ebcf43fd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2687012037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.2687012037
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2654907049
Short name T537
Test name
Test status
Simulation time 26710327 ps
CPU time 0.57 seconds
Started Mar 03 12:40:10 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 194044 kb
Host smart-36e2a2f9-f77b-4146-8fce-c5b93097f818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654907049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2654907049
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2965077131
Short name T528
Test name
Test status
Simulation time 57997635 ps
CPU time 0.63 seconds
Started Mar 03 12:40:08 PM PST 24
Finished Mar 03 12:40:10 PM PST 24
Peak memory 193964 kb
Host smart-4450b4d7-1b36-41c6-b2c0-9b2c34bf5e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965077131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2965077131
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3646767204
Short name T409
Test name
Test status
Simulation time 164123494 ps
CPU time 5.48 seconds
Started Mar 03 12:40:21 PM PST 24
Finished Mar 03 12:40:32 PM PST 24
Peak memory 198072 kb
Host smart-f36c8499-1918-4950-9b16-1e6733dc7823
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646767204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3646767204
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2993539802
Short name T61
Test name
Test status
Simulation time 44321874 ps
CPU time 0.87 seconds
Started Mar 03 12:39:54 PM PST 24
Finished Mar 03 12:39:55 PM PST 24
Peak memory 196172 kb
Host smart-7f721bc2-252f-4281-a008-6eda6562b4a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993539802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2993539802
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.4078189208
Short name T590
Test name
Test status
Simulation time 102888741 ps
CPU time 1.03 seconds
Started Mar 03 12:40:04 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 196188 kb
Host smart-a73c537d-03af-4fb1-b76f-e78ed2d01066
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078189208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.4078189208
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2911671868
Short name T658
Test name
Test status
Simulation time 170004959 ps
CPU time 3.25 seconds
Started Mar 03 12:40:08 PM PST 24
Finished Mar 03 12:40:12 PM PST 24
Peak memory 198136 kb
Host smart-486d756f-2441-4fab-96a2-b6c62eaf65c4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911671868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2911671868
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.871519940
Short name T700
Test name
Test status
Simulation time 228111004 ps
CPU time 1.57 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:04 PM PST 24
Peak memory 195868 kb
Host smart-ab22c1c3-6366-4c32-b080-e3aeb3f2d42a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871519940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
871519940
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3353423795
Short name T562
Test name
Test status
Simulation time 94534074 ps
CPU time 0.68 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:08 PM PST 24
Peak memory 195368 kb
Host smart-fd706c8b-a2ba-488c-b74a-462286726582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353423795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3353423795
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.135310780
Short name T651
Test name
Test status
Simulation time 33554021 ps
CPU time 1.24 seconds
Started Mar 03 12:40:18 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 198092 kb
Host smart-01c35c97-2b5a-4c9a-84e8-133dac504f44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135310780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.135310780
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1608823921
Short name T135
Test name
Test status
Simulation time 197909598 ps
CPU time 4.44 seconds
Started Mar 03 12:40:12 PM PST 24
Finished Mar 03 12:40:17 PM PST 24
Peak memory 198052 kb
Host smart-58c5e64f-3994-43da-957e-5a8e2b770ad8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608823921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1608823921
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3340559091
Short name T285
Test name
Test status
Simulation time 108044370 ps
CPU time 1.05 seconds
Started Mar 03 12:40:04 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 195760 kb
Host smart-d819be14-620c-4a0f-bc01-fce8a05a890b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340559091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3340559091
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.994298235
Short name T237
Test name
Test status
Simulation time 91520552 ps
CPU time 1.27 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:07 PM PST 24
Peak memory 196444 kb
Host smart-7420f977-9a2b-4dec-8668-1a61d82413d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994298235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.994298235
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3122837790
Short name T203
Test name
Test status
Simulation time 25253303084 ps
CPU time 89.09 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:41:51 PM PST 24
Peak memory 198196 kb
Host smart-ed61cf55-d8e2-4988-bc41-32777d82aef9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122837790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3122837790
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1007315622
Short name T703
Test name
Test status
Simulation time 11680008 ps
CPU time 0.56 seconds
Started Mar 03 12:39:54 PM PST 24
Finished Mar 03 12:39:55 PM PST 24
Peak memory 194144 kb
Host smart-b7035fb3-5e52-43bc-ae87-6a8ae6fc2496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007315622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1007315622
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.4257594521
Short name T565
Test name
Test status
Simulation time 107904911 ps
CPU time 0.82 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 195312 kb
Host smart-2c2fc505-7000-4bd6-abd5-648952e10d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257594521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.4257594521
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3948637642
Short name T120
Test name
Test status
Simulation time 1690331577 ps
CPU time 22.48 seconds
Started Mar 03 12:40:17 PM PST 24
Finished Mar 03 12:40:40 PM PST 24
Peak memory 196960 kb
Host smart-9fd4fc8e-22f7-411d-9bf0-ef939e479f74
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948637642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3948637642
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2864012636
Short name T154
Test name
Test status
Simulation time 232820628 ps
CPU time 0.98 seconds
Started Mar 03 12:40:01 PM PST 24
Finished Mar 03 12:40:02 PM PST 24
Peak memory 196664 kb
Host smart-0a89b4a8-61b3-4ea6-9f03-82b11f220226
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864012636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2864012636
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3339721637
Short name T106
Test name
Test status
Simulation time 359025941 ps
CPU time 1.22 seconds
Started Mar 03 12:39:59 PM PST 24
Finished Mar 03 12:40:01 PM PST 24
Peak memory 196576 kb
Host smart-387b8a4a-f6e7-43c0-825b-9e0eab45146d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339721637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3339721637
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3897005963
Short name T255
Test name
Test status
Simulation time 88061957 ps
CPU time 0.99 seconds
Started Mar 03 12:40:08 PM PST 24
Finished Mar 03 12:40:10 PM PST 24
Peak memory 196312 kb
Host smart-b666a78a-45b0-44f6-9f19-d115b329787d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897005963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3897005963
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.987088923
Short name T716
Test name
Test status
Simulation time 433885501 ps
CPU time 2.57 seconds
Started Mar 03 12:39:58 PM PST 24
Finished Mar 03 12:40:00 PM PST 24
Peak memory 195880 kb
Host smart-3d456df0-845c-403c-8135-b8e88e42ad3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987088923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
987088923
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2902274432
Short name T495
Test name
Test status
Simulation time 64036349 ps
CPU time 1.14 seconds
Started Mar 03 12:40:17 PM PST 24
Finished Mar 03 12:40:19 PM PST 24
Peak memory 197216 kb
Host smart-4b38bec9-3f8a-49b7-99df-071d9c6c33b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902274432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2902274432
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.544163635
Short name T705
Test name
Test status
Simulation time 476841999 ps
CPU time 1.05 seconds
Started Mar 03 12:40:01 PM PST 24
Finished Mar 03 12:40:02 PM PST 24
Peak memory 196356 kb
Host smart-57192b65-83c6-4ba1-8510-342902702cac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544163635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.544163635
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2599699524
Short name T459
Test name
Test status
Simulation time 189148049 ps
CPU time 2.35 seconds
Started Mar 03 12:40:00 PM PST 24
Finished Mar 03 12:40:02 PM PST 24
Peak memory 197840 kb
Host smart-46a5f98f-5cd6-4ed6-91c2-ba765fccb754
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599699524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2599699524
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1012921771
Short name T570
Test name
Test status
Simulation time 34873794 ps
CPU time 1.03 seconds
Started Mar 03 12:40:21 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 196480 kb
Host smart-bb4fb764-278a-47c8-84bc-35f248daac3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012921771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1012921771
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.951168968
Short name T569
Test name
Test status
Simulation time 48981673 ps
CPU time 0.85 seconds
Started Mar 03 12:40:10 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 195156 kb
Host smart-b3c487ca-ddc5-4888-af52-ae9ca6d52483
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951168968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.951168968
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.4047642346
Short name T13
Test name
Test status
Simulation time 29728076421 ps
CPU time 197.62 seconds
Started Mar 03 12:40:05 PM PST 24
Finished Mar 03 12:43:23 PM PST 24
Peak memory 198328 kb
Host smart-14b5ae24-0d82-4371-a432-e93397f0c663
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047642346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.4047642346
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.332261233
Short name T633
Test name
Test status
Simulation time 394277096743 ps
CPU time 1221.31 seconds
Started Mar 03 12:40:05 PM PST 24
Finished Mar 03 01:00:26 PM PST 24
Peak memory 198376 kb
Host smart-ba9314e2-bf9c-41d0-89ff-920fbb9be9fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=332261233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.332261233
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1024734171
Short name T341
Test name
Test status
Simulation time 12718156 ps
CPU time 0.59 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:03 PM PST 24
Peak memory 194088 kb
Host smart-93e008ce-4830-41f0-974d-db9233e94a3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024734171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1024734171
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3092373481
Short name T400
Test name
Test status
Simulation time 177557727 ps
CPU time 1.01 seconds
Started Mar 03 12:40:17 PM PST 24
Finished Mar 03 12:40:19 PM PST 24
Peak memory 196312 kb
Host smart-973b32f3-5da1-4845-af31-b7bac3fa2368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092373481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3092373481
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1255605446
Short name T182
Test name
Test status
Simulation time 308714078 ps
CPU time 8.3 seconds
Started Mar 03 12:40:11 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 196828 kb
Host smart-17c54734-2627-42e3-a1f5-d0cebf68b7c2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255605446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1255605446
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.84106293
Short name T514
Test name
Test status
Simulation time 65642317 ps
CPU time 0.67 seconds
Started Mar 03 12:40:04 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 194592 kb
Host smart-ced07f51-6676-46d0-868d-708468d79b7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84106293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.84106293
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1588626055
Short name T544
Test name
Test status
Simulation time 43305223 ps
CPU time 0.88 seconds
Started Mar 03 12:40:03 PM PST 24
Finished Mar 03 12:40:04 PM PST 24
Peak memory 197484 kb
Host smart-252148f9-3698-41ac-b714-9694af479dff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588626055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1588626055
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2348664553
Short name T144
Test name
Test status
Simulation time 93368364 ps
CPU time 3.31 seconds
Started Mar 03 12:40:07 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 198068 kb
Host smart-044a2bc5-f125-4077-ba6d-42337a1ab763
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348664553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2348664553
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1735992029
Short name T259
Test name
Test status
Simulation time 264007672 ps
CPU time 1.6 seconds
Started Mar 03 12:40:09 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 196048 kb
Host smart-167bcac0-a5f6-4a1d-998c-a7bc65d2ea1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735992029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1735992029
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.4050093807
Short name T577
Test name
Test status
Simulation time 25623192 ps
CPU time 0.72 seconds
Started Mar 03 12:40:03 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 195060 kb
Host smart-bafc09dd-b9bf-48be-b1cc-63207af31ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050093807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.4050093807
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.254629222
Short name T11
Test name
Test status
Simulation time 182523783 ps
CPU time 1.13 seconds
Started Mar 03 12:40:01 PM PST 24
Finished Mar 03 12:40:03 PM PST 24
Peak memory 196104 kb
Host smart-aaf6ed36-7851-43d7-a0e7-675f78c446b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254629222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.254629222
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.4038352301
Short name T556
Test name
Test status
Simulation time 57008964 ps
CPU time 2.72 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 198052 kb
Host smart-5bacc90b-52ae-4486-8c75-fe5f92592141
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038352301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.4038352301
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3916571770
Short name T711
Test name
Test status
Simulation time 161076400 ps
CPU time 1.06 seconds
Started Mar 03 12:40:05 PM PST 24
Finished Mar 03 12:40:06 PM PST 24
Peak memory 195576 kb
Host smart-82217893-ce47-498d-8b01-66a8d4fcee02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916571770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3916571770
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3866503788
Short name T278
Test name
Test status
Simulation time 84901716 ps
CPU time 1.26 seconds
Started Mar 03 12:40:00 PM PST 24
Finished Mar 03 12:40:02 PM PST 24
Peak memory 196688 kb
Host smart-d2c6eec6-4bb9-49f0-a1a8-65c4825a585d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866503788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3866503788
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2928026362
Short name T585
Test name
Test status
Simulation time 9348834462 ps
CPU time 128.23 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:42:11 PM PST 24
Peak memory 198232 kb
Host smart-226689b2-8829-43e0-aac6-99f90182afc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928026362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2928026362
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1741624387
Short name T213
Test name
Test status
Simulation time 27960584 ps
CPU time 0.55 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:07 PM PST 24
Peak memory 192736 kb
Host smart-b82743a3-75ab-4041-a642-1bfea030fa01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741624387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1741624387
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2564907929
Short name T207
Test name
Test status
Simulation time 59441362 ps
CPU time 0.79 seconds
Started Mar 03 12:40:19 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 195104 kb
Host smart-be221a03-d9ab-4728-8d86-d9d0d4a595cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564907929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2564907929
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1312616904
Short name T538
Test name
Test status
Simulation time 267762224 ps
CPU time 8.64 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 198164 kb
Host smart-2145fddb-1485-42ed-8c51-c1b095d3ed73
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312616904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1312616904
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2315059915
Short name T451
Test name
Test status
Simulation time 49154070 ps
CPU time 0.73 seconds
Started Mar 03 12:39:57 PM PST 24
Finished Mar 03 12:39:58 PM PST 24
Peak memory 194700 kb
Host smart-b8359b96-c084-4e85-8169-b1d1e8382bca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315059915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2315059915
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3861893108
Short name T434
Test name
Test status
Simulation time 156287010 ps
CPU time 0.85 seconds
Started Mar 03 12:40:09 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 196480 kb
Host smart-a665b802-0022-46a6-adb1-9aa967dde718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861893108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3861893108
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2943678283
Short name T536
Test name
Test status
Simulation time 60584687 ps
CPU time 2.52 seconds
Started Mar 03 12:39:53 PM PST 24
Finished Mar 03 12:39:56 PM PST 24
Peak memory 198220 kb
Host smart-3d72b080-1e0a-40f5-8f54-2cb1fd4c8cd6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943678283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2943678283
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.842133635
Short name T391
Test name
Test status
Simulation time 169855296 ps
CPU time 1.46 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:08 PM PST 24
Peak memory 196100 kb
Host smart-cfd8d5a8-6d0a-4d29-ba5e-3451bdfcd4ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842133635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
842133635
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3118020355
Short name T327
Test name
Test status
Simulation time 75152647 ps
CPU time 1.41 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:08 PM PST 24
Peak memory 196952 kb
Host smart-068d076a-c387-4c8a-aff5-f67df8caf818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118020355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3118020355
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1701425167
Short name T129
Test name
Test status
Simulation time 18809252 ps
CPU time 0.77 seconds
Started Mar 03 12:40:11 PM PST 24
Finished Mar 03 12:40:12 PM PST 24
Peak memory 195568 kb
Host smart-939fdd4d-f5a0-4f43-bc89-faa2ce074200
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701425167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1701425167
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3623975382
Short name T3
Test name
Test status
Simulation time 169990580 ps
CPU time 2.19 seconds
Started Mar 03 12:40:04 PM PST 24
Finished Mar 03 12:40:12 PM PST 24
Peak memory 198032 kb
Host smart-b5a1429b-7f33-4df2-b66b-386dba3b76f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623975382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3623975382
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.681335190
Short name T392
Test name
Test status
Simulation time 77462743 ps
CPU time 1.19 seconds
Started Mar 03 12:40:18 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 195656 kb
Host smart-9a6d26d4-4ca4-42a2-9aaa-556ca6b3d889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681335190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.681335190
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1094717119
Short name T662
Test name
Test status
Simulation time 26583520 ps
CPU time 0.87 seconds
Started Mar 03 12:39:59 PM PST 24
Finished Mar 03 12:40:00 PM PST 24
Peak memory 196568 kb
Host smart-3de4c7b3-fea3-4ad5-893e-ed4c8e0dbceb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094717119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1094717119
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2718431641
Short name T153
Test name
Test status
Simulation time 52456555609 ps
CPU time 195.83 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:43:38 PM PST 24
Peak memory 198256 kb
Host smart-2ceab5ad-c0a5-4586-a8c7-b9276f5594c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718431641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2718431641
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3630105853
Short name T506
Test name
Test status
Simulation time 19029865 ps
CPU time 0.54 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 193916 kb
Host smart-8399418d-518b-4032-8b00-ced5e523dc72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630105853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3630105853
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2762461790
Short name T374
Test name
Test status
Simulation time 88209054 ps
CPU time 0.71 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:03 PM PST 24
Peak memory 194232 kb
Host smart-10bdb40f-1e75-42a2-a04c-e744135440f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762461790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2762461790
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3966598691
Short name T330
Test name
Test status
Simulation time 12562074135 ps
CPU time 24.17 seconds
Started Mar 03 12:40:15 PM PST 24
Finished Mar 03 12:40:45 PM PST 24
Peak memory 198464 kb
Host smart-3686c072-0f3c-468c-a604-6dc85ee39d33
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966598691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3966598691
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3029603624
Short name T673
Test name
Test status
Simulation time 92290426 ps
CPU time 1.09 seconds
Started Mar 03 12:40:09 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 196520 kb
Host smart-157740ec-f480-4cdb-8ca5-ca0c419f9a82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029603624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3029603624
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1679113156
Short name T404
Test name
Test status
Simulation time 31310059 ps
CPU time 0.74 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:08 PM PST 24
Peak memory 195688 kb
Host smart-9233470f-70cf-4d45-ac60-a6104b6c15b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679113156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1679113156
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2459371809
Short name T649
Test name
Test status
Simulation time 102276506 ps
CPU time 2.87 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 198020 kb
Host smart-b61a6730-4d71-432a-b2ff-c66c8a58aa24
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459371809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2459371809
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1600543065
Short name T132
Test name
Test status
Simulation time 172857327 ps
CPU time 3.19 seconds
Started Mar 03 12:40:04 PM PST 24
Finished Mar 03 12:40:08 PM PST 24
Peak memory 197264 kb
Host smart-976ccb7c-d936-4082-ae6e-b8ca294bf848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600543065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1600543065
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3314601188
Short name T142
Test name
Test status
Simulation time 171566170 ps
CPU time 1.1 seconds
Started Mar 03 12:40:14 PM PST 24
Finished Mar 03 12:40:16 PM PST 24
Peak memory 196120 kb
Host smart-5de68e41-198e-4e6b-9043-b6fa91c61941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314601188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3314601188
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1180318387
Short name T503
Test name
Test status
Simulation time 25247566 ps
CPU time 0.72 seconds
Started Mar 03 12:40:04 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 195436 kb
Host smart-a4f4d3bf-c587-4317-97f3-5057665036b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180318387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1180318387
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.4232775271
Short name T686
Test name
Test status
Simulation time 121797504 ps
CPU time 5.34 seconds
Started Mar 03 12:40:01 PM PST 24
Finished Mar 03 12:40:06 PM PST 24
Peak memory 198036 kb
Host smart-b6b930ad-a387-4319-ba23-56360706f6ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232775271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.4232775271
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.534348234
Short name T620
Test name
Test status
Simulation time 252726764 ps
CPU time 1.35 seconds
Started Mar 03 12:40:03 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 195588 kb
Host smart-765cdd1d-c546-4f43-be8b-8b651bd1d279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534348234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.534348234
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2178915957
Short name T211
Test name
Test status
Simulation time 58184043 ps
CPU time 1 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:03 PM PST 24
Peak memory 196456 kb
Host smart-f3d52dae-426f-4b53-9f11-77984aa31520
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178915957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2178915957
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3436093136
Short name T710
Test name
Test status
Simulation time 6332052901 ps
CPU time 70.8 seconds
Started Mar 03 12:40:13 PM PST 24
Finished Mar 03 12:41:24 PM PST 24
Peak memory 198332 kb
Host smart-67741998-778c-44ad-90c9-2891d70cb375
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436093136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3436093136
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.1075451778
Short name T688
Test name
Test status
Simulation time 22988795399 ps
CPU time 670.01 seconds
Started Mar 03 12:40:05 PM PST 24
Finished Mar 03 12:51:15 PM PST 24
Peak memory 198376 kb
Host smart-1af50dd1-57ff-44f8-85f1-48476033523a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1075451778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.1075451778
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3510922155
Short name T467
Test name
Test status
Simulation time 25069823 ps
CPU time 0.6 seconds
Started Mar 03 12:39:02 PM PST 24
Finished Mar 03 12:39:03 PM PST 24
Peak memory 195012 kb
Host smart-1423b31f-0346-4083-acae-52c94b312d5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510922155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3510922155
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1400483947
Short name T370
Test name
Test status
Simulation time 34826518 ps
CPU time 0.64 seconds
Started Mar 03 12:38:57 PM PST 24
Finished Mar 03 12:38:59 PM PST 24
Peak memory 194760 kb
Host smart-62e1156e-c2c4-4774-b46b-554f242eba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400483947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1400483947
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1845973647
Short name T215
Test name
Test status
Simulation time 660120968 ps
CPU time 16.97 seconds
Started Mar 03 12:38:57 PM PST 24
Finished Mar 03 12:39:14 PM PST 24
Peak memory 197076 kb
Host smart-c0db91a5-ca9f-4a32-ae94-1b98a8bcbd0a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845973647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1845973647
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.634470138
Short name T624
Test name
Test status
Simulation time 23672237 ps
CPU time 0.61 seconds
Started Mar 03 12:39:03 PM PST 24
Finished Mar 03 12:39:04 PM PST 24
Peak memory 195224 kb
Host smart-a8422d40-84a3-48ba-ba3d-afb026325a6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634470138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.634470138
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.4056213861
Short name T304
Test name
Test status
Simulation time 60890785 ps
CPU time 1.06 seconds
Started Mar 03 12:38:57 PM PST 24
Finished Mar 03 12:38:58 PM PST 24
Peak memory 196984 kb
Host smart-923df376-9973-4922-9c37-425110105395
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056213861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.4056213861
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3597913437
Short name T175
Test name
Test status
Simulation time 55850069 ps
CPU time 2.34 seconds
Started Mar 03 12:39:15 PM PST 24
Finished Mar 03 12:39:22 PM PST 24
Peak memory 198092 kb
Host smart-72835b3c-a900-430f-bbaa-ba0bc25a1042
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597913437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3597913437
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2113337278
Short name T515
Test name
Test status
Simulation time 869524400 ps
CPU time 3.23 seconds
Started Mar 03 12:39:13 PM PST 24
Finished Mar 03 12:39:18 PM PST 24
Peak memory 196812 kb
Host smart-3d8c1c88-5f22-41d6-b8e5-4c9cecc544c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113337278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2113337278
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.4096351572
Short name T204
Test name
Test status
Simulation time 43100344 ps
CPU time 0.95 seconds
Started Mar 03 12:39:03 PM PST 24
Finished Mar 03 12:39:05 PM PST 24
Peak memory 196432 kb
Host smart-a8584046-044c-4ab4-b60e-b6892ba080f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096351572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.4096351572
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2931564576
Short name T504
Test name
Test status
Simulation time 137508352 ps
CPU time 0.82 seconds
Started Mar 03 12:39:01 PM PST 24
Finished Mar 03 12:39:03 PM PST 24
Peak memory 196172 kb
Host smart-994f0054-b9a9-4390-b35e-583b579429f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931564576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2931564576
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1495606997
Short name T456
Test name
Test status
Simulation time 3118187284 ps
CPU time 3.43 seconds
Started Mar 03 12:39:00 PM PST 24
Finished Mar 03 12:39:03 PM PST 24
Peak memory 198168 kb
Host smart-36c58507-f62f-43b9-974d-06d392649f0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495606997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1495606997
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_smoke.3070298888
Short name T282
Test name
Test status
Simulation time 281042733 ps
CPU time 1.4 seconds
Started Mar 03 12:39:00 PM PST 24
Finished Mar 03 12:39:01 PM PST 24
Peak memory 196724 kb
Host smart-bc19663f-502d-47e0-886a-33bde8e603e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070298888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3070298888
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3240541756
Short name T487
Test name
Test status
Simulation time 153157798 ps
CPU time 1.42 seconds
Started Mar 03 12:39:01 PM PST 24
Finished Mar 03 12:39:04 PM PST 24
Peak memory 198352 kb
Host smart-7b1ea5d8-04b9-4984-be1f-df76952ee203
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240541756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3240541756
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1398052762
Short name T273
Test name
Test status
Simulation time 10577722840 ps
CPU time 149.75 seconds
Started Mar 03 12:38:57 PM PST 24
Finished Mar 03 12:41:26 PM PST 24
Peak memory 198340 kb
Host smart-34ae4e56-a243-44d6-9a71-35a4c51aa1b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398052762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1398052762
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.2596756698
Short name T27
Test name
Test status
Simulation time 267286633589 ps
CPU time 1436.87 seconds
Started Mar 03 12:39:20 PM PST 24
Finished Mar 03 01:03:18 PM PST 24
Peak memory 198396 kb
Host smart-ad945f3e-32a5-4587-9eb8-63220155ffac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2596756698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.2596756698
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1908297632
Short name T197
Test name
Test status
Simulation time 23275290 ps
CPU time 0.62 seconds
Started Mar 03 12:40:07 PM PST 24
Finished Mar 03 12:40:08 PM PST 24
Peak memory 194020 kb
Host smart-629026fe-f812-45f5-aa1c-f5609263251d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908297632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1908297632
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1751496293
Short name T643
Test name
Test status
Simulation time 153089285 ps
CPU time 0.92 seconds
Started Mar 03 12:40:14 PM PST 24
Finished Mar 03 12:40:16 PM PST 24
Peak memory 196596 kb
Host smart-87eae59a-edd0-4513-b65f-760f85e1c6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751496293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1751496293
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.431842361
Short name T652
Test name
Test status
Simulation time 403594223 ps
CPU time 5.62 seconds
Started Mar 03 12:40:19 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 197072 kb
Host smart-b3b4bc2e-e676-4f0b-a993-87913d2d3860
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431842361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.431842361
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3103268820
Short name T421
Test name
Test status
Simulation time 208698904 ps
CPU time 0.95 seconds
Started Mar 03 12:40:18 PM PST 24
Finished Mar 03 12:40:19 PM PST 24
Peak memory 196668 kb
Host smart-09e43d02-1bfb-49d8-8958-a0019d1fe3e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103268820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3103268820
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3414426177
Short name T265
Test name
Test status
Simulation time 133949309 ps
CPU time 0.78 seconds
Started Mar 03 12:40:15 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 194716 kb
Host smart-e8bd322b-323e-433d-89db-d478f497b629
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414426177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3414426177
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2727689919
Short name T292
Test name
Test status
Simulation time 298241711 ps
CPU time 2.74 seconds
Started Mar 03 12:40:33 PM PST 24
Finished Mar 03 12:40:36 PM PST 24
Peak memory 198244 kb
Host smart-ca58dc57-a2c4-473b-96c2-7ee35f70b177
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727689919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2727689919
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.532704716
Short name T137
Test name
Test status
Simulation time 176636595 ps
CPU time 1.57 seconds
Started Mar 03 12:40:04 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 196148 kb
Host smart-4ad6a229-6f35-4506-b62e-54b2f1046c74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532704716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.
532704716
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1489921585
Short name T168
Test name
Test status
Simulation time 61690601 ps
CPU time 1.18 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 196028 kb
Host smart-2a104ae4-ea8d-4966-b91e-6ddd4bf3e430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489921585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1489921585
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1852006024
Short name T164
Test name
Test status
Simulation time 115525410 ps
CPU time 1.25 seconds
Started Mar 03 12:40:05 PM PST 24
Finished Mar 03 12:40:07 PM PST 24
Peak memory 197100 kb
Host smart-a703eb56-fd23-4ddb-9170-803a8b3dc877
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852006024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1852006024
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2228710624
Short name T443
Test name
Test status
Simulation time 253741599 ps
CPU time 3 seconds
Started Mar 03 12:40:05 PM PST 24
Finished Mar 03 12:40:08 PM PST 24
Peak memory 198040 kb
Host smart-b8b90d8b-b0b4-47db-8018-5551701dfac8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228710624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2228710624
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2380616855
Short name T126
Test name
Test status
Simulation time 35105989 ps
CPU time 1.06 seconds
Started Mar 03 12:40:01 PM PST 24
Finished Mar 03 12:40:02 PM PST 24
Peak memory 195544 kb
Host smart-105a4a25-141e-4381-ad9c-b71fea8cf8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380616855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2380616855
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.4074965042
Short name T591
Test name
Test status
Simulation time 57451386 ps
CPU time 0.95 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:08 PM PST 24
Peak memory 196268 kb
Host smart-342e6370-b700-440d-9ecf-4bd0edf9aeef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074965042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.4074965042
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3715228081
Short name T276
Test name
Test status
Simulation time 8261235800 ps
CPU time 56.29 seconds
Started Mar 03 12:40:02 PM PST 24
Finished Mar 03 12:40:59 PM PST 24
Peak memory 198248 kb
Host smart-b8c2a745-5e39-4984-97ad-add1db725ea0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715228081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3715228081
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1455733531
Short name T534
Test name
Test status
Simulation time 37332800 ps
CPU time 0.57 seconds
Started Mar 03 12:40:11 PM PST 24
Finished Mar 03 12:40:12 PM PST 24
Peak memory 194168 kb
Host smart-7507484d-6216-444d-b430-0279531be0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455733531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1455733531
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3092518876
Short name T414
Test name
Test status
Simulation time 54940324 ps
CPU time 0.86 seconds
Started Mar 03 12:39:56 PM PST 24
Finished Mar 03 12:39:57 PM PST 24
Peak memory 196724 kb
Host smart-69c04bf7-f166-4352-a639-50f78d4e3388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092518876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3092518876
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2799261126
Short name T427
Test name
Test status
Simulation time 694464045 ps
CPU time 18.72 seconds
Started Mar 03 12:40:05 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 197104 kb
Host smart-3d8d152d-435c-46cb-9e01-86517da754a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799261126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2799261126
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1822935901
Short name T539
Test name
Test status
Simulation time 39042452 ps
CPU time 0.73 seconds
Started Mar 03 12:40:26 PM PST 24
Finished Mar 03 12:40:27 PM PST 24
Peak memory 194720 kb
Host smart-a29f348e-e8e2-4277-b781-38b2cf409063
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822935901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1822935901
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.945173549
Short name T553
Test name
Test status
Simulation time 20228743 ps
CPU time 0.67 seconds
Started Mar 03 12:40:17 PM PST 24
Finished Mar 03 12:40:19 PM PST 24
Peak memory 194268 kb
Host smart-6dd728e9-10df-4c37-bfe1-64023f671fbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945173549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.945173549
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.596895334
Short name T329
Test name
Test status
Simulation time 136647500 ps
CPU time 2.6 seconds
Started Mar 03 12:40:08 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 196480 kb
Host smart-4fc78246-d5a5-4ced-8191-2d6b6b0308a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596895334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.596895334
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1065185739
Short name T364
Test name
Test status
Simulation time 45633647 ps
CPU time 1.47 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 196948 kb
Host smart-24c2031b-6b72-4c30-9eee-27bb2c9688f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065185739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1065185739
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3558457667
Short name T119
Test name
Test status
Simulation time 34663859 ps
CPU time 0.85 seconds
Started Mar 03 12:40:19 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 196616 kb
Host smart-fd408c89-9978-447f-afdf-4031fdecebd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558457667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3558457667
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3172102845
Short name T616
Test name
Test status
Simulation time 23431708 ps
CPU time 0.97 seconds
Started Mar 03 12:40:07 PM PST 24
Finished Mar 03 12:40:08 PM PST 24
Peak memory 196644 kb
Host smart-e065e606-b894-4057-85be-3bb136ab363a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172102845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3172102845
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2059568860
Short name T326
Test name
Test status
Simulation time 316970060 ps
CPU time 5.15 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:28 PM PST 24
Peak memory 197784 kb
Host smart-7510e94b-3b3d-44d9-8d3e-889cce501c0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059568860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2059568860
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1433739302
Short name T402
Test name
Test status
Simulation time 226276033 ps
CPU time 1.07 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 195852 kb
Host smart-defd2d38-cb0c-4794-8b40-95a1a034c4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433739302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1433739302
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.42054016
Short name T247
Test name
Test status
Simulation time 37794728 ps
CPU time 0.97 seconds
Started Mar 03 12:40:08 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 197288 kb
Host smart-25cf537b-9bf0-43bb-b5b5-90b95d04af17
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42054016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.42054016
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1205329031
Short name T439
Test name
Test status
Simulation time 5876226513 ps
CPU time 83.97 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:41:44 PM PST 24
Peak memory 198228 kb
Host smart-4a4c4237-0b33-4ef3-ac98-7996da94d267
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205329031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1205329031
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.1138173285
Short name T58
Test name
Test status
Simulation time 26046632547 ps
CPU time 265.34 seconds
Started Mar 03 12:40:12 PM PST 24
Finished Mar 03 12:44:38 PM PST 24
Peak memory 198400 kb
Host smart-ca1ffd8b-f208-4398-9456-3eaf1f365bdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1138173285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.1138173285
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3003659860
Short name T385
Test name
Test status
Simulation time 12975750 ps
CPU time 0.56 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 194776 kb
Host smart-c124e76f-a064-4861-aa4d-a38d54c6e20f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003659860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3003659860
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3304487206
Short name T679
Test name
Test status
Simulation time 113908021 ps
CPU time 0.81 seconds
Started Mar 03 12:40:13 PM PST 24
Finished Mar 03 12:40:15 PM PST 24
Peak memory 196020 kb
Host smart-00672b96-9413-4020-a10a-fa02d9322f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304487206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3304487206
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1065020649
Short name T103
Test name
Test status
Simulation time 341613064 ps
CPU time 11.19 seconds
Started Mar 03 12:40:08 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 196916 kb
Host smart-d277f50e-0cc8-437b-ba15-ea91808fb218
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065020649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1065020649
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3186576782
Short name T294
Test name
Test status
Simulation time 350024494 ps
CPU time 0.65 seconds
Started Mar 03 12:40:09 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 195124 kb
Host smart-6de7f583-a973-46cc-ae4c-c5f01b1b841f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186576782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3186576782
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.541981077
Short name T143
Test name
Test status
Simulation time 95779695 ps
CPU time 1.29 seconds
Started Mar 03 12:40:13 PM PST 24
Finished Mar 03 12:40:15 PM PST 24
Peak memory 196076 kb
Host smart-14c79ca9-7e2b-41b7-a103-136940a238c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541981077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.541981077
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1419723163
Short name T486
Test name
Test status
Simulation time 36006466 ps
CPU time 1.54 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:19 PM PST 24
Peak memory 197036 kb
Host smart-8d91ccac-432a-408c-8b31-a00ef73a8d80
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419723163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1419723163
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3532581844
Short name T117
Test name
Test status
Simulation time 1083399912 ps
CPU time 2.46 seconds
Started Mar 03 12:40:12 PM PST 24
Finished Mar 03 12:40:15 PM PST 24
Peak memory 196572 kb
Host smart-2678c91d-c09c-4a2f-9396-52b05949af99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532581844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3532581844
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.877343935
Short name T373
Test name
Test status
Simulation time 158750686 ps
CPU time 1.02 seconds
Started Mar 03 12:40:04 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 195904 kb
Host smart-e1fed4d7-7d1d-4dcd-ad10-a48f5cb2b960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877343935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.877343935
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.830597862
Short name T582
Test name
Test status
Simulation time 36560644 ps
CPU time 1.18 seconds
Started Mar 03 12:40:21 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 197108 kb
Host smart-3095d4a8-ee43-4080-b286-9fa6d4716fd6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830597862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.830597862
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2578174100
Short name T225
Test name
Test status
Simulation time 444516233 ps
CPU time 4.75 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 197960 kb
Host smart-4f0ba447-8581-47fb-a917-0421d0612d91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578174100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2578174100
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2159942171
Short name T239
Test name
Test status
Simulation time 31106205 ps
CPU time 0.78 seconds
Started Mar 03 12:40:42 PM PST 24
Finished Mar 03 12:40:42 PM PST 24
Peak memory 195204 kb
Host smart-0efbd1f2-7f76-4dff-b887-b7c655c59367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159942171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2159942171
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3065009573
Short name T639
Test name
Test status
Simulation time 58225196 ps
CPU time 1.24 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:22 PM PST 24
Peak memory 196844 kb
Host smart-0eca25ca-fb2a-4e44-a879-8ffed6002cb7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065009573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3065009573
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3703460335
Short name T435
Test name
Test status
Simulation time 24362908607 ps
CPU time 236.92 seconds
Started Mar 03 12:40:14 PM PST 24
Finished Mar 03 12:44:17 PM PST 24
Peak memory 198256 kb
Host smart-8af5cd0b-fc48-4d6b-8b88-dff9362e3170
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703460335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3703460335
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.139599373
Short name T497
Test name
Test status
Simulation time 16105345 ps
CPU time 0.57 seconds
Started Mar 03 12:40:11 PM PST 24
Finished Mar 03 12:40:12 PM PST 24
Peak memory 194288 kb
Host smart-82fcc7d2-a692-423e-8a5f-84918166f2bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139599373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.139599373
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2104034335
Short name T113
Test name
Test status
Simulation time 143573764 ps
CPU time 0.78 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 195412 kb
Host smart-3d69a2fc-c4ea-4869-bbe0-c1a4f385a620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104034335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2104034335
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1235301583
Short name T644
Test name
Test status
Simulation time 268012291 ps
CPU time 13.74 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:38 PM PST 24
Peak memory 198164 kb
Host smart-3bce6918-2aba-46d2-a7a0-6362594c68f1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235301583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1235301583
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3480743106
Short name T358
Test name
Test status
Simulation time 26332453 ps
CPU time 0.59 seconds
Started Mar 03 12:40:13 PM PST 24
Finished Mar 03 12:40:15 PM PST 24
Peak memory 194204 kb
Host smart-fb2c5930-56aa-47c1-aacf-806e2de4ad4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480743106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3480743106
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.299133335
Short name T692
Test name
Test status
Simulation time 217136323 ps
CPU time 1 seconds
Started Mar 03 12:40:14 PM PST 24
Finished Mar 03 12:40:16 PM PST 24
Peak memory 196532 kb
Host smart-e6654940-9ab8-4db8-9c1e-f393fee1a58c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299133335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.299133335
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3553861701
Short name T626
Test name
Test status
Simulation time 24798396 ps
CPU time 1.16 seconds
Started Mar 03 12:40:03 PM PST 24
Finished Mar 03 12:40:04 PM PST 24
Peak memory 197328 kb
Host smart-b165f4b0-11dc-46ff-9ffc-184477cbb99e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553861701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3553861701
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.929392699
Short name T501
Test name
Test status
Simulation time 92901837 ps
CPU time 2.57 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:26 PM PST 24
Peak memory 198116 kb
Host smart-f0b854f4-f52a-4cf8-b3ac-e821863c7e26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929392699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
929392699
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3152451883
Short name T136
Test name
Test status
Simulation time 49109408 ps
CPU time 1.14 seconds
Started Mar 03 12:40:19 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 195840 kb
Host smart-ad0e4988-68f0-4533-aeb7-80eeab4041ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152451883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3152451883
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.227476359
Short name T445
Test name
Test status
Simulation time 40354008 ps
CPU time 0.97 seconds
Started Mar 03 12:40:07 PM PST 24
Finished Mar 03 12:40:09 PM PST 24
Peak memory 195868 kb
Host smart-7a57f3d2-b50a-4458-8568-3b44656dded4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227476359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.227476359
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.848035759
Short name T107
Test name
Test status
Simulation time 277071265 ps
CPU time 4.26 seconds
Started Mar 03 12:40:13 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 197452 kb
Host smart-3e2a0d52-dfd9-4f93-8ec3-318fd9313c81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848035759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.848035759
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.4112719316
Short name T361
Test name
Test status
Simulation time 56442985 ps
CPU time 1.21 seconds
Started Mar 03 12:40:05 PM PST 24
Finished Mar 03 12:40:06 PM PST 24
Peak memory 196760 kb
Host smart-3c35241d-020c-4519-a7cd-012402a6a1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112719316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.4112719316
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1327382876
Short name T280
Test name
Test status
Simulation time 51412688 ps
CPU time 1.29 seconds
Started Mar 03 12:40:12 PM PST 24
Finished Mar 03 12:40:14 PM PST 24
Peak memory 195540 kb
Host smart-502bba17-5479-4574-8ae7-1732646eeb31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327382876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1327382876
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.4138123339
Short name T307
Test name
Test status
Simulation time 10237070992 ps
CPU time 54.52 seconds
Started Mar 03 12:40:12 PM PST 24
Finished Mar 03 12:41:12 PM PST 24
Peak memory 198336 kb
Host smart-d257177a-75a5-42c4-9223-3a084d244477
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138123339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.4138123339
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3716453507
Short name T34
Test name
Test status
Simulation time 12821865 ps
CPU time 0.58 seconds
Started Mar 03 12:40:19 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 194012 kb
Host smart-994ff288-9610-4bfa-a747-aa943c87529d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716453507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3716453507
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3105843251
Short name T50
Test name
Test status
Simulation time 116729033 ps
CPU time 0.81 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:08 PM PST 24
Peak memory 196136 kb
Host smart-a0717b57-b82a-4129-b992-32761a6d94c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105843251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3105843251
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.4276984572
Short name T244
Test name
Test status
Simulation time 817089643 ps
CPU time 27.56 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:35 PM PST 24
Peak memory 198116 kb
Host smart-d71ea471-38a7-47d8-8d8d-a298538db8f6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276984572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.4276984572
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.804944494
Short name T581
Test name
Test status
Simulation time 203687265 ps
CPU time 1.12 seconds
Started Mar 03 12:40:11 PM PST 24
Finished Mar 03 12:40:13 PM PST 24
Peak memory 196924 kb
Host smart-70f3c518-ae16-4060-a6bc-5e8f80aebcd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804944494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.804944494
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.828756619
Short name T447
Test name
Test status
Simulation time 217162656 ps
CPU time 1.05 seconds
Started Mar 03 12:40:18 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 196140 kb
Host smart-f9182076-1108-4191-be19-d8337ab36264
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828756619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.828756619
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3443963566
Short name T602
Test name
Test status
Simulation time 192638235 ps
CPU time 3.12 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 198188 kb
Host smart-c4c91093-6e8f-496d-a89c-85f1016da5ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443963566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3443963566
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.200413866
Short name T151
Test name
Test status
Simulation time 293154436 ps
CPU time 2.19 seconds
Started Mar 03 12:40:21 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 197084 kb
Host smart-dea44192-95dd-4619-94ca-13940b1ee619
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200413866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
200413866
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1286046228
Short name T521
Test name
Test status
Simulation time 42765911 ps
CPU time 0.67 seconds
Started Mar 03 12:40:09 PM PST 24
Finished Mar 03 12:40:11 PM PST 24
Peak memory 194236 kb
Host smart-101a6acf-f6bc-448b-aed9-6066c910394e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286046228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1286046228
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.804425425
Short name T560
Test name
Test status
Simulation time 28198856 ps
CPU time 0.75 seconds
Started Mar 03 12:40:11 PM PST 24
Finished Mar 03 12:40:12 PM PST 24
Peak memory 196116 kb
Host smart-d6dc651d-5a91-4cdd-b585-265545741f91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804425425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.804425425
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1683593401
Short name T642
Test name
Test status
Simulation time 630139148 ps
CPU time 1.85 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:22 PM PST 24
Peak memory 198060 kb
Host smart-e4c0b2f8-72e1-4076-9b53-abaaef5d47b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683593401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1683593401
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1381777787
Short name T699
Test name
Test status
Simulation time 139205156 ps
CPU time 1.19 seconds
Started Mar 03 12:40:12 PM PST 24
Finished Mar 03 12:40:13 PM PST 24
Peak memory 195896 kb
Host smart-7e218744-d80d-4133-b2fa-6a2bf938dc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381777787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1381777787
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1004351948
Short name T413
Test name
Test status
Simulation time 149397027 ps
CPU time 1.32 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:22 PM PST 24
Peak memory 195828 kb
Host smart-485aa17a-f01a-4d20-8759-83ab2f3ca4aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004351948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1004351948
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.270958114
Short name T5
Test name
Test status
Simulation time 2788267802 ps
CPU time 33.05 seconds
Started Mar 03 12:40:12 PM PST 24
Finished Mar 03 12:40:46 PM PST 24
Peak memory 198300 kb
Host smart-c12e080c-6f0d-43d8-8d78-716c81906cfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270958114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.270958114
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.54194781
Short name T161
Test name
Test status
Simulation time 18357726 ps
CPU time 0.56 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 194288 kb
Host smart-1cda4fe0-326b-400d-99b8-b5d10dc98515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54194781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.54194781
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3930564911
Short name T311
Test name
Test status
Simulation time 120166085 ps
CPU time 0.85 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 196292 kb
Host smart-053305f3-feb5-4666-a8ce-f7f2c1ba4921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930564911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3930564911
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.969390829
Short name T527
Test name
Test status
Simulation time 770478166 ps
CPU time 25.67 seconds
Started Mar 03 12:40:17 PM PST 24
Finished Mar 03 12:40:43 PM PST 24
Peak memory 197000 kb
Host smart-5a20d181-55aa-492a-9da8-d73d4517bbfc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969390829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.969390829
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.4116432912
Short name T10
Test name
Test status
Simulation time 394829476 ps
CPU time 1.11 seconds
Started Mar 03 12:40:39 PM PST 24
Finished Mar 03 12:40:40 PM PST 24
Peak memory 197856 kb
Host smart-d0d02e3f-f876-4260-b75d-a65f974c112b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116432912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.4116432912
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2050717106
Short name T194
Test name
Test status
Simulation time 285624468 ps
CPU time 1.11 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 196132 kb
Host smart-adc3c713-46c1-4638-bb0f-e02d93b13652
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050717106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2050717106
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2101554497
Short name T243
Test name
Test status
Simulation time 179223610 ps
CPU time 1.89 seconds
Started Mar 03 12:40:09 PM PST 24
Finished Mar 03 12:40:12 PM PST 24
Peak memory 198208 kb
Host smart-a19512b0-91f2-4ab3-8a9f-e1f5d746a646
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101554497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2101554497
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.771536234
Short name T192
Test name
Test status
Simulation time 472682152 ps
CPU time 2.46 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:19 PM PST 24
Peak memory 198440 kb
Host smart-5e2cce2b-c886-4359-9945-12ca1f3dff32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771536234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
771536234
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.144751295
Short name T369
Test name
Test status
Simulation time 267663835 ps
CPU time 1.21 seconds
Started Mar 03 12:40:15 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 197124 kb
Host smart-8689c7fe-0f88-4493-973e-9ee5b577f1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144751295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.144751295
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1702438396
Short name T110
Test name
Test status
Simulation time 126868246 ps
CPU time 1.28 seconds
Started Mar 03 12:40:06 PM PST 24
Finished Mar 03 12:40:08 PM PST 24
Peak memory 197056 kb
Host smart-5aa95102-23e8-4a40-a47f-6794aed1b219
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702438396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1702438396
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1609746282
Short name T54
Test name
Test status
Simulation time 121464392 ps
CPU time 5.28 seconds
Started Mar 03 12:40:12 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 198056 kb
Host smart-d0f3461b-286f-43d1-98a9-4faf5e6c4607
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609746282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1609746282
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1003195290
Short name T105
Test name
Test status
Simulation time 546382666 ps
CPU time 0.95 seconds
Started Mar 03 12:40:12 PM PST 24
Finished Mar 03 12:40:14 PM PST 24
Peak memory 196176 kb
Host smart-95b0ebcf-1d77-43ff-811c-5a5e55f226aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003195290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1003195290
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.603815568
Short name T436
Test name
Test status
Simulation time 236164271 ps
CPU time 1.39 seconds
Started Mar 03 12:40:18 PM PST 24
Finished Mar 03 12:40:20 PM PST 24
Peak memory 196956 kb
Host smart-d131ee1f-820a-4646-90f7-426ac668f101
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603815568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.603815568
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2441257230
Short name T426
Test name
Test status
Simulation time 5026896567 ps
CPU time 53.91 seconds
Started Mar 03 12:40:11 PM PST 24
Finished Mar 03 12:41:05 PM PST 24
Peak memory 198304 kb
Host smart-76edd8ac-2aa4-439a-a170-9848e0e1ef70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441257230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2441257230
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.1586782204
Short name T668
Test name
Test status
Simulation time 184936004114 ps
CPU time 2052.34 seconds
Started Mar 03 12:40:31 PM PST 24
Finished Mar 03 01:14:43 PM PST 24
Peak memory 198432 kb
Host smart-9fb8a7b2-d3d3-4fc8-bcdf-d056f1e64952
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1586782204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.1586782204
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2636783132
Short name T208
Test name
Test status
Simulation time 37648096 ps
CPU time 0.57 seconds
Started Mar 03 12:40:25 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 193956 kb
Host smart-4e0e0147-94b5-4bae-983e-d1e3aa50b0b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636783132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2636783132
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.2082833792
Short name T160
Test name
Test status
Simulation time 54661549 ps
CPU time 0.87 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 196432 kb
Host smart-d8044f55-0495-4bb8-a702-766a038679a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082833792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.2082833792
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2102984243
Short name T228
Test name
Test status
Simulation time 611050884 ps
CPU time 21.91 seconds
Started Mar 03 12:40:21 PM PST 24
Finished Mar 03 12:40:44 PM PST 24
Peak memory 196996 kb
Host smart-b149b545-93df-4fbc-a754-f89c004dad30
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102984243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2102984243
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1611454049
Short name T431
Test name
Test status
Simulation time 31380721 ps
CPU time 0.65 seconds
Started Mar 03 12:40:39 PM PST 24
Finished Mar 03 12:40:41 PM PST 24
Peak memory 194596 kb
Host smart-9a1dc1ce-547f-410a-a00b-c4d702d433df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611454049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1611454049
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.3972585617
Short name T52
Test name
Test status
Simulation time 39203528 ps
CPU time 1.03 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 195808 kb
Host smart-4e29b51d-6fd8-41be-bc3b-efd3bf90b11c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972585617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.3972585617
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2130203407
Short name T185
Test name
Test status
Simulation time 55221079 ps
CPU time 2.29 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 198032 kb
Host smart-eb5d7f14-945a-4d18-abba-f5713409cb58
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130203407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2130203407
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.296031932
Short name T262
Test name
Test status
Simulation time 91924085 ps
CPU time 2.65 seconds
Started Mar 03 12:40:03 PM PST 24
Finished Mar 03 12:40:05 PM PST 24
Peak memory 197272 kb
Host smart-98e2ab89-c5dc-40af-be74-b9228cdf530f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296031932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger.
296031932
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.808149790
Short name T121
Test name
Test status
Simulation time 17729099 ps
CPU time 0.76 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 195248 kb
Host smart-24bf3b02-bd8c-4b9e-8ede-d753e58138d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808149790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.808149790
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3535376420
Short name T322
Test name
Test status
Simulation time 133090122 ps
CPU time 0.81 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 196612 kb
Host smart-32ad2ac5-d0ea-41fa-a74b-5aa6373b5402
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535376420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3535376420
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1726520427
Short name T678
Test name
Test status
Simulation time 235254598 ps
CPU time 3.74 seconds
Started Mar 03 12:40:54 PM PST 24
Finished Mar 03 12:40:58 PM PST 24
Peak memory 198040 kb
Host smart-5d97a62c-f8ca-4ae5-910f-05fa8da5b568
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726520427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1726520427
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1935551150
Short name T205
Test name
Test status
Simulation time 57363664 ps
CPU time 1.07 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:26 PM PST 24
Peak memory 196624 kb
Host smart-0cd96751-91e7-4cd8-a7ca-f550647d4c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935551150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1935551150
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2264432889
Short name T221
Test name
Test status
Simulation time 252745252 ps
CPU time 1.11 seconds
Started Mar 03 12:40:12 PM PST 24
Finished Mar 03 12:40:14 PM PST 24
Peak memory 196320 kb
Host smart-92c5e41f-7c2c-4a2e-9c28-92daf4ba1846
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264432889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2264432889
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1615742972
Short name T619
Test name
Test status
Simulation time 12328302854 ps
CPU time 169.36 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:43:13 PM PST 24
Peak memory 198160 kb
Host smart-21ec372d-a1cc-492a-bf93-b8eda367f436
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615742972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1615742972
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.206335603
Short name T57
Test name
Test status
Simulation time 318914692894 ps
CPU time 1181.34 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 01:00:04 PM PST 24
Peak memory 206628 kb
Host smart-716c5df7-8ad7-4d63-b386-1e8cf00d62a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=206335603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.206335603
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.971550862
Short name T638
Test name
Test status
Simulation time 35441987 ps
CPU time 0.56 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 194652 kb
Host smart-799df7f4-743f-4d07-9120-8abef5bcf15e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971550862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.971550862
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3840008347
Short name T16
Test name
Test status
Simulation time 151094809 ps
CPU time 0.57 seconds
Started Mar 03 12:40:13 PM PST 24
Finished Mar 03 12:40:14 PM PST 24
Peak memory 193904 kb
Host smart-07eac65e-8584-49bf-9e6b-9cf8a259c192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840008347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3840008347
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2539637006
Short name T140
Test name
Test status
Simulation time 3362446606 ps
CPU time 24.82 seconds
Started Mar 03 12:40:25 PM PST 24
Finished Mar 03 12:40:50 PM PST 24
Peak memory 196988 kb
Host smart-79e9e13a-d90d-41dd-9cb7-472ffe0f3cde
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539637006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2539637006
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2038995262
Short name T21
Test name
Test status
Simulation time 348405089 ps
CPU time 0.83 seconds
Started Mar 03 12:40:44 PM PST 24
Finished Mar 03 12:40:45 PM PST 24
Peak memory 196704 kb
Host smart-c5538335-0bd1-4014-b798-51c44a4c6612
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038995262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2038995262
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3360598079
Short name T127
Test name
Test status
Simulation time 31771279 ps
CPU time 0.72 seconds
Started Mar 03 12:40:12 PM PST 24
Finished Mar 03 12:40:14 PM PST 24
Peak memory 196144 kb
Host smart-17a3da7b-78e2-4e59-af44-a53d07aea161
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360598079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3360598079
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.634024404
Short name T550
Test name
Test status
Simulation time 56851633 ps
CPU time 2.14 seconds
Started Mar 03 12:40:19 PM PST 24
Finished Mar 03 12:40:22 PM PST 24
Peak memory 198152 kb
Host smart-f10150d4-707c-410f-b01c-1ca312908eb9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634024404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.634024404
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2179224424
Short name T588
Test name
Test status
Simulation time 164947683 ps
CPU time 2.97 seconds
Started Mar 03 12:40:21 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 195972 kb
Host smart-a56aa15c-bb3f-4076-8301-c4981c22764d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179224424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2179224424
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1645644415
Short name T288
Test name
Test status
Simulation time 337603094 ps
CPU time 1.04 seconds
Started Mar 03 12:40:17 PM PST 24
Finished Mar 03 12:40:19 PM PST 24
Peak memory 196168 kb
Host smart-91e29629-7275-438e-a8d4-3614b1b9d360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645644415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1645644415
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.4242823170
Short name T196
Test name
Test status
Simulation time 260952677 ps
CPU time 1.35 seconds
Started Mar 03 12:40:25 PM PST 24
Finished Mar 03 12:40:27 PM PST 24
Peak memory 198100 kb
Host smart-d5221a93-bc71-4fb7-838b-e279c00f5640
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242823170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.4242823170
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.479260152
Short name T541
Test name
Test status
Simulation time 1535748211 ps
CPU time 2.81 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 198080 kb
Host smart-3eb868a3-5528-4b9e-b282-02016f012399
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479260152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.479260152
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2361099264
Short name T419
Test name
Test status
Simulation time 143288189 ps
CPU time 1.2 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:22 PM PST 24
Peak memory 196908 kb
Host smart-ae98d2ed-0381-489e-a0a6-4149073c2a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361099264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2361099264
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3830063384
Short name T559
Test name
Test status
Simulation time 48932515 ps
CPU time 0.88 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 195652 kb
Host smart-8dccd563-8a1b-4735-97f6-12b41a87ed36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830063384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3830063384
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.60897879
Short name T423
Test name
Test status
Simulation time 11097729837 ps
CPU time 67.65 seconds
Started Mar 03 12:40:21 PM PST 24
Finished Mar 03 12:41:29 PM PST 24
Peak memory 198184 kb
Host smart-502eed30-8340-4e2c-8f3e-31346fb4b44c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60897879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gp
io_stress_all.60897879
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.335260178
Short name T56
Test name
Test status
Simulation time 43325418836 ps
CPU time 1371.44 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 01:03:16 PM PST 24
Peak memory 198396 kb
Host smart-e06ed032-5f68-466f-adf0-0fe5bb3d264d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=335260178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.335260178
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.305096472
Short name T24
Test name
Test status
Simulation time 53271002 ps
CPU time 0.59 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 194232 kb
Host smart-4e0a2171-c24e-4cd7-a477-2e01933a1b1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305096472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.305096472
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2469145346
Short name T490
Test name
Test status
Simulation time 43711330 ps
CPU time 0.87 seconds
Started Mar 03 12:40:21 PM PST 24
Finished Mar 03 12:40:22 PM PST 24
Peak memory 196336 kb
Host smart-41e6cd7f-ca1d-454b-9a52-4f9c4760af02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469145346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2469145346
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1429974296
Short name T522
Test name
Test status
Simulation time 2707864080 ps
CPU time 18.8 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:41 PM PST 24
Peak memory 197168 kb
Host smart-2a9e9a9d-21d9-4cdd-9420-a287510d8015
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429974296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1429974296
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3879591181
Short name T407
Test name
Test status
Simulation time 33515433 ps
CPU time 0.73 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 195888 kb
Host smart-f0c1fb30-fe26-4371-b853-f21e3214bd0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879591181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3879591181
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.657244679
Short name T438
Test name
Test status
Simulation time 49555702 ps
CPU time 0.89 seconds
Started Mar 03 12:40:21 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 197532 kb
Host smart-3b7b9310-7b4e-413d-a52b-bad50c3757b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657244679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.657244679
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3204497843
Short name T323
Test name
Test status
Simulation time 66292081 ps
CPU time 1.39 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:26 PM PST 24
Peak memory 196376 kb
Host smart-2adcc1c6-3050-4729-be4f-0a4e53a0c132
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204497843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3204497843
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2858840190
Short name T458
Test name
Test status
Simulation time 133915014 ps
CPU time 1.53 seconds
Started Mar 03 12:40:21 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 196064 kb
Host smart-ebf6cb83-8c0a-4629-a46d-2265a805bb95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858840190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2858840190
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.389839904
Short name T256
Test name
Test status
Simulation time 62658418 ps
CPU time 1.21 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:21 PM PST 24
Peak memory 196220 kb
Host smart-4b2be114-34ef-4e2b-9a81-fd09f50b1e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389839904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.389839904
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2307966297
Short name T281
Test name
Test status
Simulation time 47867603 ps
CPU time 1.13 seconds
Started Mar 03 12:40:29 PM PST 24
Finished Mar 03 12:40:30 PM PST 24
Peak memory 197200 kb
Host smart-f32c0008-aba9-4f1a-ba2d-1f79e19d6356
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307966297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2307966297
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3358369872
Short name T223
Test name
Test status
Simulation time 296293170 ps
CPU time 4.99 seconds
Started Mar 03 12:40:26 PM PST 24
Finished Mar 03 12:40:32 PM PST 24
Peak memory 198052 kb
Host smart-e98b44f3-becb-44c9-985a-ad92e24fad7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358369872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3358369872
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2579283679
Short name T248
Test name
Test status
Simulation time 47173976 ps
CPU time 0.89 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 195232 kb
Host smart-617f2465-c301-416f-bab2-50ce179819ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579283679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2579283679
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.873855743
Short name T578
Test name
Test status
Simulation time 87552178 ps
CPU time 0.82 seconds
Started Mar 03 12:40:28 PM PST 24
Finished Mar 03 12:40:29 PM PST 24
Peak memory 196412 kb
Host smart-8c9a3836-5291-4d97-a1bc-e0ba6c51bb4e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873855743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.873855743
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3897108792
Short name T583
Test name
Test status
Simulation time 7184246065 ps
CPU time 104.47 seconds
Started Mar 03 12:40:43 PM PST 24
Finished Mar 03 12:42:28 PM PST 24
Peak memory 198260 kb
Host smart-cb3f15e1-1fac-4828-a029-f59a982d695d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897108792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3897108792
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3394653271
Short name T416
Test name
Test status
Simulation time 25516131 ps
CPU time 0.56 seconds
Started Mar 03 12:40:25 PM PST 24
Finished Mar 03 12:40:26 PM PST 24
Peak memory 194216 kb
Host smart-1c5b9d7c-d1f5-4ac9-9502-db0cf1cd0413
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394653271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3394653271
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3127704562
Short name T149
Test name
Test status
Simulation time 33787134 ps
CPU time 0.8 seconds
Started Mar 03 12:40:48 PM PST 24
Finished Mar 03 12:40:49 PM PST 24
Peak memory 195352 kb
Host smart-dea67f8d-69c9-4d16-baed-61c168678a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127704562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3127704562
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2409569213
Short name T111
Test name
Test status
Simulation time 1811447920 ps
CPU time 23.45 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:47 PM PST 24
Peak memory 197088 kb
Host smart-90313ed7-0cc7-462c-8506-503819910da8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409569213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2409569213
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.201769422
Short name T532
Test name
Test status
Simulation time 146712516 ps
CPU time 0.68 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 194796 kb
Host smart-6b726eb1-df2a-4798-b413-7f8f348897ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201769422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.201769422
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2645263230
Short name T446
Test name
Test status
Simulation time 62875404 ps
CPU time 0.99 seconds
Started Mar 03 12:40:36 PM PST 24
Finished Mar 03 12:40:37 PM PST 24
Peak memory 196220 kb
Host smart-547b713a-91b1-4926-9b0f-74ece695c317
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645263230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2645263230
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.444260299
Short name T186
Test name
Test status
Simulation time 296628331 ps
CPU time 2.83 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:27 PM PST 24
Peak memory 198176 kb
Host smart-56818f81-d38c-4d70-bbe7-07a75639cb1c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444260299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.444260299
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3761214495
Short name T238
Test name
Test status
Simulation time 408582908 ps
CPU time 2.01 seconds
Started Mar 03 12:40:27 PM PST 24
Finished Mar 03 12:40:30 PM PST 24
Peak memory 196208 kb
Host smart-c1232693-b5ec-4b16-829e-d14290979b07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761214495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3761214495
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1373695914
Short name T166
Test name
Test status
Simulation time 32290315 ps
CPU time 1.08 seconds
Started Mar 03 12:40:15 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 196868 kb
Host smart-6ef7e2f7-bb3f-42aa-838e-a5516020f135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373695914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1373695914
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1605546232
Short name T684
Test name
Test status
Simulation time 306054236 ps
CPU time 1.05 seconds
Started Mar 03 12:40:37 PM PST 24
Finished Mar 03 12:40:39 PM PST 24
Peak memory 196040 kb
Host smart-817e6c69-48c0-46bc-9f36-ed4cff9aa0ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605546232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1605546232
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2609439880
Short name T568
Test name
Test status
Simulation time 155634957 ps
CPU time 1.95 seconds
Started Mar 03 12:40:32 PM PST 24
Finished Mar 03 12:40:34 PM PST 24
Peak memory 198048 kb
Host smart-1e9fb7a8-a59e-41af-b583-cbadb45aaed9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609439880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2609439880
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2251250990
Short name T210
Test name
Test status
Simulation time 145333224 ps
CPU time 1.31 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 196956 kb
Host smart-f6f38cb3-3692-41f4-bc99-2ef6d44edcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251250990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2251250990
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.838903423
Short name T99
Test name
Test status
Simulation time 49686442 ps
CPU time 1.01 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 195788 kb
Host smart-61cb0d1f-9eeb-4f3a-99ba-99c5b0c879d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838903423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.838903423
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1307325837
Short name T472
Test name
Test status
Simulation time 30461961855 ps
CPU time 85.76 seconds
Started Mar 03 12:40:09 PM PST 24
Finished Mar 03 12:41:36 PM PST 24
Peak memory 198232 kb
Host smart-52df22d9-29cd-44ac-9f46-9a3165a0ba31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307325837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1307325837
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.363521088
Short name T430
Test name
Test status
Simulation time 33553172 ps
CPU time 0.57 seconds
Started Mar 03 12:39:08 PM PST 24
Finished Mar 03 12:39:09 PM PST 24
Peak memory 195068 kb
Host smart-21f74706-eea5-49e8-9886-4a92cc64aab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363521088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.363521088
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3044176534
Short name T491
Test name
Test status
Simulation time 189015844 ps
CPU time 0.87 seconds
Started Mar 03 12:39:02 PM PST 24
Finished Mar 03 12:39:03 PM PST 24
Peak memory 196612 kb
Host smart-71de6574-6b01-47f9-8503-c787caf858d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044176534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3044176534
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2415092578
Short name T600
Test name
Test status
Simulation time 2232177761 ps
CPU time 16.79 seconds
Started Mar 03 12:38:56 PM PST 24
Finished Mar 03 12:39:13 PM PST 24
Peak memory 196960 kb
Host smart-ba5fa927-29a3-43dc-9e7c-62cf611191a7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415092578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2415092578
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.848417021
Short name T682
Test name
Test status
Simulation time 322140738 ps
CPU time 1.07 seconds
Started Mar 03 12:39:10 PM PST 24
Finished Mar 03 12:39:12 PM PST 24
Peak memory 198020 kb
Host smart-3354891a-5e54-46e6-b51d-7f09981a709d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848417021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.848417021
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.255646808
Short name T625
Test name
Test status
Simulation time 495621172 ps
CPU time 0.93 seconds
Started Mar 03 12:39:02 PM PST 24
Finished Mar 03 12:39:04 PM PST 24
Peak memory 196048 kb
Host smart-61a5251c-c1ef-4183-8fef-fd1c324e1c40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255646808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.255646808
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1793733406
Short name T518
Test name
Test status
Simulation time 198605823 ps
CPU time 1.08 seconds
Started Mar 03 12:38:56 PM PST 24
Finished Mar 03 12:38:58 PM PST 24
Peak memory 197316 kb
Host smart-7bc40e35-0a08-4693-90a9-2ca5f7b45565
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793733406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1793733406
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3424983819
Short name T440
Test name
Test status
Simulation time 70553167 ps
CPU time 1.62 seconds
Started Mar 03 12:39:01 PM PST 24
Finished Mar 03 12:39:04 PM PST 24
Peak memory 196232 kb
Host smart-441371c5-3744-43a2-b32e-737c23bfa805
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424983819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3424983819
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1875932277
Short name T146
Test name
Test status
Simulation time 82437861 ps
CPU time 0.97 seconds
Started Mar 03 12:38:55 PM PST 24
Finished Mar 03 12:38:57 PM PST 24
Peak memory 196044 kb
Host smart-45b14232-1ab1-4461-9d67-56d8b839763d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875932277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1875932277
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3073087027
Short name T167
Test name
Test status
Simulation time 69456884 ps
CPU time 0.78 seconds
Started Mar 03 12:38:57 PM PST 24
Finished Mar 03 12:38:58 PM PST 24
Peak memory 196432 kb
Host smart-2ac604c7-7088-4fc6-bab4-aff942225ebc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073087027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3073087027
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.559772199
Short name T543
Test name
Test status
Simulation time 9546748888 ps
CPU time 6.61 seconds
Started Mar 03 12:39:01 PM PST 24
Finished Mar 03 12:39:09 PM PST 24
Peak memory 198164 kb
Host smart-ce9144e9-3d26-46a3-937f-b8294478b6cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559772199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.559772199
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.796856046
Short name T187
Test name
Test status
Simulation time 54396623 ps
CPU time 1.39 seconds
Started Mar 03 12:39:10 PM PST 24
Finished Mar 03 12:39:12 PM PST 24
Peak memory 198080 kb
Host smart-051de4cf-e148-4769-bc00-676d703f9c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796856046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.796856046
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2759216256
Short name T382
Test name
Test status
Simulation time 368724689 ps
CPU time 1 seconds
Started Mar 03 12:39:02 PM PST 24
Finished Mar 03 12:39:04 PM PST 24
Peak memory 196384 kb
Host smart-162dd563-1aa8-46c0-bde7-8867298a5f72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759216256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2759216256
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3138954934
Short name T334
Test name
Test status
Simulation time 4542992587 ps
CPU time 57.81 seconds
Started Mar 03 12:39:00 PM PST 24
Finished Mar 03 12:40:00 PM PST 24
Peak memory 198176 kb
Host smart-4058d04b-8a51-4608-ae27-0f6161f91ac4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138954934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3138954934
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3528704034
Short name T535
Test name
Test status
Simulation time 23063101 ps
CPU time 0.56 seconds
Started Mar 03 12:39:15 PM PST 24
Finished Mar 03 12:39:23 PM PST 24
Peak memory 194296 kb
Host smart-91e0f483-e160-4415-92f7-b2ef48b4ca02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528704034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3528704034
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1527493160
Short name T505
Test name
Test status
Simulation time 329780607 ps
CPU time 0.75 seconds
Started Mar 03 12:39:01 PM PST 24
Finished Mar 03 12:39:07 PM PST 24
Peak memory 195256 kb
Host smart-5771ce17-3995-4e56-a220-d0e92f02d499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527493160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1527493160
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2083595515
Short name T547
Test name
Test status
Simulation time 182637535 ps
CPU time 6.9 seconds
Started Mar 03 12:39:09 PM PST 24
Finished Mar 03 12:39:16 PM PST 24
Peak memory 198212 kb
Host smart-8fe3f612-2187-4dd7-b185-da242107d097
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083595515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2083595515
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3108634998
Short name T347
Test name
Test status
Simulation time 27450876 ps
CPU time 0.74 seconds
Started Mar 03 12:39:20 PM PST 24
Finished Mar 03 12:39:22 PM PST 24
Peak memory 194784 kb
Host smart-7c9f2c06-8f93-4224-aa46-f71e8a9f6b50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108634998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3108634998
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2556526904
Short name T704
Test name
Test status
Simulation time 53267524 ps
CPU time 1.33 seconds
Started Mar 03 12:38:59 PM PST 24
Finished Mar 03 12:39:01 PM PST 24
Peak memory 197104 kb
Host smart-fa340397-027e-43c4-9c17-564251ac3cb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556526904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2556526904
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1143499892
Short name T176
Test name
Test status
Simulation time 39841311 ps
CPU time 1.02 seconds
Started Mar 03 12:39:02 PM PST 24
Finished Mar 03 12:39:04 PM PST 24
Peak memory 195508 kb
Host smart-0ba78578-2ca1-441b-9012-cb1cbb19cfa4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143499892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1143499892
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2504291356
Short name T428
Test name
Test status
Simulation time 44127473 ps
CPU time 0.98 seconds
Started Mar 03 12:39:13 PM PST 24
Finished Mar 03 12:39:16 PM PST 24
Peak memory 196064 kb
Host smart-4491c7ca-a9c1-411e-b153-49d77cb89e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504291356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2504291356
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.111125979
Short name T351
Test name
Test status
Simulation time 41808916 ps
CPU time 1.2 seconds
Started Mar 03 12:38:56 PM PST 24
Finished Mar 03 12:39:04 PM PST 24
Peak memory 196964 kb
Host smart-8707ac65-f2b7-4ecc-a93f-95a2c9faa575
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111125979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.111125979
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1338248170
Short name T357
Test name
Test status
Simulation time 228269804 ps
CPU time 2.82 seconds
Started Mar 03 12:39:15 PM PST 24
Finished Mar 03 12:39:23 PM PST 24
Peak memory 198044 kb
Host smart-9b2383d1-e896-492e-a22a-dc46ddab7b9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338248170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1338248170
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2281942226
Short name T217
Test name
Test status
Simulation time 31949228 ps
CPU time 0.97 seconds
Started Mar 03 12:39:10 PM PST 24
Finished Mar 03 12:39:12 PM PST 24
Peak memory 196512 kb
Host smart-54b4247f-e16d-4cf2-89b9-7043d27bf858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281942226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2281942226
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2447316385
Short name T408
Test name
Test status
Simulation time 129211417 ps
CPU time 0.74 seconds
Started Mar 03 12:38:58 PM PST 24
Finished Mar 03 12:38:59 PM PST 24
Peak memory 195088 kb
Host smart-fa124869-1525-49a2-be18-be20239177ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447316385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2447316385
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.937833664
Short name T494
Test name
Test status
Simulation time 6644301705 ps
CPU time 174.23 seconds
Started Mar 03 12:39:24 PM PST 24
Finished Mar 03 12:42:18 PM PST 24
Peak memory 198152 kb
Host smart-971c8786-b1fb-4b60-ac60-b0b03e07abc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937833664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.937833664
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.3098630157
Short name T60
Test name
Test status
Simulation time 234420898586 ps
CPU time 1391.87 seconds
Started Mar 03 12:39:13 PM PST 24
Finished Mar 03 01:02:27 PM PST 24
Peak memory 198328 kb
Host smart-c529851c-7bb0-43a7-a1ab-65c7d62b4043
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3098630157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.3098630157
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2534894774
Short name T289
Test name
Test status
Simulation time 22851905 ps
CPU time 0.61 seconds
Started Mar 03 12:39:13 PM PST 24
Finished Mar 03 12:39:15 PM PST 24
Peak memory 195740 kb
Host smart-c7e25cab-5fa6-4e72-8117-ec01df511a91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534894774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2534894774
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3213076722
Short name T195
Test name
Test status
Simulation time 33800650 ps
CPU time 0.61 seconds
Started Mar 03 12:39:15 PM PST 24
Finished Mar 03 12:39:24 PM PST 24
Peak memory 193984 kb
Host smart-cbb1ac71-3add-4a17-a9af-b14864c66ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213076722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3213076722
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.590983212
Short name T509
Test name
Test status
Simulation time 682521357 ps
CPU time 17.1 seconds
Started Mar 03 12:39:11 PM PST 24
Finished Mar 03 12:39:29 PM PST 24
Peak memory 197212 kb
Host smart-4145efb0-c4cb-4369-814a-abd50bd12c70
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590983212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.590983212
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2079483532
Short name T533
Test name
Test status
Simulation time 69971676 ps
CPU time 0.96 seconds
Started Mar 03 12:39:14 PM PST 24
Finished Mar 03 12:39:19 PM PST 24
Peak memory 196424 kb
Host smart-624c9726-fa1d-435f-af76-f0b9532d016e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079483532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2079483532
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2313105215
Short name T519
Test name
Test status
Simulation time 296344166 ps
CPU time 1.25 seconds
Started Mar 03 12:39:30 PM PST 24
Finished Mar 03 12:39:32 PM PST 24
Peak memory 195972 kb
Host smart-f39b4084-42f2-4fd5-a5ce-b6de3d9d4c39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313105215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2313105215
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.677299506
Short name T342
Test name
Test status
Simulation time 45166639 ps
CPU time 1.11 seconds
Started Mar 03 12:39:11 PM PST 24
Finished Mar 03 12:39:13 PM PST 24
Peak memory 197936 kb
Host smart-424b80dc-1472-4614-b374-b08e1580021a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677299506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.677299506
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1072382589
Short name T706
Test name
Test status
Simulation time 135734831 ps
CPU time 3.01 seconds
Started Mar 03 12:39:19 PM PST 24
Finished Mar 03 12:39:24 PM PST 24
Peak memory 196984 kb
Host smart-02ea8fd9-200f-44b4-801b-22cc1cedf84f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072382589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1072382589
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2978963873
Short name T483
Test name
Test status
Simulation time 228207578 ps
CPU time 1.28 seconds
Started Mar 03 12:39:18 PM PST 24
Finished Mar 03 12:39:21 PM PST 24
Peak memory 197176 kb
Host smart-ca871eed-bcc3-485a-99da-67212337d283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978963873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2978963873
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.670217303
Short name T605
Test name
Test status
Simulation time 244566787 ps
CPU time 1.31 seconds
Started Mar 03 12:39:15 PM PST 24
Finished Mar 03 12:39:21 PM PST 24
Peak memory 197008 kb
Host smart-0487fc69-ea77-46d6-b607-acf83a5fb814
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670217303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.670217303
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2378322434
Short name T220
Test name
Test status
Simulation time 127808306 ps
CPU time 1.6 seconds
Started Mar 03 12:39:21 PM PST 24
Finished Mar 03 12:39:28 PM PST 24
Peak memory 198148 kb
Host smart-c294105b-fd97-4e6d-8f26-d06a42ab6a96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378322434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2378322434
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.104364911
Short name T162
Test name
Test status
Simulation time 81386237 ps
CPU time 0.81 seconds
Started Mar 03 12:39:17 PM PST 24
Finished Mar 03 12:39:21 PM PST 24
Peak memory 195280 kb
Host smart-cddd452b-6c34-4d08-a013-c37efcaa13e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104364911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.104364911
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2313950265
Short name T233
Test name
Test status
Simulation time 231660477 ps
CPU time 1.09 seconds
Started Mar 03 12:39:29 PM PST 24
Finished Mar 03 12:39:30 PM PST 24
Peak memory 195736 kb
Host smart-d3302230-f61a-49a9-a89f-baf1a848f5a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313950265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2313950265
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.278824380
Short name T650
Test name
Test status
Simulation time 26135669635 ps
CPU time 167.2 seconds
Started Mar 03 12:39:11 PM PST 24
Finished Mar 03 12:41:59 PM PST 24
Peak memory 198264 kb
Host smart-01d5b227-e019-4ce8-ac92-096a75e093c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278824380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.278824380
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1207640452
Short name T12
Test name
Test status
Simulation time 409986673951 ps
CPU time 2858.35 seconds
Started Mar 03 12:39:14 PM PST 24
Finished Mar 03 01:26:54 PM PST 24
Peak memory 198292 kb
Host smart-50dcd6ee-167c-4f34-8de9-286171b89c09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1207640452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1207640452
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3508760043
Short name T314
Test name
Test status
Simulation time 15385750 ps
CPU time 0.58 seconds
Started Mar 03 12:39:15 PM PST 24
Finished Mar 03 12:39:21 PM PST 24
Peak memory 194756 kb
Host smart-c75b742d-a68b-4f26-8e62-c916bf9215e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508760043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3508760043
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.202170242
Short name T529
Test name
Test status
Simulation time 29312490 ps
CPU time 0.7 seconds
Started Mar 03 12:39:12 PM PST 24
Finished Mar 03 12:39:21 PM PST 24
Peak memory 194052 kb
Host smart-03dee3e9-1645-41eb-a7cc-83dcc6230810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202170242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.202170242
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1562185953
Short name T147
Test name
Test status
Simulation time 730465772 ps
CPU time 23.51 seconds
Started Mar 03 12:39:10 PM PST 24
Finished Mar 03 12:39:35 PM PST 24
Peak memory 198080 kb
Host smart-736ea9bb-f7d9-46de-a5b1-4dc56a45aa33
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562185953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1562185953
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1032387066
Short name T383
Test name
Test status
Simulation time 947219641 ps
CPU time 0.93 seconds
Started Mar 03 12:39:16 PM PST 24
Finished Mar 03 12:39:21 PM PST 24
Peak memory 196580 kb
Host smart-654b27ca-cac1-43ca-a552-b4d15ad0443d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032387066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1032387066
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2361191345
Short name T366
Test name
Test status
Simulation time 127346720 ps
CPU time 1.05 seconds
Started Mar 03 12:39:14 PM PST 24
Finished Mar 03 12:39:16 PM PST 24
Peak memory 196140 kb
Host smart-7f7bda6a-07b1-4c56-bcb3-b3e7b9de34aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361191345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2361191345
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.2554266539
Short name T412
Test name
Test status
Simulation time 186926769 ps
CPU time 1.86 seconds
Started Mar 03 12:39:25 PM PST 24
Finished Mar 03 12:39:28 PM PST 24
Peak memory 198020 kb
Host smart-2635f9d6-507a-4276-a32b-6de22ca15185
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554266539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.2554266539
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1014855159
Short name T397
Test name
Test status
Simulation time 68591770 ps
CPU time 2 seconds
Started Mar 03 12:39:27 PM PST 24
Finished Mar 03 12:39:30 PM PST 24
Peak memory 195816 kb
Host smart-7a8a1ba2-c078-479d-9337-b4c06e01524f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014855159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1014855159
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.667405392
Short name T163
Test name
Test status
Simulation time 86676058 ps
CPU time 1.03 seconds
Started Mar 03 12:39:20 PM PST 24
Finished Mar 03 12:39:22 PM PST 24
Peak memory 196004 kb
Host smart-51d302ba-2eae-45e8-b5e5-5e1808b0f9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667405392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.667405392
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3146714638
Short name T152
Test name
Test status
Simulation time 30934036 ps
CPU time 0.71 seconds
Started Mar 03 12:39:19 PM PST 24
Finished Mar 03 12:39:22 PM PST 24
Peak memory 196364 kb
Host smart-4fd8fc24-9f4a-4860-8b8c-75376f755acc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146714638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3146714638
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2114606050
Short name T493
Test name
Test status
Simulation time 88704069 ps
CPU time 3.99 seconds
Started Mar 03 12:39:20 PM PST 24
Finished Mar 03 12:39:25 PM PST 24
Peak memory 198024 kb
Host smart-a60b6be4-d76d-4617-bcb8-7f80b4f8716b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114606050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2114606050
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.4022093410
Short name T482
Test name
Test status
Simulation time 41042501 ps
CPU time 1.17 seconds
Started Mar 03 12:39:11 PM PST 24
Finished Mar 03 12:39:13 PM PST 24
Peak memory 195608 kb
Host smart-ee81400f-3314-417d-b58a-11c149ea9dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022093410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.4022093410
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.58269546
Short name T249
Test name
Test status
Simulation time 94227460 ps
CPU time 1.04 seconds
Started Mar 03 12:39:21 PM PST 24
Finished Mar 03 12:39:22 PM PST 24
Peak memory 196516 kb
Host smart-723825f1-4dd3-44b9-9cec-e8874c960f92
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58269546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.58269546
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2900062603
Short name T641
Test name
Test status
Simulation time 40119206717 ps
CPU time 120.51 seconds
Started Mar 03 12:39:04 PM PST 24
Finished Mar 03 12:41:04 PM PST 24
Peak memory 198256 kb
Host smart-9009ce13-bab7-44f9-b2d2-dac0f7c72dbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900062603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2900062603
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3842943276
Short name T485
Test name
Test status
Simulation time 495271170453 ps
CPU time 2424.29 seconds
Started Mar 03 12:39:11 PM PST 24
Finished Mar 03 01:19:36 PM PST 24
Peak memory 198388 kb
Host smart-2d49255a-0d5d-42bc-859d-31ae882f7f2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3842943276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3842943276
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.134721730
Short name T466
Test name
Test status
Simulation time 11167879 ps
CPU time 0.56 seconds
Started Mar 03 12:39:12 PM PST 24
Finished Mar 03 12:39:14 PM PST 24
Peak memory 193956 kb
Host smart-62ca7e89-5251-40b0-b62b-38ba14e51814
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134721730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.134721730
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2090888237
Short name T672
Test name
Test status
Simulation time 48500081 ps
CPU time 0.91 seconds
Started Mar 03 12:39:25 PM PST 24
Finished Mar 03 12:39:26 PM PST 24
Peak memory 196280 kb
Host smart-6b0a2820-b5ff-4418-acea-6be07fd1fea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090888237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2090888237
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.79493362
Short name T156
Test name
Test status
Simulation time 2066840112 ps
CPU time 15.87 seconds
Started Mar 03 12:39:29 PM PST 24
Finished Mar 03 12:39:45 PM PST 24
Peak memory 197252 kb
Host smart-b4efd8a1-8c0b-49e5-a6b2-318a72458163
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79493362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress.79493362
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.966417144
Short name T112
Test name
Test status
Simulation time 376518268 ps
CPU time 0.69 seconds
Started Mar 03 12:39:16 PM PST 24
Finished Mar 03 12:39:30 PM PST 24
Peak memory 194608 kb
Host smart-8b26fd7a-7174-4cd8-a701-ae01ab4a4e09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966417144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.966417144
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2717199601
Short name T508
Test name
Test status
Simulation time 37803628 ps
CPU time 0.82 seconds
Started Mar 03 12:39:14 PM PST 24
Finished Mar 03 12:39:16 PM PST 24
Peak memory 195556 kb
Host smart-31e8d2e5-b564-41e1-9515-ed51c3d8d2ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717199601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2717199601
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.4013151880
Short name T622
Test name
Test status
Simulation time 69179452 ps
CPU time 0.99 seconds
Started Mar 03 12:39:14 PM PST 24
Finished Mar 03 12:39:19 PM PST 24
Peak memory 196676 kb
Host smart-34972b7a-6d50-4af2-81c0-2b51a00fdb3f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013151880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.4013151880
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2326410421
Short name T715
Test name
Test status
Simulation time 483186731 ps
CPU time 3.52 seconds
Started Mar 03 12:39:30 PM PST 24
Finished Mar 03 12:39:43 PM PST 24
Peak memory 197112 kb
Host smart-98313f7e-2b0a-4299-9d9f-9290eee724d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326410421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2326410421
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3836654872
Short name T331
Test name
Test status
Simulation time 357266672 ps
CPU time 0.91 seconds
Started Mar 03 12:39:30 PM PST 24
Finished Mar 03 12:39:31 PM PST 24
Peak memory 196660 kb
Host smart-469c7a0e-c956-432a-95eb-81e7ad1b8e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836654872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3836654872
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2913612468
Short name T674
Test name
Test status
Simulation time 135633293 ps
CPU time 0.88 seconds
Started Mar 03 12:39:16 PM PST 24
Finished Mar 03 12:39:20 PM PST 24
Peak memory 196072 kb
Host smart-b47300cb-4fe1-4363-8bbf-80daa2f5e46a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913612468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2913612468
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.72341310
Short name T572
Test name
Test status
Simulation time 428814288 ps
CPU time 5.15 seconds
Started Mar 03 12:39:19 PM PST 24
Finished Mar 03 12:39:26 PM PST 24
Peak memory 197992 kb
Host smart-30f68c71-c74a-4157-b948-f369eb60c641
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72341310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rando
m_long_reg_writes_reg_reads.72341310
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3788350775
Short name T589
Test name
Test status
Simulation time 100956084 ps
CPU time 1.26 seconds
Started Mar 03 12:39:10 PM PST 24
Finished Mar 03 12:39:21 PM PST 24
Peak memory 196904 kb
Host smart-7f3dec4c-59a1-4e7c-81a6-848e1e9290e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788350775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3788350775
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1068621577
Short name T579
Test name
Test status
Simulation time 78228876 ps
CPU time 0.9 seconds
Started Mar 03 12:39:10 PM PST 24
Finished Mar 03 12:39:12 PM PST 24
Peak memory 196304 kb
Host smart-d0bf71bb-dea4-4374-966e-312e274e68aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068621577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1068621577
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.965871255
Short name T540
Test name
Test status
Simulation time 21977227117 ps
CPU time 65.82 seconds
Started Mar 03 12:39:17 PM PST 24
Finished Mar 03 12:40:26 PM PST 24
Peak memory 198296 kb
Host smart-1d853162-085e-4671-ac70-3169f8a5422b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965871255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.965871255
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2726641348
Short name T894
Test name
Test status
Simulation time 54539320 ps
CPU time 0.84 seconds
Started Mar 03 12:42:27 PM PST 24
Finished Mar 03 12:42:28 PM PST 24
Peak memory 195432 kb
Host smart-ba135107-5226-43bc-88a0-51ac81294454
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2726641348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2726641348
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4131730126
Short name T868
Test name
Test status
Simulation time 51657222 ps
CPU time 1.44 seconds
Started Mar 03 12:42:28 PM PST 24
Finished Mar 03 12:42:29 PM PST 24
Peak memory 195640 kb
Host smart-51f66e65-cb4a-47c5-bc63-286e111edd75
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131730126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4131730126
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2511218000
Short name T909
Test name
Test status
Simulation time 96253985 ps
CPU time 0.89 seconds
Started Mar 03 12:42:35 PM PST 24
Finished Mar 03 12:42:36 PM PST 24
Peak memory 196756 kb
Host smart-832b8042-4779-4a4a-ba1b-f096eff1512d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2511218000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2511218000
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.464493153
Short name T937
Test name
Test status
Simulation time 312845053 ps
CPU time 1.15 seconds
Started Mar 03 12:42:27 PM PST 24
Finished Mar 03 12:42:29 PM PST 24
Peak memory 196744 kb
Host smart-3aff6b3f-f029-4b97-a776-ac22fc20b5f6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464493153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.464493153
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.449361248
Short name T879
Test name
Test status
Simulation time 52912085 ps
CPU time 0.7 seconds
Started Mar 03 12:42:35 PM PST 24
Finished Mar 03 12:42:35 PM PST 24
Peak memory 194300 kb
Host smart-f5b932a4-c2c8-466b-a835-fc868bf2e597
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=449361248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.449361248
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3373169018
Short name T851
Test name
Test status
Simulation time 134750263 ps
CPU time 0.79 seconds
Started Mar 03 12:42:34 PM PST 24
Finished Mar 03 12:42:35 PM PST 24
Peak memory 196084 kb
Host smart-ed7d12b0-b5df-43fe-a925-d90f09706fc5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373169018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3373169018
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2271344801
Short name T930
Test name
Test status
Simulation time 42386850 ps
CPU time 0.8 seconds
Started Mar 03 12:42:34 PM PST 24
Finished Mar 03 12:42:35 PM PST 24
Peak memory 195308 kb
Host smart-561ddb0c-be13-4e87-95b9-8be7cee489e7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2271344801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2271344801
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4262419242
Short name T896
Test name
Test status
Simulation time 257134411 ps
CPU time 1.32 seconds
Started Mar 03 12:42:34 PM PST 24
Finished Mar 03 12:42:36 PM PST 24
Peak memory 196964 kb
Host smart-9f341b21-d615-47ab-b400-3939eb148be2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262419242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4262419242
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1534284509
Short name T873
Test name
Test status
Simulation time 50144043 ps
CPU time 1.16 seconds
Started Mar 03 12:42:34 PM PST 24
Finished Mar 03 12:42:36 PM PST 24
Peak memory 197584 kb
Host smart-e2307bcd-7229-47fd-9344-42f56e0f711f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1534284509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1534284509
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1625860107
Short name T857
Test name
Test status
Simulation time 63885184 ps
CPU time 1.12 seconds
Started Mar 03 12:42:35 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 196672 kb
Host smart-22ae337f-2f0d-47fc-9ddc-807c53a4031d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625860107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1625860107
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1998002610
Short name T916
Test name
Test status
Simulation time 283035471 ps
CPU time 1.46 seconds
Started Mar 03 12:42:36 PM PST 24
Finished Mar 03 12:42:38 PM PST 24
Peak memory 196616 kb
Host smart-b5d6fcc7-cbe4-4a36-96c3-b4c453da2c2f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1998002610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1998002610
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4054992153
Short name T911
Test name
Test status
Simulation time 95445243 ps
CPU time 1.27 seconds
Started Mar 03 12:42:34 PM PST 24
Finished Mar 03 12:42:36 PM PST 24
Peak memory 196780 kb
Host smart-ce8d3281-72fc-4937-a4bc-4280194aaa50
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054992153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4054992153
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3800320241
Short name T872
Test name
Test status
Simulation time 175352490 ps
CPU time 1.38 seconds
Started Mar 03 12:42:37 PM PST 24
Finished Mar 03 12:42:39 PM PST 24
Peak memory 195976 kb
Host smart-bb43332f-1f2a-462a-8aa3-0c322f14719c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3800320241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3800320241
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1923932201
Short name T892
Test name
Test status
Simulation time 35139951 ps
CPU time 1.01 seconds
Started Mar 03 12:42:34 PM PST 24
Finished Mar 03 12:42:35 PM PST 24
Peak memory 197992 kb
Host smart-8febabe1-843f-4e63-bd31-3fca13890c5e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923932201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1923932201
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2726379591
Short name T843
Test name
Test status
Simulation time 173360042 ps
CPU time 1.31 seconds
Started Mar 03 12:42:35 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 195836 kb
Host smart-d931f450-c36a-4ee2-84cc-4901829984df
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2726379591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2726379591
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3787998891
Short name T887
Test name
Test status
Simulation time 226433492 ps
CPU time 1.12 seconds
Started Mar 03 12:42:34 PM PST 24
Finished Mar 03 12:42:35 PM PST 24
Peak memory 196372 kb
Host smart-974a0847-c347-409d-93bd-d8cfd0efd3ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787998891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3787998891
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3220019575
Short name T905
Test name
Test status
Simulation time 172710860 ps
CPU time 1.49 seconds
Started Mar 03 12:42:35 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 196576 kb
Host smart-4c479969-f1b9-4045-b6fa-7d4e4a83f763
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3220019575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3220019575
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.529448070
Short name T875
Test name
Test status
Simulation time 205671702 ps
CPU time 1.2 seconds
Started Mar 03 12:42:37 PM PST 24
Finished Mar 03 12:42:39 PM PST 24
Peak memory 196492 kb
Host smart-f8c4c8d0-2c5a-4a9e-914b-f5b3954378c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529448070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.529448070
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3332514625
Short name T907
Test name
Test status
Simulation time 32968300 ps
CPU time 0.77 seconds
Started Mar 03 12:42:36 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 195424 kb
Host smart-ad5c1c87-9dee-4925-83b2-d1a0f46c6df3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3332514625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3332514625
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.413679320
Short name T913
Test name
Test status
Simulation time 214646516 ps
CPU time 0.92 seconds
Started Mar 03 12:42:32 PM PST 24
Finished Mar 03 12:42:33 PM PST 24
Peak memory 195340 kb
Host smart-f2b8e65f-db7c-45b7-9f0a-7958ece739ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413679320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.413679320
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3881788624
Short name T864
Test name
Test status
Simulation time 208309392 ps
CPU time 1.29 seconds
Started Mar 03 12:42:34 PM PST 24
Finished Mar 03 12:42:35 PM PST 24
Peak memory 196640 kb
Host smart-605e5361-d185-413e-ae0d-444c8b977bb5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3881788624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3881788624
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.662768887
Short name T922
Test name
Test status
Simulation time 44096785 ps
CPU time 1.21 seconds
Started Mar 03 12:42:36 PM PST 24
Finished Mar 03 12:42:38 PM PST 24
Peak memory 196292 kb
Host smart-492104b9-670e-4cbb-9945-60baf1e437ad
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662768887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.662768887
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3068535159
Short name T934
Test name
Test status
Simulation time 52115013 ps
CPU time 1.61 seconds
Started Mar 03 12:42:32 PM PST 24
Finished Mar 03 12:42:34 PM PST 24
Peak memory 196348 kb
Host smart-21624812-8ffe-44bd-85fa-a945be50806c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3068535159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3068535159
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3539819493
Short name T878
Test name
Test status
Simulation time 95811611 ps
CPU time 1.08 seconds
Started Mar 03 12:42:36 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 198340 kb
Host smart-1cd483dc-7750-4217-8a8f-05a86c68017f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539819493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3539819493
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.202565907
Short name T903
Test name
Test status
Simulation time 100578765 ps
CPU time 1.31 seconds
Started Mar 03 12:42:28 PM PST 24
Finished Mar 03 12:42:29 PM PST 24
Peak memory 196972 kb
Host smart-1bd2aac0-3f53-44ab-b507-bd63bfba1395
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=202565907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.202565907
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.987112630
Short name T874
Test name
Test status
Simulation time 83292567 ps
CPU time 0.81 seconds
Started Mar 03 12:42:35 PM PST 24
Finished Mar 03 12:42:36 PM PST 24
Peak memory 196064 kb
Host smart-3e0ae6da-ea3f-466e-86c5-53cb3b667e06
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987112630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.987112630
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.904811382
Short name T861
Test name
Test status
Simulation time 133468840 ps
CPU time 1 seconds
Started Mar 03 12:42:35 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 197764 kb
Host smart-9cf5b8ef-6395-462a-b445-190cc259beaa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=904811382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.904811382
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3685647234
Short name T844
Test name
Test status
Simulation time 24721196 ps
CPU time 0.8 seconds
Started Mar 03 12:42:32 PM PST 24
Finished Mar 03 12:42:33 PM PST 24
Peak memory 195400 kb
Host smart-733dfd55-779b-430e-8740-e70e356884ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685647234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3685647234
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.772330046
Short name T938
Test name
Test status
Simulation time 59059310 ps
CPU time 0.67 seconds
Started Mar 03 12:42:43 PM PST 24
Finished Mar 03 12:42:43 PM PST 24
Peak memory 194936 kb
Host smart-9f62edfa-8fc6-4efc-a3b2-faeb9c27bddd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=772330046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.772330046
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1375842455
Short name T842
Test name
Test status
Simulation time 82232317 ps
CPU time 1.26 seconds
Started Mar 03 12:42:45 PM PST 24
Finished Mar 03 12:42:48 PM PST 24
Peak memory 198004 kb
Host smart-1d84bea6-1d28-4a63-a9ce-814a1232ee0c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375842455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1375842455
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.422352136
Short name T876
Test name
Test status
Simulation time 28262316 ps
CPU time 0.83 seconds
Started Mar 03 12:42:45 PM PST 24
Finished Mar 03 12:42:47 PM PST 24
Peak memory 195292 kb
Host smart-99a02d0a-cdf3-4dcf-a297-c99451a5aed6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=422352136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.422352136
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1241499583
Short name T897
Test name
Test status
Simulation time 37031012 ps
CPU time 1.27 seconds
Started Mar 03 12:42:44 PM PST 24
Finished Mar 03 12:42:46 PM PST 24
Peak memory 196488 kb
Host smart-6fc549a7-36ed-40e8-a33b-a6fe94bcfd40
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241499583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1241499583
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3058997081
Short name T882
Test name
Test status
Simulation time 131952197 ps
CPU time 1.19 seconds
Started Mar 03 12:42:43 PM PST 24
Finished Mar 03 12:42:45 PM PST 24
Peak memory 195816 kb
Host smart-e53eb8bd-0d71-4bcf-afe9-341e0c7f3328
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3058997081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3058997081
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1177592719
Short name T940
Test name
Test status
Simulation time 35151828 ps
CPU time 1.12 seconds
Started Mar 03 12:42:43 PM PST 24
Finished Mar 03 12:42:44 PM PST 24
Peak memory 195692 kb
Host smart-1a70f330-76fc-4ef2-b448-621da15b6fcd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177592719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1177592719
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3632431506
Short name T886
Test name
Test status
Simulation time 277067900 ps
CPU time 1.2 seconds
Started Mar 03 12:42:46 PM PST 24
Finished Mar 03 12:42:48 PM PST 24
Peak memory 195748 kb
Host smart-7aa91d37-c1be-4251-abd7-20c2cdf43630
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3632431506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3632431506
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2576379054
Short name T939
Test name
Test status
Simulation time 36042647 ps
CPU time 1.1 seconds
Started Mar 03 12:42:44 PM PST 24
Finished Mar 03 12:42:45 PM PST 24
Peak memory 195876 kb
Host smart-1681681a-edfc-4ad0-b355-2fca8835507f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576379054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2576379054
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2103055600
Short name T921
Test name
Test status
Simulation time 151226256 ps
CPU time 0.83 seconds
Started Mar 03 12:42:44 PM PST 24
Finished Mar 03 12:42:45 PM PST 24
Peak memory 196200 kb
Host smart-cfedbd63-7614-439b-a2eb-d29c430d7f89
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2103055600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2103055600
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1248064098
Short name T858
Test name
Test status
Simulation time 124698476 ps
CPU time 1.42 seconds
Started Mar 03 12:42:42 PM PST 24
Finished Mar 03 12:42:44 PM PST 24
Peak memory 198004 kb
Host smart-22a00f2a-dbda-4f56-83ee-4f928c0360a6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248064098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1248064098
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1269885889
Short name T923
Test name
Test status
Simulation time 81094900 ps
CPU time 1.34 seconds
Started Mar 03 12:42:45 PM PST 24
Finished Mar 03 12:42:47 PM PST 24
Peak memory 196496 kb
Host smart-3e33c486-0727-4b35-b2a1-5f0672ea363c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1269885889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1269885889
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.171072754
Short name T855
Test name
Test status
Simulation time 154148793 ps
CPU time 1.02 seconds
Started Mar 03 12:42:44 PM PST 24
Finished Mar 03 12:42:46 PM PST 24
Peak memory 196368 kb
Host smart-435c132c-f56c-49f5-8e36-d5abfae4dba5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171072754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.171072754
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2845796855
Short name T885
Test name
Test status
Simulation time 46544650 ps
CPU time 1.07 seconds
Started Mar 03 12:42:45 PM PST 24
Finished Mar 03 12:42:48 PM PST 24
Peak memory 197800 kb
Host smart-f95f2ca7-65b0-4f86-851e-ef36e147ae24
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2845796855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2845796855
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4083781642
Short name T919
Test name
Test status
Simulation time 168463619 ps
CPU time 1.18 seconds
Started Mar 03 12:42:44 PM PST 24
Finished Mar 03 12:42:45 PM PST 24
Peak memory 196796 kb
Host smart-22a3fa4a-da4e-49a9-9b8f-be4d91c8441a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083781642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4083781642
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2634019382
Short name T920
Test name
Test status
Simulation time 36903776 ps
CPU time 1.33 seconds
Started Mar 03 12:42:44 PM PST 24
Finished Mar 03 12:42:45 PM PST 24
Peak memory 197644 kb
Host smart-20e9b0f4-886b-4a78-9b1d-dce59736f0af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2634019382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2634019382
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3260396272
Short name T929
Test name
Test status
Simulation time 57419725 ps
CPU time 1.59 seconds
Started Mar 03 12:42:45 PM PST 24
Finished Mar 03 12:42:48 PM PST 24
Peak memory 196792 kb
Host smart-721a7e98-b12b-47d3-b469-94b43c3b0dd8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260396272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3260396272
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.977804765
Short name T924
Test name
Test status
Simulation time 307012374 ps
CPU time 1.69 seconds
Started Mar 03 12:42:45 PM PST 24
Finished Mar 03 12:42:48 PM PST 24
Peak memory 196748 kb
Host smart-118cee6a-4cfc-4cbb-9317-5fd0692d022a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=977804765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.977804765
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.306111219
Short name T918
Test name
Test status
Simulation time 218221638 ps
CPU time 1.07 seconds
Started Mar 03 12:42:47 PM PST 24
Finished Mar 03 12:42:50 PM PST 24
Peak memory 196716 kb
Host smart-b19ef605-a342-4acc-9998-5b8ff8c72816
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306111219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.306111219
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.268890518
Short name T865
Test name
Test status
Simulation time 130635597 ps
CPU time 0.93 seconds
Started Mar 03 12:42:35 PM PST 24
Finished Mar 03 12:42:36 PM PST 24
Peak memory 196652 kb
Host smart-bb4a2254-b48c-4826-b717-6b883bb6bec6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=268890518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.268890518
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.858439749
Short name T933
Test name
Test status
Simulation time 104242251 ps
CPU time 0.97 seconds
Started Mar 03 12:42:30 PM PST 24
Finished Mar 03 12:42:31 PM PST 24
Peak memory 195460 kb
Host smart-980ff710-f51e-4a74-b0c9-85ad9a7f88b4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858439749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.858439749
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2183959436
Short name T895
Test name
Test status
Simulation time 195900831 ps
CPU time 1.48 seconds
Started Mar 03 12:42:45 PM PST 24
Finished Mar 03 12:42:48 PM PST 24
Peak memory 197952 kb
Host smart-702fa24e-447b-4e18-885c-a0b6c24e4489
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2183959436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2183959436
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4151507395
Short name T871
Test name
Test status
Simulation time 58755937 ps
CPU time 1.21 seconds
Started Mar 03 12:42:46 PM PST 24
Finished Mar 03 12:42:49 PM PST 24
Peak memory 198008 kb
Host smart-801cd7c1-ebbf-48c5-81f5-d1f242413253
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151507395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4151507395
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2625254126
Short name T877
Test name
Test status
Simulation time 70512513 ps
CPU time 1.16 seconds
Started Mar 03 12:42:43 PM PST 24
Finished Mar 03 12:42:45 PM PST 24
Peak memory 198104 kb
Host smart-c4b9108d-c01d-4eb3-93df-d68f0bf27454
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2625254126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2625254126
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.773097292
Short name T845
Test name
Test status
Simulation time 28269507 ps
CPU time 0.79 seconds
Started Mar 03 12:42:44 PM PST 24
Finished Mar 03 12:42:45 PM PST 24
Peak memory 195928 kb
Host smart-0e392d99-80d8-4efc-8149-709529dec11a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773097292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.773097292
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3328663716
Short name T847
Test name
Test status
Simulation time 192938766 ps
CPU time 1.12 seconds
Started Mar 03 12:42:44 PM PST 24
Finished Mar 03 12:42:45 PM PST 24
Peak memory 195744 kb
Host smart-4c00c988-7b80-4c63-ae24-8eae21d542be
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3328663716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3328663716
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4053343436
Short name T931
Test name
Test status
Simulation time 48208613 ps
CPU time 1.43 seconds
Started Mar 03 12:42:46 PM PST 24
Finished Mar 03 12:42:48 PM PST 24
Peak memory 196528 kb
Host smart-71f11761-7293-48c3-8093-720db5bcbaa4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053343436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4053343436
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3641761489
Short name T891
Test name
Test status
Simulation time 219677837 ps
CPU time 1.29 seconds
Started Mar 03 12:42:43 PM PST 24
Finished Mar 03 12:42:44 PM PST 24
Peak memory 195676 kb
Host smart-d7582b9b-2f7b-4397-9ab5-71b6d793f71d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3641761489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3641761489
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.587467741
Short name T888
Test name
Test status
Simulation time 148911384 ps
CPU time 0.9 seconds
Started Mar 03 12:42:45 PM PST 24
Finished Mar 03 12:42:47 PM PST 24
Peak memory 196500 kb
Host smart-fe12c1a8-f2f3-4bac-bfab-17f88fe37214
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587467741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.587467741
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3436125056
Short name T867
Test name
Test status
Simulation time 113307507 ps
CPU time 1.34 seconds
Started Mar 03 12:42:43 PM PST 24
Finished Mar 03 12:42:45 PM PST 24
Peak memory 195532 kb
Host smart-e625382b-0d5c-4099-b1e6-72216a50653d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3436125056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3436125056
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2000395601
Short name T928
Test name
Test status
Simulation time 68938159 ps
CPU time 1.07 seconds
Started Mar 03 12:42:44 PM PST 24
Finished Mar 03 12:42:46 PM PST 24
Peak memory 196672 kb
Host smart-b430d2ad-d7ba-41df-9455-dde9b749c8c2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000395601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2000395601
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3163065061
Short name T870
Test name
Test status
Simulation time 63247646 ps
CPU time 1.28 seconds
Started Mar 03 12:42:46 PM PST 24
Finished Mar 03 12:42:48 PM PST 24
Peak memory 195860 kb
Host smart-989bcb16-6770-404f-94a5-a6602e47e206
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3163065061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3163065061
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1334968631
Short name T914
Test name
Test status
Simulation time 182146562 ps
CPU time 1.16 seconds
Started Mar 03 12:42:45 PM PST 24
Finished Mar 03 12:42:48 PM PST 24
Peak memory 196360 kb
Host smart-bf9a45b6-00a7-4f19-8890-2c4f9aa74e65
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334968631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1334968631
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1035378119
Short name T881
Test name
Test status
Simulation time 86782381 ps
CPU time 1.44 seconds
Started Mar 03 12:42:54 PM PST 24
Finished Mar 03 12:42:56 PM PST 24
Peak memory 195664 kb
Host smart-6378945c-a812-4163-9f23-db099e8f9600
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1035378119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1035378119
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3124263743
Short name T853
Test name
Test status
Simulation time 195780224 ps
CPU time 1.54 seconds
Started Mar 03 12:42:54 PM PST 24
Finished Mar 03 12:42:57 PM PST 24
Peak memory 198004 kb
Host smart-671abbb3-8ad3-4d28-8e6c-5306ffe59064
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124263743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3124263743
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3742649048
Short name T854
Test name
Test status
Simulation time 73094008 ps
CPU time 1.46 seconds
Started Mar 03 12:42:56 PM PST 24
Finished Mar 03 12:42:58 PM PST 24
Peak memory 197084 kb
Host smart-52918cb8-adc1-4834-aef4-60fc29ac0039
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3742649048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3742649048
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1571111657
Short name T941
Test name
Test status
Simulation time 646511738 ps
CPU time 1.16 seconds
Started Mar 03 12:42:56 PM PST 24
Finished Mar 03 12:42:58 PM PST 24
Peak memory 196480 kb
Host smart-3e0fe686-3fc0-48b2-b1f9-602f3ddb3d97
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571111657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1571111657
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1459643151
Short name T890
Test name
Test status
Simulation time 156274552 ps
CPU time 1.15 seconds
Started Mar 03 12:42:55 PM PST 24
Finished Mar 03 12:42:56 PM PST 24
Peak memory 196812 kb
Host smart-6324744c-2d05-49e8-9610-d704db40b59e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1459643151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1459643151
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2049417290
Short name T925
Test name
Test status
Simulation time 87546648 ps
CPU time 1.39 seconds
Started Mar 03 12:42:54 PM PST 24
Finished Mar 03 12:42:56 PM PST 24
Peak memory 196872 kb
Host smart-e8a1d885-6355-4898-a9c7-8af0010befee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049417290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2049417290
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.253087694
Short name T904
Test name
Test status
Simulation time 108271406 ps
CPU time 1.31 seconds
Started Mar 03 12:42:52 PM PST 24
Finished Mar 03 12:42:53 PM PST 24
Peak memory 198012 kb
Host smart-68fff0bc-cad9-4c05-b31b-b881e563c690
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=253087694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.253087694
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3380729419
Short name T899
Test name
Test status
Simulation time 90818259 ps
CPU time 1.42 seconds
Started Mar 03 12:42:51 PM PST 24
Finished Mar 03 12:42:53 PM PST 24
Peak memory 196868 kb
Host smart-f8e93125-883b-42b5-b680-54722e74458b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380729419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3380729419
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.575402105
Short name T936
Test name
Test status
Simulation time 87379400 ps
CPU time 1.27 seconds
Started Mar 03 12:42:35 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 196596 kb
Host smart-f50ee141-fc11-4388-aa04-8a6c96201856
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=575402105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.575402105
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.322611098
Short name T935
Test name
Test status
Simulation time 53226145 ps
CPU time 1.15 seconds
Started Mar 03 12:42:29 PM PST 24
Finished Mar 03 12:42:30 PM PST 24
Peak memory 198092 kb
Host smart-80bc97cb-3c74-4732-8c1a-16b7fbbe5da7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322611098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.322611098
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1045137291
Short name T883
Test name
Test status
Simulation time 113158392 ps
CPU time 1.05 seconds
Started Mar 03 12:42:55 PM PST 24
Finished Mar 03 12:42:56 PM PST 24
Peak memory 195600 kb
Host smart-c05708bb-f49c-4e10-8dae-8b43e911cf40
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1045137291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1045137291
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4179928933
Short name T849
Test name
Test status
Simulation time 25178926 ps
CPU time 0.92 seconds
Started Mar 03 12:42:54 PM PST 24
Finished Mar 03 12:42:55 PM PST 24
Peak memory 196416 kb
Host smart-13890bac-7994-4cba-bde6-04cbdf55324c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179928933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4179928933
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3753184514
Short name T884
Test name
Test status
Simulation time 55922433 ps
CPU time 1.14 seconds
Started Mar 03 12:42:56 PM PST 24
Finished Mar 03 12:42:58 PM PST 24
Peak memory 196632 kb
Host smart-cb66d61d-a11f-4d2f-8776-c0e016f8cbac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3753184514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3753184514
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3071416043
Short name T848
Test name
Test status
Simulation time 78006031 ps
CPU time 1.32 seconds
Started Mar 03 12:42:54 PM PST 24
Finished Mar 03 12:42:56 PM PST 24
Peak memory 198088 kb
Host smart-4633bb1a-3058-418d-acd2-23424fac1d4b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071416043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3071416043
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.749753147
Short name T898
Test name
Test status
Simulation time 54916060 ps
CPU time 1.6 seconds
Started Mar 03 12:42:55 PM PST 24
Finished Mar 03 12:42:57 PM PST 24
Peak memory 196644 kb
Host smart-6f4bc392-7c9e-4c73-9103-91c47a62bc31
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=749753147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.749753147
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.148429154
Short name T880
Test name
Test status
Simulation time 223767240 ps
CPU time 1.11 seconds
Started Mar 03 12:42:53 PM PST 24
Finished Mar 03 12:42:55 PM PST 24
Peak memory 198020 kb
Host smart-22d1cfd8-5a7e-4374-bb9c-4b7f5f1e4c6c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148429154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.148429154
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1767762535
Short name T859
Test name
Test status
Simulation time 158923681 ps
CPU time 0.97 seconds
Started Mar 03 12:42:53 PM PST 24
Finished Mar 03 12:42:55 PM PST 24
Peak memory 195900 kb
Host smart-53959f79-b2ca-4877-b0a5-b12b84466f31
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1767762535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1767762535
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3528817927
Short name T862
Test name
Test status
Simulation time 185863716 ps
CPU time 1.38 seconds
Started Mar 03 12:42:53 PM PST 24
Finished Mar 03 12:42:55 PM PST 24
Peak memory 196928 kb
Host smart-7e09c179-f329-4fed-984f-5233accfbee5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528817927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3528817927
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4008501815
Short name T900
Test name
Test status
Simulation time 575095332 ps
CPU time 1.02 seconds
Started Mar 03 12:42:52 PM PST 24
Finished Mar 03 12:42:54 PM PST 24
Peak memory 196760 kb
Host smart-d42e5dc5-f3bb-4fa8-908f-a8bf84047aab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4008501815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.4008501815
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2195607568
Short name T846
Test name
Test status
Simulation time 82171794 ps
CPU time 1.35 seconds
Started Mar 03 12:42:53 PM PST 24
Finished Mar 03 12:42:55 PM PST 24
Peak memory 196712 kb
Host smart-a73d9d25-6d8e-4032-bafa-74b6ed303b3d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195607568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2195607568
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2145007022
Short name T932
Test name
Test status
Simulation time 132961533 ps
CPU time 0.93 seconds
Started Mar 03 12:42:53 PM PST 24
Finished Mar 03 12:42:55 PM PST 24
Peak memory 196580 kb
Host smart-ec422805-8eea-49d9-bee1-a071aa9b1af6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2145007022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2145007022
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.49710211
Short name T889
Test name
Test status
Simulation time 329828993 ps
CPU time 1.52 seconds
Started Mar 03 12:42:54 PM PST 24
Finished Mar 03 12:42:56 PM PST 24
Peak memory 196984 kb
Host smart-b8e3720b-bd33-49e3-b21f-79972b58d425
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49710211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.49710211
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.593614572
Short name T906
Test name
Test status
Simulation time 51997006 ps
CPU time 1.36 seconds
Started Mar 03 12:42:54 PM PST 24
Finished Mar 03 12:42:56 PM PST 24
Peak memory 196964 kb
Host smart-a336751b-eb7f-4270-b62d-7f695a0eadff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=593614572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.593614572
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2610155772
Short name T910
Test name
Test status
Simulation time 121617217 ps
CPU time 1.39 seconds
Started Mar 03 12:42:54 PM PST 24
Finished Mar 03 12:42:56 PM PST 24
Peak memory 196524 kb
Host smart-f9ddc1e4-d21b-41c2-a458-bba12eb107a4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610155772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2610155772
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.117551625
Short name T869
Test name
Test status
Simulation time 84010795 ps
CPU time 0.71 seconds
Started Mar 03 12:42:54 PM PST 24
Finished Mar 03 12:42:55 PM PST 24
Peak memory 194916 kb
Host smart-0322d284-e6c5-4f93-b79a-62560d9a66b0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=117551625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.117551625
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4265109326
Short name T917
Test name
Test status
Simulation time 195729838 ps
CPU time 0.99 seconds
Started Mar 03 12:42:52 PM PST 24
Finished Mar 03 12:42:53 PM PST 24
Peak memory 195400 kb
Host smart-77422efa-e0fa-41ff-ad89-0564bb751331
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265109326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4265109326
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1723000345
Short name T856
Test name
Test status
Simulation time 71192530 ps
CPU time 1.39 seconds
Started Mar 03 12:42:55 PM PST 24
Finished Mar 03 12:42:57 PM PST 24
Peak memory 197108 kb
Host smart-8b517f65-1ab0-407c-8378-53d67fd9aef3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1723000345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1723000345
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2100510557
Short name T852
Test name
Test status
Simulation time 126743037 ps
CPU time 1.11 seconds
Started Mar 03 12:42:55 PM PST 24
Finished Mar 03 12:42:57 PM PST 24
Peak memory 196460 kb
Host smart-4516e7ba-0aba-4e4a-9312-bab9a39967c7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100510557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2100510557
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2950129638
Short name T893
Test name
Test status
Simulation time 290774206 ps
CPU time 1.16 seconds
Started Mar 03 12:42:55 PM PST 24
Finished Mar 03 12:42:56 PM PST 24
Peak memory 196364 kb
Host smart-d492955b-9d2d-4b45-a883-d468eb592f3b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2950129638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2950129638
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1351236552
Short name T915
Test name
Test status
Simulation time 61700344 ps
CPU time 1.19 seconds
Started Mar 03 12:42:53 PM PST 24
Finished Mar 03 12:42:55 PM PST 24
Peak memory 196584 kb
Host smart-007b3bce-ebe1-4157-9369-d65b17f7cca6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351236552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1351236552
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2209225261
Short name T912
Test name
Test status
Simulation time 859592157 ps
CPU time 1.52 seconds
Started Mar 03 12:42:27 PM PST 24
Finished Mar 03 12:42:29 PM PST 24
Peak memory 197988 kb
Host smart-a67c59a4-3f66-4f61-b5ba-ba386f7ab438
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2209225261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2209225261
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2076919453
Short name T863
Test name
Test status
Simulation time 192865172 ps
CPU time 1.08 seconds
Started Mar 03 12:42:36 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 195856 kb
Host smart-066c78f0-8708-4fdd-876a-4eff20b7861e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076919453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2076919453
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.755007335
Short name T901
Test name
Test status
Simulation time 144634599 ps
CPU time 1.01 seconds
Started Mar 03 12:42:29 PM PST 24
Finished Mar 03 12:42:30 PM PST 24
Peak memory 196444 kb
Host smart-1f2a0cd2-ca29-437c-bc81-29a746e427e8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=755007335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.755007335
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3676967269
Short name T926
Test name
Test status
Simulation time 91063536 ps
CPU time 1.27 seconds
Started Mar 03 12:42:31 PM PST 24
Finished Mar 03 12:42:32 PM PST 24
Peak memory 196624 kb
Host smart-8461c477-c665-4211-a5cc-779f2eb1634d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676967269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3676967269
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.121732627
Short name T908
Test name
Test status
Simulation time 298105387 ps
CPU time 1.42 seconds
Started Mar 03 12:42:27 PM PST 24
Finished Mar 03 12:42:29 PM PST 24
Peak memory 198032 kb
Host smart-01de7e31-f29a-49cb-a4e0-08ac28affa37
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=121732627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.121732627
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.39068089
Short name T850
Test name
Test status
Simulation time 108866931 ps
CPU time 0.92 seconds
Started Mar 03 12:42:29 PM PST 24
Finished Mar 03 12:42:30 PM PST 24
Peak memory 197884 kb
Host smart-cf589940-5c4b-4018-b570-ab4a8061450d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39068089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.39068089
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2407513421
Short name T866
Test name
Test status
Simulation time 204582475 ps
CPU time 1.4 seconds
Started Mar 03 12:42:28 PM PST 24
Finished Mar 03 12:42:30 PM PST 24
Peak memory 198048 kb
Host smart-b1833828-bbf0-4b92-b1f1-5a07ee6822d0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2407513421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2407513421
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2013144403
Short name T860
Test name
Test status
Simulation time 35979813 ps
CPU time 1.01 seconds
Started Mar 03 12:42:39 PM PST 24
Finished Mar 03 12:42:40 PM PST 24
Peak memory 195824 kb
Host smart-e60677d9-383a-4b8a-9891-cdeb825c4189
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013144403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2013144403
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3952145734
Short name T902
Test name
Test status
Simulation time 47414584 ps
CPU time 1.27 seconds
Started Mar 03 12:42:36 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 196804 kb
Host smart-4b72ebf6-45fa-44b9-9051-d2b83c419e7e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3952145734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3952145734
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2281268714
Short name T927
Test name
Test status
Simulation time 71637034 ps
CPU time 1.09 seconds
Started Mar 03 12:42:37 PM PST 24
Finished Mar 03 12:42:38 PM PST 24
Peak memory 197064 kb
Host smart-4f2048c4-8c00-4ae4-8925-49ea1e16e4fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281268714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2281268714
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%