Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3617433	1			T21	104		T22	1		T23	1
all_pins[1]	3617433	1			T21	104		T22	1		T23	1
all_pins[2]	3617433	1			T21	104		T22	1		T23	1
all_pins[3]	3617433	1			T21	104		T22	1		T23	1
all_pins[4]	3617433	1			T21	104		T22	1		T23	1
all_pins[5]	3617433	1			T21	104		T22	1		T23	1
all_pins[6]	3617433	1			T21	104		T22	1		T23	1
all_pins[7]	3617433	1			T21	104		T22	1		T23	1
all_pins[8]	3617433	1			T21	104		T22	1		T23	1
all_pins[9]	3617433	1			T21	104		T22	1		T23	1
all_pins[10]	3617433	1			T21	104		T22	1		T23	1
all_pins[11]	3617433	1			T21	104		T22	1		T23	1
all_pins[12]	3617433	1			T21	104		T22	1		T23	1
all_pins[13]	3617433	1			T21	104		T22	1		T23	1
all_pins[14]	3617433	1			T21	104		T22	1		T23	1
all_pins[15]	3617433	1			T21	104		T22	1		T23	1
all_pins[16]	3617433	1			T21	104		T22	1		T23	1
all_pins[17]	3617433	1			T21	104		T22	1		T23	1
all_pins[18]	3617433	1			T21	104		T22	1		T23	1
all_pins[19]	3617433	1			T21	104		T22	1		T23	1
all_pins[20]	3617433	1			T21	104		T22	1		T23	1
all_pins[21]	3617433	1			T21	104		T22	1		T23	1
all_pins[22]	3617433	1			T21	104		T22	1		T23	1
all_pins[23]	3617433	1			T21	104		T22	1		T23	1
all_pins[24]	3617433	1			T21	104		T22	1		T23	1
all_pins[25]	3617433	1			T21	104		T22	1		T23	1
all_pins[26]	3617433	1			T21	104		T22	1		T23	1
all_pins[27]	3617433	1			T21	104		T22	1		T23	1
all_pins[28]	3617433	1			T21	104		T22	1		T23	1
all_pins[29]	3617433	1			T21	104		T22	1		T23	1
all_pins[30]	3617433	1			T21	104		T22	1		T23	1
all_pins[31]	3617433	1			T21	104		T22	1		T23	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	71913170	1			T21	1665		T22	32		T23	32
values[0x1]	43844686	1			T21	1663		T24	303		T25	10635
transitions[0x0=>0x1]	26271722	1			T21	832		T24	211		T25	6372
transitions[0x1=>0x0]	26271578	1			T21	831		T24	211		T25	6371

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2249414	1			T21	50		T22	1		T23	1
all_pins[0]	values[0x1]	1368019	1			T21	54		T24	12		T25	354
all_pins[0]	transitions[0x0=>0x1]	847608	1			T21	29		T24	9		T25	154
all_pins[0]	transitions[0x1=>0x0]	844087	1			T21	22		T25	169		T27	16
all_pins[1]	values[0x0]	2239495	1			T21	45		T22	1		T23	1
all_pins[1]	values[0x1]	1377938	1			T21	59		T24	2		T25	347
all_pins[1]	transitions[0x0=>0x1]	824594	1			T21	26		T24	2		T25	211
all_pins[1]	transitions[0x1=>0x0]	814675	1			T21	21		T24	12		T25	218
all_pins[2]	values[0x0]	2246538	1			T21	54		T22	1		T23	1
all_pins[2]	values[0x1]	1370895	1			T21	50		T24	14		T25	294
all_pins[2]	transitions[0x0=>0x1]	817308	1			T21	16		T24	14		T25	178
all_pins[2]	transitions[0x1=>0x0]	824351	1			T21	25		T24	2		T25	231
all_pins[3]	values[0x0]	2248706	1			T21	62		T22	1		T23	1
all_pins[3]	values[0x1]	1368727	1			T21	42		T24	9		T25	298
all_pins[3]	transitions[0x0=>0x1]	819813	1			T21	20		T24	8		T25	199
all_pins[3]	transitions[0x1=>0x0]	821981	1			T21	28		T24	13		T25	195
all_pins[4]	values[0x0]	2251830	1			T21	56		T22	1		T23	1
all_pins[4]	values[0x1]	1365603	1			T21	48		T24	5		T25	349
all_pins[4]	transitions[0x0=>0x1]	820069	1			T21	26		T24	1		T25	244
all_pins[4]	transitions[0x1=>0x0]	823193	1			T21	20		T24	5		T25	193
all_pins[5]	values[0x0]	2243607	1			T21	52		T22	1		T23	1
all_pins[5]	values[0x1]	1373826	1			T21	52		T24	7		T25	316
all_pins[5]	transitions[0x0=>0x1]	821523	1			T21	27		T24	6		T25	221
all_pins[5]	transitions[0x1=>0x0]	813300	1			T21	23		T24	4		T25	254
all_pins[6]	values[0x0]	2248756	1			T21	48		T22	1		T23	1
all_pins[6]	values[0x1]	1368677	1			T21	56		T24	12		T25	270
all_pins[6]	transitions[0x0=>0x1]	820359	1			T21	24		T24	11		T25	159
all_pins[6]	transitions[0x1=>0x0]	825508	1			T21	20		T24	6		T25	205
all_pins[7]	values[0x0]	2249671	1			T21	48		T22	1		T23	1
all_pins[7]	values[0x1]	1367762	1			T21	56		T24	10		T25	275
all_pins[7]	transitions[0x0=>0x1]	818535	1			T21	24		T24	6		T25	186
all_pins[7]	transitions[0x1=>0x0]	819450	1			T21	24		T24	8		T25	181
all_pins[8]	values[0x0]	2243912	1			T21	51		T22	1		T23	1
all_pins[8]	values[0x1]	1373521	1			T21	53		T25	310		T27	23
all_pins[8]	transitions[0x0=>0x1]	823120	1			T21	24		T25	207		T27	8
all_pins[8]	transitions[0x1=>0x0]	817361	1			T21	27		T24	10		T25	172
all_pins[9]	values[0x0]	2245131	1			T21	54		T22	1		T23	1
all_pins[9]	values[0x1]	1372302	1			T21	50		T24	10		T25	270
all_pins[9]	transitions[0x0=>0x1]	818096	1			T21	27		T24	10		T25	148
all_pins[9]	transitions[0x1=>0x0]	819315	1			T21	30		T25	188		T27	7
all_pins[10]	values[0x0]	2250486	1			T21	58		T22	1		T23	1
all_pins[10]	values[0x1]	1366947	1			T21	46		T24	8		T25	368
all_pins[10]	transitions[0x0=>0x1]	817119	1			T21	24		T24	5		T25	270
all_pins[10]	transitions[0x1=>0x0]	822474	1			T21	28		T24	7		T25	172
all_pins[11]	values[0x0]	2244141	1			T21	63		T22	1		T23	1
all_pins[11]	values[0x1]	1373292	1			T21	41		T24	11		T25	243
all_pins[11]	transitions[0x0=>0x1]	822746	1			T21	25		T24	6		T25	127
all_pins[11]	transitions[0x1=>0x0]	816401	1			T21	30		T24	3		T25	252
all_pins[12]	values[0x0]	2246089	1			T21	50		T22	1		T23	1
all_pins[12]	values[0x1]	1371344	1			T21	54		T24	5		T25	360
all_pins[12]	transitions[0x0=>0x1]	818773	1			T21	32		T24	1		T25	258
all_pins[12]	transitions[0x1=>0x0]	820721	1			T21	19		T24	7		T25	141
all_pins[13]	values[0x0]	2246353	1			T21	58		T22	1		T23	1
all_pins[13]	values[0x1]	1371080	1			T21	46		T24	10		T25	308
all_pins[13]	transitions[0x0=>0x1]	821746	1			T21	24		T24	10		T25	185
all_pins[13]	transitions[0x1=>0x0]	822010	1			T21	32		T24	5		T25	237
all_pins[14]	values[0x0]	2252277	1			T21	52		T22	1		T23	1
all_pins[14]	values[0x1]	1365156	1			T21	52		T24	11		T25	345
all_pins[14]	transitions[0x0=>0x1]	818419	1			T21	31		T24	7		T25	214
all_pins[14]	transitions[0x1=>0x0]	824343	1			T21	25		T24	6		T25	177
all_pins[15]	values[0x0]	2247391	1			T21	62		T22	1		T23	1
all_pins[15]	values[0x1]	1370042	1			T21	42		T24	8		T25	249
all_pins[15]	transitions[0x0=>0x1]	821327	1			T21	20		T24	4		T25	139
all_pins[15]	transitions[0x1=>0x0]	816441	1			T21	30		T24	7		T25	235
all_pins[16]	values[0x0]	2252886	1			T21	54		T22	1		T23	1
all_pins[16]	values[0x1]	1364547	1			T21	50		T24	10		T25	339
all_pins[16]	transitions[0x0=>0x1]	815952	1			T21	33		T24	10		T25	222
all_pins[16]	transitions[0x1=>0x0]	821447	1			T21	25		T24	8		T25	132
all_pins[17]	values[0x0]	2243530	1			T21	40		T22	1		T23	1
all_pins[17]	values[0x1]	1373903	1			T21	64		T24	19		T25	310
all_pins[17]	transitions[0x0=>0x1]	826802	1			T21	33		T24	14		T25	187
all_pins[17]	transitions[0x1=>0x0]	817446	1			T21	19		T24	5		T25	216
all_pins[18]	values[0x0]	2245998	1			T21	46		T22	1		T23	1
all_pins[18]	values[0x1]	1371435	1			T21	58		T24	5		T25	339
all_pins[18]	transitions[0x0=>0x1]	818406	1			T21	20		T24	4		T25	193
all_pins[18]	transitions[0x1=>0x0]	820874	1			T21	26		T24	18		T25	164
all_pins[19]	values[0x0]	2248626	1			T21	54		T22	1		T23	1
all_pins[19]	values[0x1]	1368807	1			T21	50		T25	299		T27	32
all_pins[19]	transitions[0x0=>0x1]	819207	1			T21	24		T25	169		T27	6
all_pins[19]	transitions[0x1=>0x0]	821835	1			T21	32		T24	5		T25	209
all_pins[20]	values[0x0]	2244600	1			T21	49		T22	1		T23	1
all_pins[20]	values[0x1]	1372833	1			T21	55		T24	13		T25	444
all_pins[20]	transitions[0x0=>0x1]	823100	1			T21	29		T24	13		T25	275
all_pins[20]	transitions[0x1=>0x0]	819074	1			T21	24		T25	130		T27	18
all_pins[21]	values[0x0]	2246631	1			T21	48		T22	1		T23	1
all_pins[21]	values[0x1]	1370802	1			T21	56		T24	10		T25	351
all_pins[21]	transitions[0x0=>0x1]	819879	1			T21	25		T24	4		T25	180
all_pins[21]	transitions[0x1=>0x0]	821910	1			T21	24		T24	7		T25	273
all_pins[22]	values[0x0]	2248630	1			T21	53		T22	1		T23	1
all_pins[22]	values[0x1]	1368803	1			T21	51		T24	13		T25	350
all_pins[22]	transitions[0x0=>0x1]	820648	1			T21	27		T24	11		T25	201
all_pins[22]	transitions[0x1=>0x0]	822647	1			T21	32		T24	8		T25	202
all_pins[23]	values[0x0]	2247655	1			T21	49		T22	1		T23	1
all_pins[23]	values[0x1]	1369778	1			T21	55		T24	15		T25	396
all_pins[23]	transitions[0x0=>0x1]	821340	1			T21	30		T24	8		T25	224
all_pins[23]	transitions[0x1=>0x0]	820365	1			T21	26		T24	6		T25	178
all_pins[24]	values[0x0]	2242412	1			T21	50		T22	1		T23	1
all_pins[24]	values[0x1]	1375021	1			T21	54		T24	11		T25	379
all_pins[24]	transitions[0x0=>0x1]	823029	1			T21	22		T24	6		T25	188
all_pins[24]	transitions[0x1=>0x0]	817786	1			T21	23		T24	10		T25	205
all_pins[25]	values[0x0]	2251234	1			T21	55		T22	1		T23	1
all_pins[25]	values[0x1]	1366199	1			T21	49		T24	10		T25	316
all_pins[25]	transitions[0x0=>0x1]	816992	1			T21	28		T24	7		T25	220
all_pins[25]	transitions[0x1=>0x0]	825814	1			T21	33		T24	8		T25	283
all_pins[26]	values[0x0]	2242347	1			T21	39		T22	1		T23	1
all_pins[26]	values[0x1]	1375086	1			T21	65		T24	21		T25	383
all_pins[26]	transitions[0x0=>0x1]	824180	1			T21	37		T24	13		T25	221
all_pins[26]	transitions[0x1=>0x0]	815293	1			T21	21		T24	2		T25	154
all_pins[27]	values[0x0]	2242503	1			T21	53		T22	1		T23	1
all_pins[27]	values[0x1]	1374930	1			T21	51		T24	18		T25	358
all_pins[27]	transitions[0x0=>0x1]	820597	1			T21	17		T24	8		T25	203
all_pins[27]	transitions[0x1=>0x0]	820753	1			T21	31		T24	11		T25	228
all_pins[28]	values[0x0]	2251570	1			T21	50		T22	1		T23	1
all_pins[28]	values[0x1]	1365863	1			T21	54		T24	7		T25	366
all_pins[28]	transitions[0x0=>0x1]	814977	1			T21	29		T24	1		T25	182
all_pins[28]	transitions[0x1=>0x0]	824044	1			T21	26		T24	12		T25	174
all_pins[29]	values[0x0]	2244769	1			T21	53		T22	1		T23	1
all_pins[29]	values[0x1]	1372664	1			T21	51		T24	9		T25	393
all_pins[29]	transitions[0x0=>0x1]	823802	1			T21	26		T24	5		T25	220
all_pins[29]	transitions[0x1=>0x0]	817001	1			T21	29		T24	3		T25	193
all_pins[30]	values[0x0]	2253191	1			T21	53		T22	1		T23	1
all_pins[30]	values[0x1]	1364242	1			T21	51		T24	5		T25	286
all_pins[30]	transitions[0x0=>0x1]	813387	1			T21	25		T24	4		T25	153
all_pins[30]	transitions[0x1=>0x0]	821809	1			T21	25		T24	8		T25	260
all_pins[31]	values[0x0]	2252791	1			T21	56		T22	1		T23	1
all_pins[31]	values[0x1]	1364642	1			T21	48		T24	3		T25	370
all_pins[31]	transitions[0x0=>0x1]	818269	1			T21	28		T24	3		T25	234
all_pins[31]	transitions[0x1=>0x0]	817869	1			T21	31		T24	5		T25	150