Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[1]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[2]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[3]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[4]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[5]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[6]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[7]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[8]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[9]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[10]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[11]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[12]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[13]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[14]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[15]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[16]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[17]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[18]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[19]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[20]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[21]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[22]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[23]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[24]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[25]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[26]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[27]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[28]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[29]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[30]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[31]	12365717	1			T21	56149		T22	876		T23	139

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

223906361

1

T21

887136

T22

20428

T23

909

auto[1]

171796583

1

T21

909632

T22

7604

T23

3539

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

319231438

1

T21

179676

T22

15698

T23

3117

auto[1]

76471506

1

T22

12334

T23

1331

T24

712

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296823113

1

T21

179676

T22

15774

T23

2125

auto[1]

98879831

1

T22

12258

T23

2323

T24

1378

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4439028	1			T21	27223		T22	230		T23	6
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3636552	1			T21	28926		T22	43		T23	47
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1203547	1			T22	180		T23	17		T24	5
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1351398	1			T22	203		T23	3		T24	15
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	547679	1			T23	37		T24	17		T29	6
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1187513	1			T22	220		T23	29		T24	11
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4442331	1			T21	25505		T22	264		T23	8
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3631670	1			T21	30644		T22	47		T23	42
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1200596	1			T22	241		T23	10		T24	5
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1348092	1			T22	160		T23	2		T24	34
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	551384	1			T23	43		T24	17		T29	58
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1191644	1			T22	164		T23	34		T24	10
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4438799	1			T21	27506		T22	257		T23	2
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3633365	1			T21	28643		T22	52		T23	39
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1201359	1			T22	176		T23	14		T24	21
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1343624	1			T22	202		T23	10		T24	34
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	552482	1			T23	62		T24	14		T29	14
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1196088	1			T22	189		T23	12		T24	13
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4445296	1			T21	29158		T22	242		T23	4
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3626166	1			T21	26991		T22	47		T23	51
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1201862	1			T22	212		T23	29		T24	13
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1349257	1			T22	211		T23	1		T24	36
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	549939	1			T23	40		T24	12		T29	36
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1193197	1			T22	164		T23	14		T26	45
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4442573	1			T21	27433		T22	275		T24	77
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3625349	1			T21	28716		T22	50		T23	14
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1206369	1			T22	200		T23	5		T24	14
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1346851	1			T22	194		T23	11		T24	44
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	549612	1			T23	74		T24	4		T29	69
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1194963	1			T22	157		T23	35		T24	3
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4443938	1			T21	30785		T22	254		T23	4
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3630499	1			T21	25364		T22	45		T23	63
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1201552	1			T22	197		T23	19		T24	16
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1349284	1			T22	184		T23	5		T24	12
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	549941	1			T23	44		T24	26		T29	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1190503	1			T22	196		T23	4		T24	26
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4445408	1			T21	26271		T22	235		T23	5
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3629206	1			T21	29878		T22	44		T23	27
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1201867	1			T22	209		T23	24		T24	18
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1347082	1			T22	176		T23	3		T24	12
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	551392	1			T23	42		T24	8		T29	9
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1190762	1			T22	212		T23	38		T24	10
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4453784	1			T21	27969		T22	259		T23	5
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3626941	1			T21	28180		T22	46		T23	44
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1201197	1			T22	159		T23	30		T24	15
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1349706	1			T22	250		T23	4		T24	20
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	547227	1			T23	22		T24	8		T29	63
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1186862	1			T22	162		T23	34		T24	2
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4449197	1			T21	28092		T22	267		T24	128
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3621026	1			T21	28057		T22	42		T23	23
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1203499	1			T22	211		T23	11		T24	20
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1344885	1			T22	182		T23	16		T24	26
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	553080	1			T23	48		T24	11		T29	61
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1194030	1			T22	174		T23	41		T24	13
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4452812	1			T21	27081		T22	219		T23	4
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3619319	1			T21	29068		T22	46		T23	35
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1203274	1			T22	180		T23	29		T24	2
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1346267	1			T22	226		T23	8		T24	38
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	551541	1			T23	38		T24	13		T29	28
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1192504	1			T22	205		T23	25		T24	11
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4443194	1			T21	27046		T22	241		T23	6
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3634186	1			T21	29103		T22	52		T23	38
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1205411	1			T22	200		T23	37		T24	13
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1342173	1			T22	187		T23	1		T24	22
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	549122	1			T23	30		T24	13		T29	24
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1191631	1			T22	196		T23	27		T24	9
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4447329	1			T21	28181		T22	243		T23	6
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3620519	1			T21	27968		T22	54		T23	60
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1199346	1			T22	216		T23	16		T24	25
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1352717	1			T22	178		T23	5		T24	14
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	554606	1			T23	41		T24	10		T29	52
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1191200	1			T22	185		T23	11		T24	5
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4447233	1			T21	29197		T22	280		T23	7
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3625802	1			T21	26952		T22	45		T23	61
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1199714	1			T22	183		T23	21		T24	17
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1348502	1			T22	190		T23	4		T24	38
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	551736	1			T23	38		T24	14		T29	11
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1192730	1			T22	178		T23	8		T24	5
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4443355	1			T21	28507		T22	212		T23	7
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3630237	1			T21	27642		T22	47		T23	51
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1199490	1			T22	217		T23	26		T24	22
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1353174	1			T22	216		T23	1		T24	26
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	551240	1			T23	28		T24	2		T29	40
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1188221	1			T22	184		T23	26		T24	2
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4449222	1			T21	27956		T22	231		T24	82
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3624345	1			T21	28193		T22	46		T23	29
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1200375	1			T22	175		T23	13		T24	13
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1352964	1			T22	190		T23	4		T24	6
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	548684	1			T23	58		T24	2		T29	5
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1190127	1			T22	234		T23	35		T26	58
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4436930	1			T21	28821		T22	266		T23	11
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3635539	1			T21	27328		T22	48		T23	61
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1204436	1			T22	190		T23	20		T24	24
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1346447	1			T22	174		T24	23		T26	54
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	551484	1			T23	39		T24	11		T29	32
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1190881	1			T22	198		T23	8		T24	13
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4455109	1			T21	25776		T22	263		T23	2
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3622634	1			T21	30373		T22	46		T23	38
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1198564	1			T22	151		T23	18		T24	16
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1349660	1			T22	210		T23	6		T24	32
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	553303	1			T23	34		T24	8		T29	49
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1186447	1			T22	206		T23	41		T26	45
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4440378	1			T21	29515		T22	233		T23	5
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3635091	1			T21	26634		T22	47		T23	55
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1192669	1			T22	204		T23	25		T24	6
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1355505	1			T22	216		T23	4		T24	37
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	555571	1			T23	42		T24	14		T29	43
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1186503	1			T22	176		T23	8		T24	7
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4449555	1			T21	26750		T22	255		T23	4
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3629408	1			T21	29399		T22	45		T23	39
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1195725	1			T22	204		T23	23		T24	17
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1355446	1			T22	188		T23	2		T24	12
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	552937	1			T23	61		T24	18		T29	5
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1182646	1			T22	184		T23	10		T24	14
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4456735	1			T21	28156		T22	246		T23	8
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3620223	1			T21	27993		T22	39		T23	63
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1197639	1			T22	199		T23	30		T24	12
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1352625	1			T22	210		T23	1		T24	6
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	550381	1			T23	32		T24	12		T29	52
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1188114	1			T22	182		T23	5		T24	17
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4448245	1			T21	27753		T22	258		T23	4
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3636075	1			T21	28396		T22	41		T23	39
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1200597	1			T22	218		T23	5		T24	10
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1349159	1			T22	152		T23	5		T26	48
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	549056	1			T23	74		T24	13		T29	47
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1182585	1			T22	207		T23	12		T24	5
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4448696	1			T21	28155		T22	245		T23	8
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3624629	1			T21	27994		T22	42		T23	42
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1197130	1			T22	201		T23	16		T24	9
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1350079	1			T22	208		T23	3		T24	42
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	553557	1			T23	53		T24	17		T29	7
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1191626	1			T22	180		T23	17		T24	8
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4457563	1			T21	26893		T22	222		T23	7
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3619104	1			T21	29256		T22	47		T23	31
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1199972	1			T22	188		T23	7		T24	3
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1351947	1			T22	183		T23	4		T24	13
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	549180	1			T23	80		T24	15		T29	18
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1187951	1			T22	236		T23	10		T26	49
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4432996	1			T21	27849		T22	284		T23	5
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3641064	1			T21	28300		T22	44		T23	35
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1202700	1			T22	188		T23	22		T24	4
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1348997	1			T22	184		T23	6		T24	21
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	552537	1			T23	44		T24	17		T29	22
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1187423	1			T22	176		T23	27		T24	6
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4449008	1			T21	29788		T22	234		T23	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3628889	1			T21	26361		T22	53		T23	34
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1200966	1			T22	181		T23	8		T24	1
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1345392	1			T22	176		T23	6		T24	13
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	551338	1			T23	50		T24	6		T29	55
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1190124	1			T22	232		T23	40		T24	7
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4445099	1			T21	25694		T22	226		T23	4
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3632549	1			T21	30455		T22	59		T23	56
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1198565	1			T22	227		T23	14		T24	4
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1352655	1			T22	194		T23	4		T24	17
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	550803	1			T23	46		T24	24		T29	47
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1186046	1			T22	170		T23	15		T24	23
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4452248	1			T21	28408		T22	257		T23	5
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3626677	1			T21	27741		T22	50		T23	54
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1196699	1			T22	161		T23	53		T24	18
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1349508	1			T22	208		T23	1		T24	14
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	551883	1			T23	17		T24	4		T45	3
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1188702	1			T22	200		T23	9		T24	16
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4445109	1			T21	26293		T22	252		T23	3
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3636196	1			T21	29856		T22	49		T23	34
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1197543	1			T22	192		T23	26		T24	13
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1349304	1			T22	178		T23	5		T24	15
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	550701	1			T23	54		T24	14		T29	6
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1186864	1			T22	205		T23	17		T24	9
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4452770	1			T21	28022		T22	249		T23	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3626329	1			T21	28127		T22	54		T23	48
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1205296	1			T22	218		T23	27		T24	24
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1347614	1			T22	161		T23	8		T24	20
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	551945	1			T23	44		T24	15		T29	56
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1181763	1			T22	194		T23	10		T24	6
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4452180	1			T21	27488		T22	304		T23	2
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3623017	1			T21	28661		T22	53		T23	45
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1201321	1			T22	188		T23	11		T24	22
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1353046	1			T22	194		T23	7		T24	25
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	550631	1			T23	47		T24	10		T29	54
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1185522	1			T22	137		T23	27		T24	3
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4455980	1			T21	26315		T22	271		T23	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3621515	1			T21	29834		T22	46		T23	23
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1199705	1			T22	188		T23	6		T24	15
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1348364	1			T22	179		T23	7		T24	27
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	551147	1			T23	48		T24	12		T29	51
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1189006	1			T22	192		T23	54		T24	8
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4440217	1			T21	27550		T22	242		T23	3
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3628006	1			T21	28599		T22	45		T23	46
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1199684	1			T22	190		T23	7		T24	20
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1353651	1			T22	204		T23	4		T24	17
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	555500	1			T23	50		T24	11		T45	20
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1188659	1			T22	195		T23	29		T24	13

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal