Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[1]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[2]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[3]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[4]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[5]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[6]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[7]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[8]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[9]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[10]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[11]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[12]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[13]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[14]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[15]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[16]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[17]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[18]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[19]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[20]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[21]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[22]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[23]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[24]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[25]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[26]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[27]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[28]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[29]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[30]	12365717	1			T21	56149		T22	876		T23	139
bins_for_gpio_bits[31]	12365717	1			T21	56149		T22	876		T23	139

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

223906361

1

T21

887136

T22

20428

T23

909

auto[1]

171796583

1

T21

909632

T22

7604

T23

3539

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

223901302

1

T21

887136

T22

20420

T23

918

auto[1]

171801642

1

T21

909632

T22

7612

T23

3530

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6779324	1			T21	27223		T22	561		T23	23
bins_for_gpio_bits[0]	auto[0]	auto[1]	214515	1			T22	52		T23	3		T24	1
bins_for_gpio_bits[0]	auto[1]	auto[0]	214649	1			T22	52		T23	3		T24	1
bins_for_gpio_bits[0]	auto[1]	auto[1]	5157229	1			T21	28926		T22	211		T23	110
bins_for_gpio_bits[1]	auto[0]	auto[0]	6776319	1			T21	25505		T22	622		T23	18
bins_for_gpio_bits[1]	auto[0]	auto[1]	214535	1			T22	43		T23	2		T24	1
bins_for_gpio_bits[1]	auto[1]	auto[0]	214700	1			T22	43		T23	2		T24	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	5160163	1			T21	30644		T22	168		T23	117
bins_for_gpio_bits[2]	auto[0]	auto[0]	6769379	1			T21	27506		T22	581		T23	23
bins_for_gpio_bits[2]	auto[0]	auto[1]	214278	1			T22	53		T23	3		T26	15
bins_for_gpio_bits[2]	auto[1]	auto[0]	214403	1			T22	54		T23	3		T24	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	5167657	1			T21	28643		T22	188		T23	110
bins_for_gpio_bits[3]	auto[0]	auto[0]	6781763	1			T21	29158		T22	616		T23	29
bins_for_gpio_bits[3]	auto[0]	auto[1]	214518	1			T22	49		T23	5		T26	12
bins_for_gpio_bits[3]	auto[1]	auto[0]	214652	1			T22	49		T23	5		T26	13
bins_for_gpio_bits[3]	auto[1]	auto[1]	5154784	1			T21	26991		T22	162		T23	100
bins_for_gpio_bits[4]	auto[0]	auto[0]	6780814	1			T21	27433		T22	625		T23	15
bins_for_gpio_bits[4]	auto[0]	auto[1]	214835	1			T22	43		T23	1		T26	14
bins_for_gpio_bits[4]	auto[1]	auto[0]	214979	1			T22	44		T23	1		T26	15
bins_for_gpio_bits[4]	auto[1]	auto[1]	5155089	1			T21	28716		T22	164		T23	122
bins_for_gpio_bits[5]	auto[0]	auto[0]	6780249	1			T21	30785		T22	587		T23	26
bins_for_gpio_bits[5]	auto[0]	auto[1]	214350	1			T22	48		T23	3		T26	13
bins_for_gpio_bits[5]	auto[1]	auto[0]	214525	1			T22	48		T23	2		T24	2
bins_for_gpio_bits[5]	auto[1]	auto[1]	5156593	1			T21	25364		T22	193		T23	108
bins_for_gpio_bits[6]	auto[0]	auto[0]	6779914	1			T21	26271		T22	576		T23	29
bins_for_gpio_bits[6]	auto[0]	auto[1]	214298	1			T22	44		T23	3		T26	14
bins_for_gpio_bits[6]	auto[1]	auto[0]	214443	1			T22	44		T23	3		T26	15
bins_for_gpio_bits[6]	auto[1]	auto[1]	5157062	1			T21	29878		T22	212		T23	104
bins_for_gpio_bits[7]	auto[0]	auto[0]	6790323	1			T21	27969		T22	626		T23	35
bins_for_gpio_bits[7]	auto[0]	auto[1]	214247	1			T22	42		T23	5		T26	16
bins_for_gpio_bits[7]	auto[1]	auto[0]	214364	1			T22	42		T23	4		T24	1
bins_for_gpio_bits[7]	auto[1]	auto[1]	5146783	1			T21	28180		T22	166		T23	95
bins_for_gpio_bits[8]	auto[0]	auto[0]	6782772	1			T21	28092		T22	607		T23	25
bins_for_gpio_bits[8]	auto[0]	auto[1]	214657	1			T22	53		T23	2		T26	17
bins_for_gpio_bits[8]	auto[1]	auto[0]	214809	1			T22	53		T23	2		T24	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	5153479	1			T21	28057		T22	163		T23	110
bins_for_gpio_bits[9]	auto[0]	auto[0]	6787550	1			T21	27081		T22	573		T23	38
bins_for_gpio_bits[9]	auto[0]	auto[1]	214622	1			T22	51		T23	3		T24	1
bins_for_gpio_bits[9]	auto[1]	auto[0]	214803	1			T22	52		T23	3		T24	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	5148742	1			T21	29068		T22	200		T23	95
bins_for_gpio_bits[10]	auto[0]	auto[0]	6775954	1			T21	27046		T22	585		T23	40
bins_for_gpio_bits[10]	auto[0]	auto[1]	214632	1			T22	43		T23	5		T26	12
bins_for_gpio_bits[10]	auto[1]	auto[0]	214824	1			T22	43		T23	4		T26	12
bins_for_gpio_bits[10]	auto[1]	auto[1]	5160307	1			T21	29103		T22	205		T23	90
bins_for_gpio_bits[11]	auto[0]	auto[0]	6785015	1			T21	28181		T22	585		T23	25
bins_for_gpio_bits[11]	auto[0]	auto[1]	214199	1			T22	51		T23	2		T26	14
bins_for_gpio_bits[11]	auto[1]	auto[0]	214377	1			T22	52		T23	2		T26	14
bins_for_gpio_bits[11]	auto[1]	auto[1]	5152126	1			T21	27968		T22	188		T23	110
bins_for_gpio_bits[12]	auto[0]	auto[0]	6781156	1			T21	29197		T22	607		T23	28
bins_for_gpio_bits[12]	auto[0]	auto[1]	214066	1			T22	46		T23	4		T26	15
bins_for_gpio_bits[12]	auto[1]	auto[0]	214293	1			T22	46		T23	4		T26	15
bins_for_gpio_bits[12]	auto[1]	auto[1]	5156202	1			T21	26952		T22	177		T23	103
bins_for_gpio_bits[13]	auto[0]	auto[0]	6781783	1			T21	28507		T22	591		T23	29
bins_for_gpio_bits[13]	auto[0]	auto[1]	214047	1			T22	54		T23	5		T26	11
bins_for_gpio_bits[13]	auto[1]	auto[0]	214236	1			T22	54		T23	5		T24	1
bins_for_gpio_bits[13]	auto[1]	auto[1]	5155651	1			T21	27642		T22	177		T23	100
bins_for_gpio_bits[14]	auto[0]	auto[0]	6787823	1			T21	27956		T22	551		T23	15
bins_for_gpio_bits[14]	auto[0]	auto[1]	214614	1			T22	45		T23	3		T26	13
bins_for_gpio_bits[14]	auto[1]	auto[0]	214738	1			T22	45		T23	2		T26	13
bins_for_gpio_bits[14]	auto[1]	auto[1]	5148542	1			T21	28193		T22	235		T23	119
bins_for_gpio_bits[15]	auto[0]	auto[0]	6773481	1			T21	28821		T22	582		T23	28
bins_for_gpio_bits[15]	auto[0]	auto[1]	214153	1			T22	48		T23	4		T24	1
bins_for_gpio_bits[15]	auto[1]	auto[0]	214332	1			T22	48		T23	3		T24	2
bins_for_gpio_bits[15]	auto[1]	auto[1]	5163751	1			T21	27328		T22	198		T23	104
bins_for_gpio_bits[16]	auto[0]	auto[0]	6788802	1			T21	25776		T22	572		T23	22
bins_for_gpio_bits[16]	auto[0]	auto[1]	214360	1			T22	52		T23	4		T26	11
bins_for_gpio_bits[16]	auto[1]	auto[0]	214531	1			T22	52		T23	4		T26	12
bins_for_gpio_bits[16]	auto[1]	auto[1]	5148024	1			T21	30373		T22	200		T23	109
bins_for_gpio_bits[17]	auto[0]	auto[0]	6774215	1			T21	29515		T22	603		T23	31
bins_for_gpio_bits[17]	auto[0]	auto[1]	214201	1			T22	50		T23	3		T24	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	214337	1			T22	50		T23	3		T24	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	5162964	1			T21	26634		T22	173		T23	102
bins_for_gpio_bits[18]	auto[0]	auto[0]	6786673	1			T21	26750		T22	602		T23	25
bins_for_gpio_bits[18]	auto[0]	auto[1]	213866	1			T22	45		T23	4		T24	2
bins_for_gpio_bits[18]	auto[1]	auto[0]	214053	1			T22	45		T23	4		T24	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	5151125	1			T21	29399		T22	184		T23	106
bins_for_gpio_bits[19]	auto[0]	auto[0]	6791976	1			T21	28156		T22	608		T23	35
bins_for_gpio_bits[19]	auto[0]	auto[1]	214874	1			T22	47		T23	4		T26	8
bins_for_gpio_bits[19]	auto[1]	auto[0]	215023	1			T22	47		T23	4		T26	9
bins_for_gpio_bits[19]	auto[1]	auto[1]	5143844	1			T21	27993		T22	174		T23	96
bins_for_gpio_bits[20]	auto[0]	auto[0]	6783380	1			T21	27753		T22	577		T23	14
bins_for_gpio_bits[20]	auto[0]	auto[1]	214481	1			T22	50		T23	1		T26	13
bins_for_gpio_bits[20]	auto[1]	auto[0]	214621	1			T22	51		T26	14		T29	3
bins_for_gpio_bits[20]	auto[1]	auto[1]	5153235	1			T21	28396		T22	198		T23	124
bins_for_gpio_bits[21]	auto[0]	auto[0]	6781008	1			T21	28155		T22	602		T23	24
bins_for_gpio_bits[21]	auto[0]	auto[1]	214752	1			T22	52		T23	4		T24	1
bins_for_gpio_bits[21]	auto[1]	auto[0]	214897	1			T22	52		T23	3		T24	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	5155060	1			T21	27994		T22	170		T23	108
bins_for_gpio_bits[22]	auto[0]	auto[0]	6794563	1			T21	26893		T22	538		T23	17
bins_for_gpio_bits[22]	auto[0]	auto[1]	214772	1			T22	55		T23	2		T26	12
bins_for_gpio_bits[22]	auto[1]	auto[0]	214919	1			T22	55		T23	1		T26	13
bins_for_gpio_bits[22]	auto[1]	auto[1]	5141463	1			T21	29256		T22	228		T23	119
bins_for_gpio_bits[23]	auto[0]	auto[0]	6769969	1			T21	27849		T22	610		T23	28
bins_for_gpio_bits[23]	auto[0]	auto[1]	214602	1			T22	46		T23	5		T26	15
bins_for_gpio_bits[23]	auto[1]	auto[0]	214724	1			T22	46		T23	5		T26	15
bins_for_gpio_bits[23]	auto[1]	auto[1]	5166422	1			T21	28300		T22	174		T23	101
bins_for_gpio_bits[24]	auto[0]	auto[0]	6780690	1			T21	29788		T22	539		T23	13
bins_for_gpio_bits[24]	auto[0]	auto[1]	214537	1			T22	52		T23	2		T26	17
bins_for_gpio_bits[24]	auto[1]	auto[0]	214676	1			T22	52		T23	2		T26	17
bins_for_gpio_bits[24]	auto[1]	auto[1]	5155814	1			T21	26361		T22	233		T23	122
bins_for_gpio_bits[25]	auto[0]	auto[0]	6781707	1			T21	25694		T22	600		T23	19
bins_for_gpio_bits[25]	auto[0]	auto[1]	214461	1			T22	47		T23	3		T26	16
bins_for_gpio_bits[25]	auto[1]	auto[0]	214612	1			T22	47		T23	3		T26	16
bins_for_gpio_bits[25]	auto[1]	auto[1]	5154937	1			T21	30455		T22	182		T23	114
bins_for_gpio_bits[26]	auto[0]	auto[0]	6783773	1			T21	28408		T22	581		T23	52
bins_for_gpio_bits[26]	auto[0]	auto[1]	214539	1			T22	45		T23	7		T26	16
bins_for_gpio_bits[26]	auto[1]	auto[0]	214682	1			T22	45		T23	7		T26	17
bins_for_gpio_bits[26]	auto[1]	auto[1]	5152723	1			T21	27741		T22	205		T23	73
bins_for_gpio_bits[27]	auto[0]	auto[0]	6776991	1			T21	26293		T22	567		T23	29
bins_for_gpio_bits[27]	auto[0]	auto[1]	214821	1			T22	54		T23	5		T26	14
bins_for_gpio_bits[27]	auto[1]	auto[0]	214965	1			T22	55		T23	5		T26	14
bins_for_gpio_bits[27]	auto[1]	auto[1]	5158940	1			T21	29856		T22	200		T23	100
bins_for_gpio_bits[28]	auto[0]	auto[0]	6791017	1			T21	28022		T22	584		T23	33
bins_for_gpio_bits[28]	auto[0]	auto[1]	214443	1			T22	44		T23	4		T26	15
bins_for_gpio_bits[28]	auto[1]	auto[0]	214663	1			T22	44		T23	4		T26	15
bins_for_gpio_bits[28]	auto[1]	auto[1]	5145594	1			T21	28127		T22	204		T23	98
bins_for_gpio_bits[29]	auto[0]	auto[0]	6791934	1			T21	27488		T22	642		T23	18
bins_for_gpio_bits[29]	auto[0]	auto[1]	214421	1			T22	43		T23	2		T26	9
bins_for_gpio_bits[29]	auto[1]	auto[0]	214613	1			T22	44		T23	2		T26	9
bins_for_gpio_bits[29]	auto[1]	auto[1]	5144749	1			T21	28661		T22	147		T23	117
bins_for_gpio_bits[30]	auto[0]	auto[0]	6789433	1			T21	26315		T22	601		T23	12
bins_for_gpio_bits[30]	auto[0]	auto[1]	214439	1			T22	37		T23	2		T26	14
bins_for_gpio_bits[30]	auto[1]	auto[0]	214616	1			T22	37		T23	2		T26	14
bins_for_gpio_bits[30]	auto[1]	auto[1]	5147229	1			T21	29834		T22	201		T23	123
bins_for_gpio_bits[31]	auto[0]	auto[0]	6778558	1			T21	27550		T22	585		T23	13
bins_for_gpio_bits[31]	auto[0]	auto[1]	214859	1			T22	50		T23	2		T24	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	214994	1			T22	51		T23	1		T24	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	5157306	1			T21	28599		T22	190		T23	123