Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7418107 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
5115260 |
1 |
|
|
T24 |
31 |
|
T25 |
1251 |
|
T27 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11876486 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
656881 |
1 |
|
|
T24 |
1 |
|
T25 |
188 |
|
T27 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7421264 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
5112103 |
1 |
|
|
T24 |
23 |
|
T25 |
967 |
|
T27 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2232328 |
1 |
|
|
T24 |
22 |
|
T25 |
407 |
|
T27 |
9 |
| auto[1] |
auto[0] |
auto[1] |
329111 |
1 |
|
|
T24 |
1 |
|
T25 |
103 |
|
T27 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2222894 |
1 |
|
|
T25 |
372 |
|
T27 |
17 |
|
T30 |
11 |
| auto[1] |
auto[1] |
auto[1] |
327770 |
1 |
|
|
T25 |
85 |
|
T61 |
80 |
|
T31 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |