Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7405189 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
5128178 |
1 |
|
|
T24 |
35 |
|
T25 |
984 |
|
T27 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11880915 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
652452 |
1 |
|
|
T24 |
1 |
|
T25 |
231 |
|
T61 |
115 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7443167 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
5090200 |
1 |
|
|
T24 |
20 |
|
T25 |
1147 |
|
T27 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2231367 |
1 |
|
|
T24 |
12 |
|
T25 |
619 |
|
T27 |
19 |
| auto[1] |
auto[0] |
auto[1] |
328308 |
1 |
|
|
T24 |
1 |
|
T25 |
144 |
|
T61 |
45 |
| auto[1] |
auto[1] |
auto[0] |
2206381 |
1 |
|
|
T24 |
7 |
|
T25 |
297 |
|
T27 |
17 |
| auto[1] |
auto[1] |
auto[1] |
324144 |
1 |
|
|
T25 |
87 |
|
T61 |
70 |
|
T44 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |