Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7391269 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
5142098 |
1 |
|
|
T24 |
8 |
|
T25 |
1272 |
|
T27 |
31 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10303178 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
2230189 |
1 |
|
|
T24 |
10 |
|
T25 |
593 |
|
T27 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7425393 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
5107974 |
1 |
|
|
T24 |
15 |
|
T25 |
1171 |
|
T27 |
58 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1441556 |
1 |
|
|
T24 |
5 |
|
T25 |
282 |
|
T27 |
27 |
| auto[1] |
auto[0] |
auto[1] |
1116239 |
1 |
|
|
T24 |
10 |
|
T25 |
285 |
|
T27 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1436229 |
1 |
|
|
T25 |
296 |
|
T27 |
20 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1113950 |
1 |
|
|
T25 |
308 |
|
T27 |
4 |
|
T61 |
269 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |