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Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7405963 1 T21 56149 T22 486 T23 69
auto[1] 5127404 1 T24 44 T25 1188 T27 42


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10281842 1 T21 56149 T22 486 T23 69
auto[1] 2251525 1 T25 544 T27 33 T30 4


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7380882 1 T21 56149 T22 486 T23 69
auto[1] 5152485 1 T24 10 T25 1009 T27 34


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1455340 1 T24 8 T25 254 T27 1
auto[1] auto[0] auto[1] 1129545 1 T25 297 T27 14 T30 4
auto[1] auto[1] auto[0] 1445620 1 T24 2 T25 211 T61 161
auto[1] auto[1] auto[1] 1121980 1 T25 247 T27 19 T61 175


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded

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