Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7398309 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
5135058 |
1 |
|
|
T24 |
49 |
|
T25 |
1568 |
|
T27 |
43 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10301163 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
2232204 |
1 |
|
|
T24 |
10 |
|
T25 |
618 |
|
T27 |
33 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7410234 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
5123133 |
1 |
|
|
T24 |
17 |
|
T25 |
1295 |
|
T27 |
33 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1442159 |
1 |
|
|
T24 |
7 |
|
T25 |
260 |
|
T61 |
107 |
| auto[1] |
auto[0] |
auto[1] |
1117660 |
1 |
|
|
T24 |
6 |
|
T25 |
218 |
|
T27 |
15 |
| auto[1] |
auto[1] |
auto[0] |
1448770 |
1 |
|
|
T25 |
417 |
|
T61 |
176 |
|
T31 |
4 |
| auto[1] |
auto[1] |
auto[1] |
1114544 |
1 |
|
|
T24 |
4 |
|
T25 |
400 |
|
T27 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |